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Blame information for rev 6

Line No.	Rev	Author	Line
1	6	kaklik	`/! \file enc28j60.h \brief Microchip ENC28J60 Ethernet Interface Driver. /`
2			`//*****************************************************************************`
3			`//`
4			`// File Name : 'enc28j60.h'`
5			`// Title : Microchip ENC28J60 Ethernet Interface Driver`
6			`// Author : Pascal Stang (c)2005`
7			`// Created : 9/22/2005`
8			`// Revised : 9/22/2005`
9			`// Version : 0.1`
10			`// Target MCU : Atmel AVR series`
11			`// Editor Tabs : 4`
12			`//`
13			`/// \ingroup network`
14			`/// \defgroup enc28j60 Microchip ENC28J60 Ethernet Interface Driver (enc28j60.c)`
15			`/// \code #include "net/enc28j60.h" \endcode`
16			`/// \par Overview`
17			`/// This driver provides initialization and transmit/receive`
18			`/// functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY.`
19			`/// This chip is novel in that it is a full MAC+PHY interface all in a 28-pin`
20			`/// chip, using an SPI interface to the host processor.`
21			`///`
22			`//`
23			`//*****************************************************************************`
24			`//@{`
25
26			`#ifndef ENC28J60_H`
27			`#define ENC28J60_H`
28
29			`#include "global.h"`
30
31			`#define nop() asm volatile ("nop")`
32
33			`// ENC28J60 Control Registers`
34			`// Control register definitions are a combination of address,`
35			`// bank number, and Ethernet/MAC/PHY indicator bits.`
36			`// - Register address (bits 0-4)`
37			`// - Bank number (bits 5-6)`
38			`// - MAC/PHY indicator (bit 7)`
39			`#define ADDR_MASK 0x1F`
40			`#define BANK_MASK 0x60`
41			`#define SPRD_MASK 0x80`
42			`// All-bank registers`
43			`#define EIE 0x1B`
44			`#define EIR 0x1C`
45			`#define ESTAT 0x1D`
46			`#define ECON2 0x1E`
47			`#define ECON1 0x1F`
48			`// Bank 0 registers`
49			`#define ERDPTL (0x00\|0x00)`
50			`#define ERDPTH (0x01\|0x00)`
51			`#define EWRPTL (0x02\|0x00)`
52			`#define EWRPTH (0x03\|0x00)`
53			`#define ETXSTL (0x04\|0x00)`
54			`#define ETXSTH (0x05\|0x00)`
55			`#define ETXNDL (0x06\|0x00)`
56			`#define ETXNDH (0x07\|0x00)`
57			`#define ERXSTL (0x08\|0x00)`
58			`#define ERXSTH (0x09\|0x00)`
59			`#define ERXNDL (0x0A\|0x00)`
60			`#define ERXNDH (0x0B\|0x00)`
61			`#define ERXRDPTL (0x0C\|0x00)`
62			`#define ERXRDPTH (0x0D\|0x00)`
63			`#define ERXWRPTL (0x0E\|0x00)`
64			`#define ERXWRPTH (0x0F\|0x00)`
65			`#define EDMASTL (0x10\|0x00)`
66			`#define EDMASTH (0x11\|0x00)`
67			`#define EDMANDL (0x12\|0x00)`
68			`#define EDMANDH (0x13\|0x00)`
69			`#define EDMADSTL (0x14\|0x00)`
70			`#define EDMADSTH (0x15\|0x00)`
71			`#define EDMACSL (0x16\|0x00)`
72			`#define EDMACSH (0x17\|0x00)`
73			`// Bank 1 registers`
74			`#define EHT0 (0x00\|0x20)`
75			`#define EHT1 (0x01\|0x20)`
76			`#define EHT2 (0x02\|0x20)`
77			`#define EHT3 (0x03\|0x20)`
78			`#define EHT4 (0x04\|0x20)`
79			`#define EHT5 (0x05\|0x20)`
80			`#define EHT6 (0x06\|0x20)`
81			`#define EHT7 (0x07\|0x20)`
82			`#define EPMM0 (0x08\|0x20)`
83			`#define EPMM1 (0x09\|0x20)`
84			`#define EPMM2 (0x0A\|0x20)`
85			`#define EPMM3 (0x0B\|0x20)`
86			`#define EPMM4 (0x0C\|0x20)`
87			`#define EPMM5 (0x0D\|0x20)`
88			`#define EPMM6 (0x0E\|0x20)`
89			`#define EPMM7 (0x0F\|0x20)`
90			`#define EPMCSL (0x10\|0x20)`
91			`#define EPMCSH (0x11\|0x20)`
92			`#define EPMOL (0x14\|0x20)`
93			`#define EPMOH (0x15\|0x20)`
94			`#define EWOLIE (0x16\|0x20)`
95			`#define EWOLIR (0x17\|0x20)`
96			`#define ERXFCON (0x18\|0x20)`
97			`#define EPKTCNT (0x19\|0x20)`
98			`// Bank 2 registers`
99			`#define MACON1 (0x00\|0x40\|0x80)`
100			`#define MACON2 (0x01\|0x40\|0x80)`
101			`#define MACON3 (0x02\|0x40\|0x80)`
102			`#define MACON4 (0x03\|0x40\|0x80)`
103			`#define MABBIPG (0x04\|0x40\|0x80)`
104			`#define MAIPGL (0x06\|0x40\|0x80)`
105			`#define MAIPGH (0x07\|0x40\|0x80)`
106			`#define MACLCON1 (0x08\|0x40\|0x80)`
107			`#define MACLCON2 (0x09\|0x40\|0x80)`
108			`#define MAMXFLL (0x0A\|0x40\|0x80)`
109			`#define MAMXFLH (0x0B\|0x40\|0x80)`
110			`#define MAPHSUP (0x0D\|0x40\|0x80)`
111			`#define MICON (0x11\|0x40\|0x80)`
112			`#define MICMD (0x12\|0x40\|0x80)`
113			`#define MIREGADR (0x14\|0x40\|0x80)`
114			`#define MIWRL (0x16\|0x40\|0x80)`
115			`#define MIWRH (0x17\|0x40\|0x80)`
116			`#define MIRDL (0x18\|0x40\|0x80)`
117			`#define MIRDH (0x19\|0x40\|0x80)`
118			`// Bank 3 registers`
119			`#define MAADR1 (0x00\|0x60\|0x80)`
120			`#define MAADR0 (0x01\|0x60\|0x80)`
121			`#define MAADR3 (0x02\|0x60\|0x80)`
122			`#define MAADR2 (0x03\|0x60\|0x80)`
123			`#define MAADR5 (0x04\|0x60\|0x80)`
124			`#define MAADR4 (0x05\|0x60\|0x80)`
125			`#define EBSTSD (0x06\|0x60)`
126			`#define EBSTCON (0x07\|0x60)`
127			`#define EBSTCSL (0x08\|0x60)`
128			`#define EBSTCSH (0x09\|0x60)`
129			`#define MISTAT (0x0A\|0x60\|0x80)`
130			`#define EREVID (0x12\|0x60)`
131			`#define ECOCON (0x15\|0x60)`
132			`#define EFLOCON (0x17\|0x60)`
133			`#define EPAUSL (0x18\|0x60)`
134			`#define EPAUSH (0x19\|0x60)`
135			`// PHY registers`
136			`#define PHCON1 0x00`
137			`#define PHSTAT1 0x01`
138			`#define PHHID1 0x02`
139			`#define PHHID2 0x03`
140			`#define PHCON2 0x10`
141			`#define PHSTAT2 0x11`
142			`#define PHIE 0x12`
143			`#define PHIR 0x13`
144			`#define PHLCON 0x14`
145
146			`// ENC28J60 EIE Register Bit Definitions`
147			`#define EIE_INTIE 0x80`
148			`#define EIE_PKTIE 0x40`
149			`#define EIE_DMAIE 0x20`
150			`#define EIE_LINKIE 0x10`
151			`#define EIE_TXIE 0x08`
152			`#define EIE_WOLIE 0x04`
153			`#define EIE_TXERIE 0x02`
154			`#define EIE_RXERIE 0x01`
155			`// ENC28J60 EIR Register Bit Definitions`
156			`#define EIR_PKTIF 0x40`
157			`#define EIR_DMAIF 0x20`
158			`#define EIR_LINKIF 0x10`
159			`#define EIR_TXIF 0x08`
160			`#define EIR_WOLIF 0x04`
161			`#define EIR_TXERIF 0x02`
162			`#define EIR_RXERIF 0x01`
163			`// ENC28J60 ESTAT Register Bit Definitions`
164			`#define ESTAT_INT 0x80`
165			`#define ESTAT_LATECOL 0x10`
166			`#define ESTAT_RXBUSY 0x04`
167			`#define ESTAT_TXABRT 0x02`
168			`#define ESTAT_CLKRDY 0x01`
169			`// ENC28J60 ECON2 Register Bit Definitions`
170			`#define ECON2_AUTOINC 0x80`
171			`#define ECON2_PKTDEC 0x40`
172			`#define ECON2_PWRSV 0x20`
173			`#define ECON2_VRPS 0x08`
174			`// ENC28J60 ECON1 Register Bit Definitions`
175			`#define ECON1_TXRST 0x80`
176			`#define ECON1_RXRST 0x40`
177			`#define ECON1_DMAST 0x20`
178			`#define ECON1_CSUMEN 0x10`
179			`#define ECON1_TXRTS 0x08`
180			`#define ECON1_RXEN 0x04`
181			`#define ECON1_BSEL1 0x02`
182			`#define ECON1_BSEL0 0x01`
183			`// ENC28J60 MACON1 Register Bit Definitions`
184			`#define MACON1_LOOPBK 0x10`
185			`#define MACON1_TXPAUS 0x08`
186			`#define MACON1_RXPAUS 0x04`
187			`#define MACON1_PASSALL 0x02`
188			`#define MACON1_MARXEN 0x01`
189			`// ENC28J60 MACON2 Register Bit Definitions`
190			`#define MACON2_MARST 0x80`
191			`#define MACON2_RNDRST 0x40`
192			`#define MACON2_MARXRST 0x08`
193			`#define MACON2_RFUNRST 0x04`
194			`#define MACON2_MATXRST 0x02`
195			`#define MACON2_TFUNRST 0x01`
196			`// ENC28J60 MACON3 Register Bit Definitions`
197			`#define MACON3_PADCFG2 0x80`
198			`#define MACON3_PADCFG1 0x40`
199			`#define MACON3_PADCFG0 0x20`
200			`#define MACON3_TXCRCEN 0x10`
201			`#define MACON3_PHDRLEN 0x08`
202			`#define MACON3_HFRMLEN 0x04`
203			`#define MACON3_FRMLNEN 0x02`
204			`#define MACON3_FULDPX 0x01`
205			`// ENC28J60 MICMD Register Bit Definitions`
206			`#define MICMD_MIISCAN 0x02`
207			`#define MICMD_MIIRD 0x01`
208			`// ENC28J60 MISTAT Register Bit Definitions`
209			`#define MISTAT_NVALID 0x04`
210			`#define MISTAT_SCAN 0x02`
211			`#define MISTAT_BUSY 0x01`
212			`// ENC28J60 PHY PHCON1 Register Bit Definitions`
213			`#define PHCON1_PRST 0x8000`
214			`#define PHCON1_PLOOPBK 0x4000`
215			`#define PHCON1_PPWRSV 0x0800`
216			`#define PHCON1_PDPXMD 0x0100`
217			`// ENC28J60 PHY PHSTAT1 Register Bit Definitions`
218			`#define PHSTAT1_PFDPX 0x1000`
219			`#define PHSTAT1_PHDPX 0x0800`
220			`#define PHSTAT1_LLSTAT 0x0004`
221			`#define PHSTAT1_JBSTAT 0x0002`
222			`// ENC28J60 PHY PHCON2 Register Bit Definitions`
223			`#define PHCON2_FRCLINK 0x4000`
224			`#define PHCON2_TXDIS 0x2000`
225			`#define PHCON2_JABBER 0x0400`
226			`#define PHCON2_HDLDIS 0x0100`
227
228			`// ENC28J60 Packet Control Byte Bit Definitions`
229			`#define PKTCTRL_PHUGEEN 0x08`
230			`#define PKTCTRL_PPADEN 0x04`
231			`#define PKTCTRL_PCRCEN 0x02`
232			`#define PKTCTRL_POVERRIDE 0x01`
233
234			`// SPI operation codes`
235			`#define ENC28J60_READ_CTRL_REG 0x00`
236			`#define ENC28J60_READ_BUF_MEM 0x3A`
237			`#define ENC28J60_WRITE_CTRL_REG 0x40`
238			`#define ENC28J60_WRITE_BUF_MEM 0x7A`
239			`#define ENC28J60_BIT_FIELD_SET 0x80`
240			`#define ENC28J60_BIT_FIELD_CLR 0xA0`
241			`#define ENC28J60_SOFT_RESET 0xFF`
242
243
244			`// buffer boundaries applied to internal 8K ram`
245			`// entire available packet buffer space is allocated`
246			`#define TXSTART_INIT 0x0000 // start TX buffer at 0`
247			`#define RXSTART_INIT 0x0600 // give TX buffer space for one full ethernet frame (~1500 bytes)`
248			`#define RXSTOP_INIT 0x1FFF // receive buffer gets the rest`
249
250			`#define MAX_FRAMELEN 1518 // maximum ethernet frame length`
251
252			`// Ethernet constants`
253			`#define ETHERNET_MIN_PACKET_LENGTH 0x3C`
254			`//#define ETHERNET_HEADER_LENGTH 0x0E`
255
256			`// functions`
257			`#include "nic.h"`
258
259			`// setup ports for I/O`
260			`//void ax88796SetupPorts(void);`
261
262			`//! do a ENC28J60 read operation`
263			`u08 enc28j60ReadOp(u08 op, u08 address);`
264			`//! do a ENC28J60 write operation`
265			`void enc28j60WriteOp(u08 op, u08 address, u08 data);`
266			`//! read the packet buffer memory`
267			`void enc28j60ReadBuffer(u16 len, u08* data);`
268			`//! write the packet buffer memory`
269			`void enc28j60WriteBuffer(u16 len, u08* data);`
270			`//! set the register bank for register at address`
271			`void enc28j60SetBank(u08 address);`
272			`//! read ax88796 register`
273			`u08 enc28j60Read(u08 address);`
274			`//! write ax88796 register`
275			`void enc28j60Write(u08 address, u08 data);`
276			`//! read a PHY register`
277			`u16 enc28j60PhyRead(u08 address);`
278			`//! write a PHY register`
279			`void enc28j60PhyWrite(u08 address, u16 data);`
280
281			`//! initialize the ethernet interface for transmit/receive`
282			`void enc28j60Init(void);`
283
284			`//! Packet transmit function.`
285			`/// Sends a packet on the network. It is assumed that the packet is headed by a valid ethernet header.`
286			`/// \param len Length of packet in bytes.`
287			`/// \param packet Pointer to packet data.`
288			`void enc28j60PacketSend(unsigned int len, unsigned char* packet);`
289
290			`//! Packet receive function.`
291			`/// Gets a packet from the network receive buffer, if one is available.`
292			`/// The packet will by headed by an ethernet header.`
293			`/// \param maxlen The maximum acceptable length of a retrieved packet.`
294			`/// \param packet Pointer where packet data should be stored.`
295			`/// \return Packet length in bytes if a packet was retrieved, zero otherwise.`
296			`unsigned int enc28j60PacketReceive(unsigned int maxlen, unsigned char* packet);`
297
298			`//! execute procedure for recovering from a receive overflow`
299			`/// this should be done when the receive memory fills up with packets`
300			`void enc28j60ReceiveOverflowRecover(void);`
301
302			`//! formatted print of important ENC28J60 registers`
303			`void enc28j60RegDump(void);`
304
305			`#endif`
306			`//@}`