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library

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Line No. Rev Author Line
1 6 kaklik /*! \file prism2.c \brief Prism2 802.11b Wireless-LAN Interface Driver. */
2 //*****************************************************************************
3 //
4 // File Name : 'prism2.c'
5 // Title : Prism2 802.11b Wireless-LAN Interface Driver
6 // Author : Pascal Stang
7 // Created : 12/27/2004
8 // Revised : 1/7/2005
9 // Version : 0.1
10 // Target MCU : Atmel AVR series
11 // Editor Tabs : 4
12 //
13 // Description : This driver provides initialization and transmit/receive
14 // functions for the Prism2 802.11b Wireless-LAN Controller.
15 //
16 //*****************************************************************************
17  
18 #include <avr/io.h>
19 #include <avr/interrupt.h>
20 #include <string.h>
21  
22 #include "global.h"
23 #include "timer.h"
24 #include "rprintf.h"
25 #include "debug.h"
26  
27 #include "net.h"
28 #include "prism2.h"
29  
30 // include configuration
31 #include "prism2conf.h"
32  
33 u16 TxHeader[34];
34  
35 void nicInit(void)
36 {
37 prism2Init();
38 }
39  
40 void nicSend(unsigned int len, unsigned char* packet)
41 {
42 u16 i;
43 u16 txfid;
44 u08 stat;
45 // request free buffer space to store outgoing frame
46 prism2Command(PRISM2_CMD_ALLOC, len+44+14+6);
47 // wait for buffer to be allocated
48 while( !(prism2Read16(PRISM2_REG_EVSTAT) & PRISM2_EVENT_ALLOC) );
49 // get the buffer FID
50 txfid = prism2Read16(PRISM2_REG_ALLOCFID);
51 // ACK the alloc event
52 prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_ALLOC);
53  
54 // rprintf("PRISM2: TxFID=0x");
55 // rprintfu16(txfid);
56 // rprintfCRLF();
57  
58 // adjust packet length because MAC addresses and type
59 // will be written seperately from packet payload
60 len-=14;
61  
62 // write the outgoing frame to BAP
63 // begin with control structure
64 prism2SetupTxHeader(TxHeader);
65  
66 // write dest and src MAC addresses
67 for(i=0;i<6;++i)
68 TxHeader[23+i] = packet[i*2+1]<<8 | packet[i*2];
69 // write length
70 TxHeader[29] = htons(len+8);
71 // write type
72 TxHeader[33] = packet[13]<<8 | packet[12];
73  
74 // debugPrintHexTable(34*2, (u08*)TxHeader);
75 // rprintfCRLF();
76 // debugPrintHexTable(len, &packet[14]);
77  
78 // write Tx header out to BAP
79 prism2WriteBAP0(txfid, 0, TxHeader, 34);
80 // write packet out to BAP
81 prism2WriteBAP0(txfid, 68, (u16*)&packet[14], (len+1)>>1);
82 // issue transmit command
83 stat = prism2Command(PRISM2_CMD_TX, txfid);
84 if(stat)
85 rprintf("Transmit failed: 0x%x\r\n", stat);
86 // do cleanup
87 prism2EventCheck();
88 }
89  
90 void nicGetMacAddress(u08* macaddr)
91 {
92 prism2GetMacAddress(macaddr);
93 }
94  
95 void nicSetMacAddress(u08* macaddr)
96 {
97 // not yet supported
98 }
99  
100 void nicRegDump(void)
101 {
102 prism2CardRegDump();
103 prism2RegDump();
104 }
105  
106 void prism2SetupTxHeader(u16* header)
107 {
108 u16 i;
109  
110 // clear out header
111 for(i=0;i<22;i++)
112 header[i] = 0x00;
113  
114 // set TxRate and retry count
115 header[5] = (0<<8) | 0;
116 // 0x00 = automatic selection
117 // 0x0A = 10 = 1.0Mbit/s
118 // 0x14 = 20 = 2.0Mbit/s
119 // 0x37 = 55 = 5.5Mbit/s
120 // 0x6E = 110 = 11 Mbit/s
121  
122 // set TxControl
123 header[6] = 0x0004;
124  
125 // write length
126 // (not really needed since card will pull info from 802.3 header)
127 //TxHeader[22] = len+8;
128  
129 // fill in 802.3 header fields
130 TxHeader[30] = 0xAAAA;
131 TxHeader[31] = 0x0003;
132 TxHeader[32] = 0x0000;
133  
134 // src mac address @ byte offset 52
135 }
136  
137 void prism2EventCheck(void)
138 {
139 unsigned int evstat_data;
140  
141 evstat_data = prism2Read16(PRISM2_REG_EVSTAT);
142  
143 if(evstat_data & PRISM2_EVENT_TX)
144 {
145 prism2Write16(PRISM2_REG_EVACK,PRISM2_EVENT_TX);
146 }
147  
148 if(evstat_data & PRISM2_EVENT_TXEXEC)
149 {
150 prism2Write16(PRISM2_REG_EVACK,PRISM2_EVENT_TXEXEC);
151 }
152  
153 if(evstat_data & PRISM2_EVENT_ALLOC)
154 {
155 prism2Write16(PRISM2_REG_EVACK, 0x0002);
156 }
157  
158 if(evstat_data & PRISM2_EVENT_CMD)
159 {
160 prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_CMD);
161 }
162  
163 if(evstat_data & PRISM2_EVENT_INFO)
164 {
165 prism2Read16(PRISM2_REG_INFOFID);
166 prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_INFO);
167 }
168  
169 if(evstat_data & PRISM2_EVENT_INFDROP)
170 {
171 prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_INFDROP);
172 }
173  
174 if(evstat_data & PRISM2_EVENT_WTERR)
175 {
176 prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_WTERR);
177 }
178 }
179  
180  
181 unsigned int nicPoll(unsigned int maxlen, unsigned char* packet)
182 {
183 u16 rxfid=0;
184 u16 packetLength=0;
185  
186 // check if packets have been received
187 if(prism2Read16(PRISM2_REG_EVSTAT) & PRISM2_EVENT_RX)
188 {
189 // we have a receive event
190 // get RxFID
191 rxfid = prism2Read16(PRISM2_REG_RXFID);
192 // read the packet length
193 prism2ReadBAP0(rxfid, 44, &packetLength, 1);
194 }
195  
196 // if there's no packet or an error - exit
197 if( !packetLength )
198 return 0;
199  
200 // drop anything too big for the buffer
201 if( packetLength > maxlen )
202 {
203 // ACK the receive event to finish up
204 prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_RX);
205 return 0;
206 }
207  
208 // packet is available, retrieve data
209 // this is a hack: while reading in data,
210 // convert 802.2/3 header to ethernet header
211 // first get dest and src MAC addresses
212 prism2ReadBAP0(rxfid, 46, (u16*)&packet[0], 6);
213 // skip length, snap, and ctrl fields
214 // begin data copy again at type field
215 prism2ReadBAP0(rxfid, 46+12+8, (u16*)&packet[12], packetLength-6);
216 // ACK the receive event to finish up
217 prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_RX);
218  
219 return packetLength;
220 }
221  
222 void prism2InitPorts(void)
223 {
224 #if NIC_CONNECTION == MEMORY_MAPPED
225 // enable external SRAM interface - no wait states
226 sbi(MCUSR, SRE);
227 #else
228 // set address port to output
229 outb(PRISM2_ADDRESS_DDR, PRISM2_ADDRESS_MASK);
230 outb(PRISM2_HADDRESS_DDR, PRISM2_HADDRESS_MASK);
231  
232 // set data port to input with pull-ups
233 outb(PRISM2_DATA_DDR, 0x00);
234 outb(PRISM2_DATA_PORT, 0xFF);
235  
236 // initialize the control port read and write pins to de-asserted
237 sbi( PRISM2_CONTROL_PORT, PRISM2_CONTROL_IORD );
238 sbi( PRISM2_CONTROL_PORT, PRISM2_CONTROL_IOWR );
239 sbi( PRISM2_CONTROL_PORT, PRISM2_CONTROL_MEMRD );
240 sbi( PRISM2_CONTROL_PORT, PRISM2_CONTROL_MEMWR );
241 // set the read and write pins to output
242 sbi( PRISM2_CONTROL_DDR, PRISM2_CONTROL_IORD );
243 sbi( PRISM2_CONTROL_DDR, PRISM2_CONTROL_IOWR );
244 sbi( PRISM2_CONTROL_DDR, PRISM2_CONTROL_MEMRD );
245 sbi( PRISM2_CONTROL_DDR, PRISM2_CONTROL_MEMWR );
246 #endif
247 // set reset pin to output
248 sbi( PRISM2_RESET_DDR, PRISM2_RESET_PIN );
249  
250 // clear -REG pin
251 sbi(DDRB, 6);
252 cbi(PORTB, 6);
253 // setup IREQ pin
254 cbi(DDRB, 7);
255 sbi(PORTB, 7);
256 }
257  
258 void prism2Init(void)
259 {
260 u08 result;
261 u16 buffer[20];
262  
263 // rprintf("Init ports\r\n");
264 prism2InitPorts();
265  
266 // assert hardware reset
267 sbi( PRISM2_RESET_PORT, PRISM2_RESET_PIN );
268 // wait
269 delay_ms(10);
270 // release hardware reset
271 cbi( PRISM2_RESET_PORT, PRISM2_RESET_PIN );
272 delay_ms(100);
273  
274 /*
275 // soft-reset card
276 prism2WriteMem(0x3E0+PCMCIA_ATTR_COR, 0x80);
277 delay_ms(10);
278 prism2WriteMem(0x3E0+PCMCIA_ATTR_COR, 0x00);
279 // wait until soft-reset is done
280 delay_ms(500);
281  
282 // set 8-bit PCMCIA I/O mode
283 prism2WriteMem(0x3E0+PCMCIA_ATTR_CSR, 0x20);
284  
285 prism2WriteMem(0x3E0+PCMCIA_ATTR_CSR, 0x04);
286 timerPause(1000);
287 prism2WriteMem(0x3E0+PCMCIA_ATTR_CSR, 0x00);
288 */
289 // enable PCMCIA I/O mode
290 prism2WriteMem(0x3E0+PCMCIA_ATTR_COR, prism2ReadMem(0x3E0+PCMCIA_ATTR_COR) | 0x01);
291 // prism2CardRegDump();
292  
293 rprintf("Prism2 Initializing...\r\n");
294 if( (result = prism2Command(PRISM2_CMD_INIT,0)) )
295 {
296 rprintf("Prism2 Initialization Failure\r\n");
297 rprintf("Result Code = %x\r\n",result);
298 }
299  
300 rprintf("Prism2 Initialized\r\n");
301  
302 // set SSID
303 prism2SetSSID("airdrop");
304  
305 // set max packet size
306 buffer[0] = 0x0002;
307 buffer[1] = PRISM2_RID_CNFMAXDATALEN;
308 buffer[2] = 0x05DC;
309 prism2WriteRID(PRISM2_RID_CNFMAXDATALEN, 0, buffer, 3);
310  
311 // set operating mode / port type
312 buffer[0] = 0x0002;
313 buffer[1] = PRISM2_RID_CNFPORTTYPE;
314 //buffer[2] = 0x0000; // IBSS
315 buffer[2] = 0x0001; // BSS
316 prism2WriteRID(PRISM2_RID_CNFPORTTYPE, 0, buffer, 3);
317  
318 // set channel
319 // buffer[0] = 0x0002;
320 // buffer[1] = 0xFC03;
321 // buffer[2] = 0x0001;
322 // prism2WriteRID(0xFC00, 0, buffer, 3);
323  
324 // enable the interface
325 prism2Command(PRISM2_CMD_ENABLE_MAC0,0);
326 }
327  
328 void prism2Off(void)
329 {
330 // turn off communication
331 prism2Command(PRISM2_CMD_DISABLE_MAC0,0);
332 // wait for all events to complete
333 delay_ms(100);
334 // reset card
335 prism2Command(PRISM2_CMD_INIT,0);
336 }
337  
338 void prism2GetMacAddress(u08* macaddr)
339 {
340 u16 buffer[5];
341  
342 // read MAC address register
343 prism2ReadRID(PRISM2_RID_CNFOWNMACADDR, 0, buffer, 5);
344  
345 *macaddr++ = buffer[2];
346 *macaddr++ = buffer[2]>>8;
347 *macaddr++ = buffer[3];
348 *macaddr++ = buffer[3]>>8;
349 *macaddr++ = buffer[4];
350 *macaddr++ = buffer[4]>>8;
351 }
352  
353 void prism2SetSSID(u08* ssid)
354 {
355 u16 buffer[12];
356  
357 // prepare buffer for SSID write
358 buffer[0] = 0x0012;
359 buffer[1] = PRISM2_RID_CNFDESIREDSSID;
360 buffer[2] = strlen(ssid);
361 // copy ssid string to buffer
362 strcpy((unsigned char*)&buffer[3], ssid);
363 // write SSID
364 prism2WriteRID(PRISM2_RID_CNFDESIREDSSID, 0, buffer, buffer[0]);
365 }
366  
367 void prism2SetWEPKey(u08* wepkey)
368 {
369 u16 buffer[9];
370  
371 // prepare buffer for SSID write
372 buffer[0] = 0x0008;
373 buffer[1] = PRISM2_RID_CNFWEPDEFAULTKEY0;
374 // copy ssid string to buffer
375 strncpy((unsigned char*)&buffer[2], wepkey, 13);
376 buffer[8] &= 0x00FF;
377 // write SSID
378 prism2WriteRID(PRISM2_RID_CNFWEPDEFAULTKEY0, 0, buffer, buffer[0]);
379  
380 // set WEP active
381 buffer[0] = 0x0002;
382 buffer[1] = PRISM2_RID_CNFWEPFLAGS;
383 buffer[2] = 0x0001;
384 prism2WriteRID(PRISM2_RID_CNFWEPFLAGS, 0, buffer, buffer[0]);
385 // set WEP active
386 buffer[0] = 0x0002;
387 buffer[1] = 0xfc2a;
388 buffer[2] = 0x0001;
389 prism2WriteRID(0xfc2a, 0, buffer, buffer[0]);
390 // set WEP active
391 buffer[0] = 0x0002;
392 buffer[1] = 0xfc23;
393 buffer[2] = 0x0000;
394 prism2WriteRID(0xfc23, 0, buffer, buffer[0]);
395  
396 }
397  
398 u08 prism2Command(u16 cmd, u16 param0)
399 {
400 u16 result;
401  
402 // wait until card not busy
403 // rprintf("PRISM_CMD: Wait until card ready\r\n");
404 while(prism2Read16(PRISM2_REG_CMD) & PRISM2_CMD_BUSY);
405  
406 // rprintf("PRISM_CMD: Issue Command = 0x%x\r\n", cmd);
407 prism2Write16(PRISM2_REG_PARAM0, param0);
408 prism2Write16(PRISM2_REG_CMD, cmd);
409  
410 // wait until card not busy
411 // rprintf("PRISM_CMD: Wait until card ready\r\n");
412 while(prism2Read16(PRISM2_REG_CMD) & PRISM2_CMD_BUSY);
413  
414 // read event register - wait for command to complete
415 // rprintf("PRISM_CMD: Wait for command to complete\r\n");
416 while(!(prism2Read16(PRISM2_REG_EVSTAT) & PRISM2_EVENT_CMD));
417  
418 // read status register
419 result = prism2Read16(PRISM2_REG_STATUS)>>8;
420 // rprintf("PRISM_CMD: Result = 0x%x\r\n", result>>8);
421 // rprintf("PRISM_CMD: CmdCode = 0x%x\r\n", result);
422  
423 // acknowledge event
424 // rprintf("PRISM_CMD: Ack command event\r\n");
425 prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_CMD);
426  
427 // return command result
428 return result;
429 }
430  
431 u08 prism2ReadRID(u16 id, u16 offset, u16* data, u16 len)
432 {
433 prism2Command(PRISM2_CMD_ACCESS_RD, id);
434 return prism2ReadBAP0(id, offset, data, len);
435 }
436  
437 u08 prism2WriteRID(u16 id, u16 offset, u16* data, u16 len)
438 {
439 u08 result;
440 result = prism2WriteBAP0(id, offset, data, len);
441 prism2Command(PRISM2_CMD_ACCESS_WR, id);
442 return result;
443 }
444  
445 u08 prism2ReadBAP0(u16 id, u16 offset, u16* data, u16 len)
446 {
447 // wait for BAP to be ready
448 //rprintf("PRISM_BAP: Wait1\r\n");
449 while( prism2Read16(PRISM2_REG_BAP0OFFSET) & PRISM2_BAPOFFSET_BUSY);
450 // set ID
451 prism2Write16(PRISM2_REG_BAP0SEL, id);
452 // set offset
453 prism2Write16(PRISM2_REG_BAP0OFFSET, offset);
454 // wait for BAP to be ready
455 //rprintf("PRISM_BAP: Wait2\r\n");
456 while( prism2Read16(PRISM2_REG_BAP0OFFSET) & PRISM2_BAPOFFSET_BUSY);
457 // check for error
458 if(prism2Read16(PRISM2_REG_BAP0OFFSET) & PRISM2_BAPOFFSET_ERROR)
459 return -1;
460 // read data
461 //rprintf("PRISM_BAP: Read\r\n");
462 while(len--)
463 *data++ = prism2Read16(PRISM2_REG_BAP0DATA);
464 // return success
465 return 0;
466 }
467  
468 u08 prism2WriteBAP0(u16 id, u16 offset, u16* data, u16 len)
469 {
470 // wait for BAP to be ready
471 //rprintf("PRISM_BAP: Wait1\r\n");
472 while( prism2Read16(PRISM2_REG_BAP0OFFSET) & PRISM2_BAPOFFSET_BUSY);
473 // set ID
474 prism2Write16(PRISM2_REG_BAP0SEL, id);
475 // set offset
476 prism2Write16(PRISM2_REG_BAP0OFFSET, offset);
477 // wait for BAP to be ready
478 //rprintf("PRISM_BAP: Wait2\r\n");
479 while( prism2Read16(PRISM2_REG_BAP0OFFSET) & PRISM2_BAPOFFSET_BUSY);
480 // check for error
481 if(prism2Read16(PRISM2_REG_BAP0OFFSET) & PRISM2_BAPOFFSET_ERROR)
482 return -1;
483 // write data
484 //rprintf("PRISM_BAP: Write\r\n");
485 while(len--)
486 prism2Write16(PRISM2_REG_BAP0DATA, *data++);
487 // return success
488 return 0;
489 }
490  
491 void prism2Write(unsigned short address, unsigned char data)
492 {
493 cli();
494 // assert the address
495 outb(PRISM2_HADDRESS_PORT, (address>>8) | (inb(PRISM2_HADDRESS_PORT)&~PRISM2_HADDRESS_MASK));
496 outb(PRISM2_ADDRESS_PORT, address | (inb(PRISM2_ADDRESS_PORT)&~PRISM2_ADDRESS_MASK));
497 // set data bus as output
498 outb(PRISM2_DATA_DDR, 0xFF);
499 // place data on bus
500 outb(PRISM2_DATA_PORT, data);
501 // assert write
502 cbi(PRISM2_CONTROL_PORT, PRISM2_CONTROL_IOWR);
503 // delay
504 PRISM2_IO_ACCESS_DELAY;
505 // negate write
506 sbi(PRISM2_CONTROL_PORT, PRISM2_CONTROL_IOWR);
507 // set data bus back to input with pullups enabled
508 outb(PRISM2_DATA_DDR, 0x00);
509 outb(PRISM2_DATA_PORT, 0xFF);
510 sei();
511 }
512  
513 unsigned char prism2Read(unsigned short address)
514 {
515 unsigned char data;
516 cli();
517 // assert the address
518 outb(PRISM2_HADDRESS_PORT, (address>>8) | (inb(PRISM2_HADDRESS_PORT)&~PRISM2_HADDRESS_MASK));
519 outb(PRISM2_ADDRESS_PORT, address | (inb(PRISM2_ADDRESS_PORT)&~PRISM2_ADDRESS_MASK));
520 // set data bus to input with pullups enabled
521 outb(PRISM2_DATA_DDR, 0x00);
522 outb(PRISM2_DATA_PORT, 0xFF);
523 // assert read
524 cbi(PRISM2_CONTROL_PORT, PRISM2_CONTROL_IORD);
525 // delay
526 PRISM2_IO_ACCESS_DELAY;
527 // read in the data
528 data = inb( PRISM2_DATA_PIN );
529 // negate read
530 sbi(PRISM2_CONTROL_PORT, PRISM2_CONTROL_IORD);
531 // return data
532 sei();
533 return data;
534 }
535  
536 void prism2Write16(unsigned short address, unsigned short data)
537 {
538 prism2Write(address, data);
539 prism2Write(address+1, data>>8);
540 }
541  
542 unsigned short prism2Read16(unsigned short address)
543 {
544 return prism2Read(address) | (prism2Read(address+1)<<8);
545 }
546  
547 void prism2WriteMem(unsigned short address, unsigned short data)
548 {
549 cli();
550 // assert the address
551 outb(PRISM2_HADDRESS_PORT, (address>>8) | (inb(PRISM2_HADDRESS_PORT)&~PRISM2_HADDRESS_MASK));
552 outb(PRISM2_ADDRESS_PORT, address | (inb(PRISM2_ADDRESS_PORT)&~PRISM2_ADDRESS_MASK));
553 // set data bus as output
554 outb(PRISM2_DATA_DDR, 0xFF);
555 // place data on bus
556 outb(PRISM2_DATA_PORT, data);
557 // assert write
558 cbi(PRISM2_CONTROL_PORT, PRISM2_CONTROL_MEMWR);
559 // delay
560 PRISM2_MEM_ACCESS_DELAY;
561 // negate write
562 sbi(PRISM2_CONTROL_PORT, PRISM2_CONTROL_MEMWR);
563 // set data bus back to input with pullups enabled
564 outb(PRISM2_DATA_DDR, 0x00);
565 outb(PRISM2_DATA_PORT, 0xFF);
566 sei();
567 }
568  
569 unsigned short prism2ReadMem(unsigned short address)
570 {
571 unsigned char data;
572 cli();
573 // assert the address
574 outb(PRISM2_HADDRESS_PORT, (address>>8) | (inb(PRISM2_HADDRESS_PORT)&~PRISM2_HADDRESS_MASK));
575 outb(PRISM2_ADDRESS_PORT, address | (inb(PRISM2_ADDRESS_PORT)&~PRISM2_ADDRESS_MASK));
576 // set data bus to input with pullups enabled
577 outb(PRISM2_DATA_DDR, 0x00);
578 outb(PRISM2_DATA_PORT, 0xFF);
579 // assert read
580 cbi(PRISM2_CONTROL_PORT, PRISM2_CONTROL_MEMRD);
581 // delay
582 PRISM2_MEM_ACCESS_DELAY;
583 // read in the data
584 data = inb( PRISM2_DATA_PIN );
585 // negate read
586 sbi(PRISM2_CONTROL_PORT, PRISM2_CONTROL_MEMRD);
587 sei();
588 // return data
589 return data;
590 }
591  
592 void prism2CardRegDump(void)
593 {
594 u16 i;
595 u08 buffer[0x100];
596  
597 rprintfProgStrM("Card Config Registers\r\n");
598 rprintfProgStrM("-------------------------------\r\n");
599 // read card CIS (16 bytes)
600 rprintf("CIS : \r\n");
601 for(i=0; i<0x100; i++)
602 buffer[i] = prism2ReadMem(i<<1);
603 debugPrintHexTable(0x100, buffer);
604  
605 rprintfCRLF();
606  
607 rprintf("COR : "); rprintfu08(prism2ReadMem(0x3E0+PCMCIA_ATTR_COR)); rprintfCRLF();
608 rprintf("CSR : "); rprintfu08(prism2ReadMem(0x3E0+PCMCIA_ATTR_CSR)); rprintfCRLF();
609 rprintf("PRR : "); rprintfu08(prism2ReadMem(0x3E0+PCMCIA_ATTR_PRR)); rprintfCRLF();
610 rprintf("SCR : "); rprintfu08(prism2ReadMem(0x3E0+PCMCIA_ATTR_SCR)); rprintfCRLF();
611 }
612  
613 void prism2RegDump(void)
614 {
615 rprintfProgStrM("Prism2 Registers\r\n");
616 rprintfProgStrM("CMD : "); rprintfu16(prism2Read16(PRISM2_REG_CMD)); rprintfCRLF();
617 rprintfProgStrM("PARAM0 : "); rprintfu16(prism2Read16(PRISM2_REG_PARAM0)); rprintfCRLF();
618 rprintfProgStrM("PARAM1 : "); rprintfu16(prism2Read16(PRISM2_REG_PARAM1)); rprintfCRLF();
619 rprintfProgStrM("PARAM2 : "); rprintfu16(prism2Read16(PRISM2_REG_PARAM2)); rprintfCRLF();
620 rprintfProgStrM("STATUS : "); rprintfu16(prism2Read16(PRISM2_REG_STATUS)); rprintfCRLF();
621 rprintfProgStrM("RESP0 : "); rprintfu16(prism2Read16(PRISM2_REG_RESP0)); rprintfCRLF();
622 rprintfProgStrM("RESP1 : "); rprintfu16(prism2Read16(PRISM2_REG_RESP1)); rprintfCRLF();
623 rprintfProgStrM("RESP2 : "); rprintfu16(prism2Read16(PRISM2_REG_RESP2)); rprintfCRLF();
624  
625 rprintfProgStrM("INFOFID : "); rprintfu16(prism2Read16(PRISM2_REG_INFOFID)); rprintfCRLF();
626 rprintfProgStrM("RXFID : "); rprintfu16(prism2Read16(PRISM2_REG_RXFID)); rprintfCRLF();
627 rprintfProgStrM("ALLOCFID: "); rprintfu16(prism2Read16(PRISM2_REG_ALLOCFID)); rprintfCRLF();
628 rprintfProgStrM("TXFID : "); rprintfu16(prism2Read16(PRISM2_REG_TXFID)); rprintfCRLF();
629  
630 rprintfProgStrM("BAP0SEL : "); rprintfu16(prism2Read16(PRISM2_REG_BAP0SEL)); rprintfCRLF();
631 rprintfProgStrM("BAP0OFFS: "); rprintfu16(prism2Read16(PRISM2_REG_BAP0OFFSET)); rprintfCRLF();
632 rprintfProgStrM("BAP0DATA: "); rprintfu16(prism2Read16(PRISM2_REG_BAP0DATA)); rprintfCRLF();
633  
634 rprintfProgStrM("BAP1SEL : "); rprintfu16(prism2Read16(PRISM2_REG_BAP1SEL)); rprintfCRLF();
635 rprintfProgStrM("BAP1OFFS: "); rprintfu16(prism2Read16(PRISM2_REG_BAP1OFFSET)); rprintfCRLF();
636 rprintfProgStrM("BAP1DATA: "); rprintfu16(prism2Read16(PRISM2_REG_BAP1DATA)); rprintfCRLF();
637  
638 rprintfProgStrM("EVSTAT : "); rprintfu16(prism2Read16(PRISM2_REG_EVSTAT)); rprintfCRLF();
639 rprintfProgStrM("INTEN : "); rprintfu16(prism2Read16(PRISM2_REG_INTEN)); rprintfCRLF();
640 rprintfProgStrM("EVACK : "); rprintfu16(prism2Read16(PRISM2_REG_EVACK)); rprintfCRLF();
641  
642 rprintfProgStrM("SWSUP0 : "); rprintfu16(prism2Read16(PRISM2_REG_SWSUP0)); rprintfCRLF();
643 rprintfProgStrM("SWSUP0 : "); rprintfu16(prism2Read16(PRISM2_REG_SWSUP1)); rprintfCRLF();
644 rprintfProgStrM("SWSUP0 : "); rprintfu16(prism2Read16(PRISM2_REG_SWSUP2)); rprintfCRLF();
645  
646 rprintfProgStrM("AUXPAGE : "); rprintfu16(prism2Read16(PRISM2_REG_AUXPAGE)); rprintfCRLF();
647 rprintfProgStrM("AUXOFFS : "); rprintfu16(prism2Read16(PRISM2_REG_AUXOFFSET)); rprintfCRLF();
648 rprintfProgStrM("AUXDATA : "); rprintfu16(prism2Read16(PRISM2_REG_AUXDATA)); rprintfCRLF();
649  
650 delay_ms(25);
651 }
{BLAME END}
{FOOTER START}

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