| Line No. | Rev | Author | Line |
|---|---|---|---|
| 1 | 6 | kaklik | /*! \file spiflash.h \brief SPI Flash Memory Driver (M25Pxx/AT25Fxxx/etc). */ |
| 2 | //***************************************************************************** |
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| 3 | // |
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| 4 | // File Name : 'spiflash.h' |
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| 5 | // Title : SPI Flash Memory Driver (M25Pxx/AT25Fxxx/etc) |
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| 6 | // Author : Pascal Stang - Copyright (C) 2006 |
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| 7 | // Created : 2006-04-15 |
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| 8 | // Revised : 2006-07-02 |
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| 9 | // Version : 0.1 |
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| 10 | // Target MCU : AVR processors |
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| 11 | // Editor Tabs : 4 |
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| 12 | // |
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| 13 | // NOTE: This code is currently below version 1.0, and therefore is considered |
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| 14 | // to be lacking in some functionality or documentation, or may not be fully |
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| 15 | // tested. Nonetheless, you can expect most functions to work. |
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| 16 | // |
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| 17 | //***************************************************************************** |
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| 18 | |||
| 19 | #ifndef AVRLIB_SPIFLASH_H |
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| 20 | #define AVRLIB_SPIFLASH_H |
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| 21 | |||
| 22 | #include "global.h" |
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| 23 | |||
| 24 | // Compatible with: |
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| 25 | // - ST M25Pxx devices |
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| 26 | // - Atmel AT25Fxxx devices |
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| 27 | // - many more |
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| 28 | |||
| 29 | // device commands |
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| 30 | #define SPIFLASH_CMD_WREN 0x06 // write enable |
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| 31 | #define SPIFLASH_CMD_WRDI 0x04 // write disable |
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| 32 | #define SPIFLASH_CMD_RDID 0x9F // read ID register |
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| 33 | #define SPIFLASH_CMD_RDSR 0x05 // read status register |
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| 34 | #define SPIFLASH_CMD_WRSR 0x01 // write status register |
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| 35 | #define SPIFLASH_CMD_READ 0x03 // read |
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| 36 | #define SPIFLASH_CMD_FASTREAD 0x0B // high-speed read |
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| 37 | #define SPIFLASH_CMD_PAGEPROG 0x02 // page program |
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| 38 | #define SPIFLASH_CMD_SECTERASE 0xD8 // sector erase |
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| 39 | #define SPIFLASH_CMD_CHIPERASE 0xC7 // chip erase |
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| 40 | |||
| 41 | // status register bits |
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| 42 | #define SPIFLASH_STATUS_BUSY 0x01 // busy, write in progress |
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| 43 | #define SPIFLASH_STATUS_WEN 0x02 // write enable |
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| 44 | #define SPIFLASH_STATUS_BP0 0x04 // block protect 0 |
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| 45 | #define SPIFLASH_STATUS_BP1 0x08 // block protect 1 |
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| 46 | #define SPIFLASH_STATUS_BP2 0x10 // block protect 2 |
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| 47 | #define SPIFLASH_STATUS_WPEN 0x80 // write protect enabled |
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| 48 | |||
| 49 | // device constants |
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| 50 | #define SPIFLASH_PAGESIZE 256 // 256 bytes/page |
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| 51 | |||
| 52 | // functions |
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| 53 | |||
| 54 | // Initializes spiflash for operation |
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| 55 | void spiflashInit(void); |
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| 56 | |||
| 57 | // Get spiflash ID |
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| 58 | // NOTE: supported only on some flash memories |
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| 59 | unsigned short spiflashGetID(void); |
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| 60 | |||
| 61 | // Erase entire flash chip |
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| 62 | void spiflashChipErase(void); |
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| 63 | |||
| 64 | // Read flash memory |
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| 65 | // - addr may be any value |
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| 66 | // - nbytes may be any value |
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| 67 | void spiflashRead(unsigned long addr, unsigned long nbytes, unsigned char *data); |
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| 68 | |||
| 69 | // Write flash memory (automatic handling of page writes) |
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| 70 | // - memory must be previously erased |
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| 71 | // - addr MUST start at a page break |
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| 72 | // OR |
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| 73 | // - nbytes must be small enough such that page boundary is not crossed |
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| 74 | void spiflashWrite(unsigned long addr, unsigned long nbytes, unsigned char *data); |
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| 75 | |||
| 76 | #endif |
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