| Line No. | Rev | Author | Line |
|---|---|---|---|
| 1 | 6 | kaklik | /*! \file timer.c \brief System Timer function library. */ |
| 2 | //***************************************************************************** |
||
| 3 | // |
||
| 4 | // File Name : 'timer.c' |
||
| 5 | // Title : System Timer function library |
||
| 6 | // Author : Pascal Stang - Copyright (C) 2000-2002 |
||
| 7 | // Created : 11/22/2000 |
||
| 8 | // Revised : 07/09/2003 |
||
| 9 | // Version : 1.1 |
||
| 10 | // Target MCU : Atmel AVR Series |
||
| 11 | // Editor Tabs : 4 |
||
| 12 | // |
||
| 13 | // This code is distributed under the GNU Public License |
||
| 14 | // which can be found at http://www.gnu.org/licenses/gpl.txt |
||
| 15 | // |
||
| 16 | //***************************************************************************** |
||
| 17 | |||
| 18 | #include <avr/io.h> |
||
| 19 | #include <avr/interrupt.h> |
||
| 20 | #include <avr/pgmspace.h> |
||
| 21 | #include <avr/sleep.h> |
||
| 22 | |||
| 23 | #include "global.h" |
||
| 24 | #include "timer.h" |
||
| 25 | |||
| 26 | #include "rprintf.h" |
||
| 27 | |||
| 28 | // Program ROM constants |
||
| 29 | // the prescale division values stored in order of timer control register index |
||
| 30 | // STOP, CLK, CLK/8, CLK/64, CLK/256, CLK/1024 |
||
| 31 | unsigned short __attribute__ ((progmem)) TimerPrescaleFactor[] = {0,1,8,64,256,1024}; |
||
| 32 | // the prescale division values stored in order of timer control register index |
||
| 33 | // STOP, CLK, CLK/8, CLK/32, CLK/64, CLK/128, CLK/256, CLK/1024 |
||
| 34 | unsigned short __attribute__ ((progmem)) TimerRTCPrescaleFactor[] = {0,1,8,32,64,128,256,1024}; |
||
| 35 | |||
| 36 | // Global variables |
||
| 37 | // time registers |
||
| 38 | volatile unsigned long TimerPauseReg; |
||
| 39 | volatile unsigned long Timer0Reg0; |
||
| 40 | volatile unsigned long Timer2Reg0; |
||
| 41 | |||
| 42 | typedef void (*voidFuncPtr)(void); |
||
| 43 | volatile static voidFuncPtr TimerIntFunc[TIMER_NUM_INTERRUPTS]; |
||
| 44 | |||
| 45 | // delay for a minimum of <us> microseconds |
||
| 46 | // the time resolution is dependent on the time the loop takes |
||
| 47 | // e.g. with 4Mhz and 5 cycles per loop, the resolution is 1.25 us |
||
| 48 | void delay_us(unsigned short time_us) |
||
| 49 | { |
||
| 50 | unsigned short delay_loops; |
||
| 51 | register unsigned short i; |
||
| 52 | |||
| 53 | delay_loops = (time_us+3)/5*CYCLES_PER_US; // +3 for rounding up (dirty) |
||
| 54 | |||
| 55 | // one loop takes 5 cpu cycles |
||
| 56 | for (i=0; i < delay_loops; i++) {}; |
||
| 57 | } |
||
| 58 | /* |
||
| 59 | void delay_ms(unsigned char time_ms) |
||
| 60 | { |
||
| 61 | unsigned short delay_count = F_CPU / 4000; |
||
| 62 | |||
| 63 | unsigned short cnt; |
||
| 64 | asm volatile ("\n" |
||
| 65 | "L_dl1%=:\n\t" |
||
| 66 | "mov %A0, %A2\n\t" |
||
| 67 | "mov %B0, %B2\n" |
||
| 68 | "L_dl2%=:\n\t" |
||
| 69 | "sbiw %A0, 1\n\t" |
||
| 70 | "brne L_dl2%=\n\t" |
||
| 71 | "dec %1\n\t" "brne L_dl1%=\n\t":"=&w" (cnt) |
||
| 72 | :"r"(time_ms), "r"((unsigned short) (delay_count)) |
||
| 73 | ); |
||
| 74 | } |
||
| 75 | */ |
||
| 76 | void timerInit(void) |
||
| 77 | { |
||
| 78 | u08 intNum; |
||
| 79 | // detach all user functions from interrupts |
||
| 80 | for(intNum=0; intNum<TIMER_NUM_INTERRUPTS; intNum++) |
||
| 81 | timerDetach(intNum); |
||
| 82 | |||
| 83 | // initialize all timers |
||
| 84 | timer0Init(); |
||
| 85 | timer1Init(); |
||
| 86 | #ifdef TCNT2 // support timer2 only if it exists |
||
| 87 | timer2Init(); |
||
| 88 | #endif |
||
| 89 | // enable interrupts |
||
| 90 | sei(); |
||
| 91 | } |
||
| 92 | |||
| 93 | void timer0Init() |
||
| 94 | { |
||
| 95 | // initialize timer 0 |
||
| 96 | timer0SetPrescaler( TIMER0PRESCALE ); // set prescaler |
||
| 97 | outb(TCNT0, 0); // reset TCNT0 |
||
| 98 | sbi(TIMSK, TOIE0); // enable TCNT0 overflow interrupt |
||
| 99 | |||
| 100 | timer0ClearOverflowCount(); // initialize time registers |
||
| 101 | } |
||
| 102 | |||
| 103 | void timer1Init(void) |
||
| 104 | { |
||
| 105 | // initialize timer 1 |
||
| 106 | timer1SetPrescaler( TIMER1PRESCALE ); // set prescaler |
||
| 107 | outb(TCNT1H, 0); // reset TCNT1 |
||
| 108 | outb(TCNT1L, 0); |
||
| 109 | sbi(TIMSK, TOIE1); // enable TCNT1 overflow |
||
| 110 | } |
||
| 111 | |||
| 112 | #ifdef TCNT2 // support timer2 only if it exists |
||
| 113 | void timer2Init(void) |
||
| 114 | { |
||
| 115 | // initialize timer 2 |
||
| 116 | timer2SetPrescaler( TIMER2PRESCALE ); // set prescaler |
||
| 117 | outb(TCNT2, 0); // reset TCNT2 |
||
| 118 | sbi(TIMSK, TOIE2); // enable TCNT2 overflow |
||
| 119 | |||
| 120 | timer2ClearOverflowCount(); // initialize time registers |
||
| 121 | } |
||
| 122 | #endif |
||
| 123 | |||
| 124 | void timer0SetPrescaler(u08 prescale) |
||
| 125 | { |
||
| 126 | // set prescaler on timer 0 |
||
| 127 | outb(TCCR0, (inb(TCCR0) & ~TIMER_PRESCALE_MASK) | prescale); |
||
| 128 | } |
||
| 129 | |||
| 130 | void timer1SetPrescaler(u08 prescale) |
||
| 131 | { |
||
| 132 | // set prescaler on timer 1 |
||
| 133 | outb(TCCR1B, (inb(TCCR1B) & ~TIMER_PRESCALE_MASK) | prescale); |
||
| 134 | } |
||
| 135 | |||
| 136 | #ifdef TCNT2 // support timer2 only if it exists |
||
| 137 | void timer2SetPrescaler(u08 prescale) |
||
| 138 | { |
||
| 139 | // set prescaler on timer 2 |
||
| 140 | outb(TCCR2, (inb(TCCR2) & ~TIMER_PRESCALE_MASK) | prescale); |
||
| 141 | } |
||
| 142 | #endif |
||
| 143 | |||
| 144 | u16 timer0GetPrescaler(void) |
||
| 145 | { |
||
| 146 | // get the current prescaler setting |
||
| 147 | return (pgm_read_word(TimerPrescaleFactor+(inb(TCCR0) & TIMER_PRESCALE_MASK))); |
||
| 148 | } |
||
| 149 | |||
| 150 | u16 timer1GetPrescaler(void) |
||
| 151 | { |
||
| 152 | // get the current prescaler setting |
||
| 153 | return (pgm_read_word(TimerPrescaleFactor+(inb(TCCR1B) & TIMER_PRESCALE_MASK))); |
||
| 154 | } |
||
| 155 | |||
| 156 | #ifdef TCNT2 // support timer2 only if it exists |
||
| 157 | u16 timer2GetPrescaler(void) |
||
| 158 | { |
||
| 159 | //TODO: can we assume for all 3-timer AVR processors, |
||
| 160 | // that timer2 is the RTC timer? |
||
| 161 | |||
| 162 | // get the current prescaler setting |
||
| 163 | return (pgm_read_word(TimerRTCPrescaleFactor+(inb(TCCR2) & TIMER_PRESCALE_MASK))); |
||
| 164 | } |
||
| 165 | #endif |
||
| 166 | |||
| 167 | void timerAttach(u08 interruptNum, void (*userFunc)(void) ) |
||
| 168 | { |
||
| 169 | // make sure the interrupt number is within bounds |
||
| 170 | if(interruptNum < TIMER_NUM_INTERRUPTS) |
||
| 171 | { |
||
| 172 | // set the interrupt function to run |
||
| 173 | // the supplied user's function |
||
| 174 | TimerIntFunc[interruptNum] = userFunc; |
||
| 175 | } |
||
| 176 | } |
||
| 177 | |||
| 178 | void timerDetach(u08 interruptNum) |
||
| 179 | { |
||
| 180 | // make sure the interrupt number is within bounds |
||
| 181 | if(interruptNum < TIMER_NUM_INTERRUPTS) |
||
| 182 | { |
||
| 183 | // set the interrupt function to run nothing |
||
| 184 | TimerIntFunc[interruptNum] = 0; |
||
| 185 | } |
||
| 186 | } |
||
| 187 | /* |
||
| 188 | u32 timerMsToTics(u16 ms) |
||
| 189 | { |
||
| 190 | // calculate the prescaler division rate |
||
| 191 | u16 prescaleDiv = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))); |
||
| 192 | // calculate the number of timer tics in x milliseconds |
||
| 193 | return (ms*(F_CPU/(prescaleDiv*256)))/1000; |
||
| 194 | } |
||
| 195 | |||
| 196 | u16 timerTicsToMs(u32 tics) |
||
| 197 | { |
||
| 198 | // calculate the prescaler division rate |
||
| 199 | u16 prescaleDiv = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))); |
||
| 200 | // calculate the number of milliseconds in x timer tics |
||
| 201 | return (tics*1000*(prescaleDiv*256))/F_CPU; |
||
| 202 | } |
||
| 203 | */ |
||
| 204 | void timerPause(unsigned short pause_ms) |
||
| 205 | { |
||
| 206 | // pauses for exactly <pause_ms> number of milliseconds |
||
| 207 | u08 timerThres; |
||
| 208 | u32 ticRateHz; |
||
| 209 | u32 pause; |
||
| 210 | |||
| 211 | // capture current pause timer value |
||
| 212 | timerThres = inb(TCNT0); |
||
| 213 | // reset pause timer overflow count |
||
| 214 | TimerPauseReg = 0; |
||
| 215 | // calculate delay for [pause_ms] milliseconds |
||
| 216 | // prescaler division = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))) |
||
| 217 | ticRateHz = F_CPU/timer0GetPrescaler(); |
||
| 218 | // precision management |
||
| 219 | // prevent overflow and precision underflow |
||
| 220 | // -could add more conditions to improve accuracy |
||
| 221 | if( ((ticRateHz < 429497) && (pause_ms <= 10000)) ) |
||
| 222 | pause = (pause_ms*ticRateHz)/1000; |
||
| 223 | else |
||
| 224 | pause = pause_ms*(ticRateHz/1000); |
||
| 225 | |||
| 226 | // loop until time expires |
||
| 227 | while( ((TimerPauseReg<<8) | inb(TCNT0)) < (pause+timerThres) ) |
||
| 228 | { |
||
| 229 | if( TimerPauseReg < (pause>>8)); |
||
| 230 | { |
||
| 231 | // save power by idling the processor |
||
| 232 | set_sleep_mode(SLEEP_MODE_IDLE); |
||
| 233 | sleep_mode(); |
||
| 234 | } |
||
| 235 | } |
||
| 236 | |||
| 237 | /* old inaccurate code, for reference |
||
| 238 | |||
| 239 | // calculate delay for [pause_ms] milliseconds |
||
| 240 | u16 prescaleDiv = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))); |
||
| 241 | u32 pause = (pause_ms*(F_CPU/(prescaleDiv*256)))/1000; |
||
| 242 | |||
| 243 | TimerPauseReg = 0; |
||
| 244 | while(TimerPauseReg < pause); |
||
| 245 | |||
| 246 | */ |
||
| 247 | } |
||
| 248 | |||
| 249 | void timer0ClearOverflowCount(void) |
||
| 250 | { |
||
| 251 | // clear the timer overflow counter registers |
||
| 252 | Timer0Reg0 = 0; // initialize time registers |
||
| 253 | } |
||
| 254 | |||
| 255 | long timer0GetOverflowCount(void) |
||
| 256 | { |
||
| 257 | // return the current timer overflow count |
||
| 258 | // (this is since the last timer0ClearOverflowCount() command was called) |
||
| 259 | return Timer0Reg0; |
||
| 260 | } |
||
| 261 | |||
| 262 | #ifdef TCNT2 // support timer2 only if it exists |
||
| 263 | void timer2ClearOverflowCount(void) |
||
| 264 | { |
||
| 265 | // clear the timer overflow counter registers |
||
| 266 | Timer2Reg0 = 0; // initialize time registers |
||
| 267 | } |
||
| 268 | |||
| 269 | long timer2GetOverflowCount(void) |
||
| 270 | { |
||
| 271 | // return the current timer overflow count |
||
| 272 | // (this is since the last timer2ClearOverflowCount() command was called) |
||
| 273 | return Timer2Reg0; |
||
| 274 | } |
||
| 275 | #endif |
||
| 276 | |||
| 277 | void timer1PWMInit(u08 bitRes) |
||
| 278 | { |
||
| 279 | // configures timer1 for use with PWM output |
||
| 280 | // on OC1A and OC1B pins |
||
| 281 | |||
| 282 | // enable timer1 as 8,9,10bit PWM |
||
| 283 | if(bitRes == 9) |
||
| 284 | { // 9bit mode |
||
| 285 | sbi(TCCR1A,PWM11); |
||
| 286 | cbi(TCCR1A,PWM10); |
||
| 287 | } |
||
| 288 | else if( bitRes == 10 ) |
||
| 289 | { // 10bit mode |
||
| 290 | sbi(TCCR1A,PWM11); |
||
| 291 | sbi(TCCR1A,PWM10); |
||
| 292 | } |
||
| 293 | else |
||
| 294 | { // default 8bit mode |
||
| 295 | cbi(TCCR1A,PWM11); |
||
| 296 | sbi(TCCR1A,PWM10); |
||
| 297 | } |
||
| 298 | |||
| 299 | // clear output compare value A |
||
| 300 | outb(OCR1AH, 0); |
||
| 301 | outb(OCR1AL, 0); |
||
| 302 | // clear output compare value B |
||
| 303 | outb(OCR1BH, 0); |
||
| 304 | outb(OCR1BL, 0); |
||
| 305 | } |
||
| 306 | |||
| 307 | #ifdef WGM10 |
||
| 308 | // include support for arbitrary top-count PWM |
||
| 309 | // on new AVR processors that support it |
||
| 310 | void timer1PWMInitICR(u16 topcount) |
||
| 311 | { |
||
| 312 | // set PWM mode with ICR top-count |
||
| 313 | cbi(TCCR1A,WGM10); |
||
| 314 | sbi(TCCR1A,WGM11); |
||
| 315 | sbi(TCCR1B,WGM12); |
||
| 316 | sbi(TCCR1B,WGM13); |
||
| 317 | |||
| 318 | // set top count value |
||
| 319 | ICR1 = topcount; |
||
| 320 | |||
| 321 | // clear output compare value A |
||
| 322 | OCR1A = 0; |
||
| 323 | // clear output compare value B |
||
| 324 | OCR1B = 0; |
||
| 325 | |||
| 326 | } |
||
| 327 | #endif |
||
| 328 | |||
| 329 | void timer1PWMOff(void) |
||
| 330 | { |
||
| 331 | // turn off timer1 PWM mode |
||
| 332 | cbi(TCCR1A,PWM11); |
||
| 333 | cbi(TCCR1A,PWM10); |
||
| 334 | // set PWM1A/B (OutputCompare action) to none |
||
| 335 | timer1PWMAOff(); |
||
| 336 | timer1PWMBOff(); |
||
| 337 | } |
||
| 338 | |||
| 339 | void timer1PWMAOn(void) |
||
| 340 | { |
||
| 341 | // turn on channel A (OC1A) PWM output |
||
| 342 | // set OC1A as non-inverted PWM |
||
| 343 | sbi(TCCR1A,COM1A1); |
||
| 344 | cbi(TCCR1A,COM1A0); |
||
| 345 | } |
||
| 346 | |||
| 347 | void timer1PWMBOn(void) |
||
| 348 | { |
||
| 349 | // turn on channel B (OC1B) PWM output |
||
| 350 | // set OC1B as non-inverted PWM |
||
| 351 | sbi(TCCR1A,COM1B1); |
||
| 352 | cbi(TCCR1A,COM1B0); |
||
| 353 | } |
||
| 354 | |||
| 355 | void timer1PWMAOff(void) |
||
| 356 | { |
||
| 357 | // turn off channel A (OC1A) PWM output |
||
| 358 | // set OC1A (OutputCompare action) to none |
||
| 359 | cbi(TCCR1A,COM1A1); |
||
| 360 | cbi(TCCR1A,COM1A0); |
||
| 361 | } |
||
| 362 | |||
| 363 | void timer1PWMBOff(void) |
||
| 364 | { |
||
| 365 | // turn off channel B (OC1B) PWM output |
||
| 366 | // set OC1B (OutputCompare action) to none |
||
| 367 | cbi(TCCR1A,COM1B1); |
||
| 368 | cbi(TCCR1A,COM1B0); |
||
| 369 | } |
||
| 370 | |||
| 371 | void timer1PWMASet(u16 pwmDuty) |
||
| 372 | { |
||
| 373 | // set PWM (output compare) duty for channel A |
||
| 374 | // this PWM output is generated on OC1A pin |
||
| 375 | // NOTE: pwmDuty should be in the range 0-255 for 8bit PWM |
||
| 376 | // pwmDuty should be in the range 0-511 for 9bit PWM |
||
| 377 | // pwmDuty should be in the range 0-1023 for 10bit PWM |
||
| 378 | //outp( (pwmDuty>>8), OCR1AH); // set the high 8bits of OCR1A |
||
| 379 | //outp( (pwmDuty&0x00FF), OCR1AL); // set the low 8bits of OCR1A |
||
| 380 | OCR1A = pwmDuty; |
||
| 381 | } |
||
| 382 | |||
| 383 | void timer1PWMBSet(u16 pwmDuty) |
||
| 384 | { |
||
| 385 | // set PWM (output compare) duty for channel B |
||
| 386 | // this PWM output is generated on OC1B pin |
||
| 387 | // NOTE: pwmDuty should be in the range 0-255 for 8bit PWM |
||
| 388 | // pwmDuty should be in the range 0-511 for 9bit PWM |
||
| 389 | // pwmDuty should be in the range 0-1023 for 10bit PWM |
||
| 390 | //outp( (pwmDuty>>8), OCR1BH); // set the high 8bits of OCR1B |
||
| 391 | //outp( (pwmDuty&0x00FF), OCR1BL); // set the low 8bits of OCR1B |
||
| 392 | OCR1B = pwmDuty; |
||
| 393 | } |
||
| 394 | |||
| 395 | //! Interrupt handler for tcnt0 overflow interrupt |
||
| 396 | TIMER_INTERRUPT_HANDLER(SIG_OVERFLOW0) |
||
| 397 | { |
||
| 398 | Timer0Reg0++; // increment low-order counter |
||
| 399 | |||
| 400 | // increment pause counter |
||
| 401 | TimerPauseReg++; |
||
| 402 | |||
| 403 | // if a user function is defined, execute it too |
||
| 404 | if(TimerIntFunc[TIMER0OVERFLOW_INT]) |
||
| 405 | TimerIntFunc[TIMER0OVERFLOW_INT](); |
||
| 406 | } |
||
| 407 | |||
| 408 | //! Interrupt handler for tcnt1 overflow interrupt |
||
| 409 | TIMER_INTERRUPT_HANDLER(SIG_OVERFLOW1) |
||
| 410 | { |
||
| 411 | // if a user function is defined, execute it |
||
| 412 | if(TimerIntFunc[TIMER1OVERFLOW_INT]) |
||
| 413 | TimerIntFunc[TIMER1OVERFLOW_INT](); |
||
| 414 | } |
||
| 415 | |||
| 416 | #ifdef TCNT2 // support timer2 only if it exists |
||
| 417 | //! Interrupt handler for tcnt2 overflow interrupt |
||
| 418 | TIMER_INTERRUPT_HANDLER(SIG_OVERFLOW2) |
||
| 419 | { |
||
| 420 | Timer2Reg0++; // increment low-order counter |
||
| 421 | |||
| 422 | // if a user function is defined, execute it |
||
| 423 | if(TimerIntFunc[TIMER2OVERFLOW_INT]) |
||
| 424 | TimerIntFunc[TIMER2OVERFLOW_INT](); |
||
| 425 | } |
||
| 426 | #endif |
||
| 427 | |||
| 428 | #ifdef OCR0 |
||
| 429 | // include support for Output Compare 0 for new AVR processors that support it |
||
| 430 | //! Interrupt handler for OutputCompare0 match (OC0) interrupt |
||
| 431 | TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE0) |
||
| 432 | { |
||
| 433 | // if a user function is defined, execute it |
||
| 434 | if(TimerIntFunc[TIMER0OUTCOMPARE_INT]) |
||
| 435 | TimerIntFunc[TIMER0OUTCOMPARE_INT](); |
||
| 436 | } |
||
| 437 | #endif |
||
| 438 | |||
| 439 | //! Interrupt handler for CutputCompare1A match (OC1A) interrupt |
||
| 440 | TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE1A) |
||
| 441 | { |
||
| 442 | // if a user function is defined, execute it |
||
| 443 | if(TimerIntFunc[TIMER1OUTCOMPAREA_INT]) |
||
| 444 | TimerIntFunc[TIMER1OUTCOMPAREA_INT](); |
||
| 445 | } |
||
| 446 | |||
| 447 | //! Interrupt handler for OutputCompare1B match (OC1B) interrupt |
||
| 448 | TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE1B) |
||
| 449 | { |
||
| 450 | // if a user function is defined, execute it |
||
| 451 | if(TimerIntFunc[TIMER1OUTCOMPAREB_INT]) |
||
| 452 | TimerIntFunc[TIMER1OUTCOMPAREB_INT](); |
||
| 453 | } |
||
| 454 | |||
| 455 | //! Interrupt handler for InputCapture1 (IC1) interrupt |
||
| 456 | TIMER_INTERRUPT_HANDLER(SIG_INPUT_CAPTURE1) |
||
| 457 | { |
||
| 458 | // if a user function is defined, execute it |
||
| 459 | if(TimerIntFunc[TIMER1INPUTCAPTURE_INT]) |
||
| 460 | TimerIntFunc[TIMER1INPUTCAPTURE_INT](); |
||
| 461 | } |
||
| 462 | |||
| 463 | //! Interrupt handler for OutputCompare2 match (OC2) interrupt |
||
| 464 | TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE2) |
||
| 465 | { |
||
| 466 | // if a user function is defined, execute it |
||
| 467 | if(TimerIntFunc[TIMER2OUTCOMPARE_INT]) |
||
| 468 | TimerIntFunc[TIMER2OUTCOMPARE_INT](); |
||
| 469 | } |
Powered by WebSVN v2.8.3