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1 | 6 | kaklik | /*! \file timer.c \brief System Timer function library. */ |
2 | //***************************************************************************** |
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3 | // |
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4 | // File Name : 'timer.c' |
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5 | // Title : System Timer function library |
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6 | // Author : Pascal Stang - Copyright (C) 2000-2002 |
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7 | // Created : 11/22/2000 |
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8 | // Revised : 07/09/2003 |
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9 | // Version : 1.1 |
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10 | // Target MCU : Atmel AVR Series |
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11 | // Editor Tabs : 4 |
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12 | // |
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13 | // This code is distributed under the GNU Public License |
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14 | // which can be found at http://www.gnu.org/licenses/gpl.txt |
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15 | // |
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16 | //***************************************************************************** |
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17 | |||
18 | #include <avr/io.h> |
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19 | #include <avr/interrupt.h> |
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20 | #include <avr/pgmspace.h> |
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21 | #include <avr/sleep.h> |
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22 | |||
23 | #include "global.h" |
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24 | #include "timer.h" |
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25 | |||
26 | #include "rprintf.h" |
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27 | |||
28 | // Program ROM constants |
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29 | // the prescale division values stored in order of timer control register index |
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30 | // STOP, CLK, CLK/8, CLK/64, CLK/256, CLK/1024 |
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31 | unsigned short __attribute__ ((progmem)) TimerPrescaleFactor[] = {0,1,8,64,256,1024}; |
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32 | // the prescale division values stored in order of timer control register index |
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33 | // STOP, CLK, CLK/8, CLK/32, CLK/64, CLK/128, CLK/256, CLK/1024 |
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34 | unsigned short __attribute__ ((progmem)) TimerRTCPrescaleFactor[] = {0,1,8,32,64,128,256,1024}; |
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35 | |||
36 | // Global variables |
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37 | // time registers |
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38 | volatile unsigned long TimerPauseReg; |
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39 | volatile unsigned long Timer0Reg0; |
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40 | volatile unsigned long Timer2Reg0; |
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41 | |||
42 | typedef void (*voidFuncPtr)(void); |
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43 | volatile static voidFuncPtr TimerIntFunc[TIMER_NUM_INTERRUPTS]; |
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44 | |||
45 | // delay for a minimum of <us> microseconds |
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46 | // the time resolution is dependent on the time the loop takes |
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47 | // e.g. with 4Mhz and 5 cycles per loop, the resolution is 1.25 us |
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48 | void delay_us(unsigned short time_us) |
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49 | { |
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50 | unsigned short delay_loops; |
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51 | register unsigned short i; |
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52 | |||
53 | delay_loops = (time_us+3)/5*CYCLES_PER_US; // +3 for rounding up (dirty) |
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54 | |||
55 | // one loop takes 5 cpu cycles |
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56 | for (i=0; i < delay_loops; i++) {}; |
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57 | } |
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58 | /* |
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59 | void delay_ms(unsigned char time_ms) |
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60 | { |
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61 | unsigned short delay_count = F_CPU / 4000; |
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62 | |||
63 | unsigned short cnt; |
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64 | asm volatile ("\n" |
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65 | "L_dl1%=:\n\t" |
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66 | "mov %A0, %A2\n\t" |
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67 | "mov %B0, %B2\n" |
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68 | "L_dl2%=:\n\t" |
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69 | "sbiw %A0, 1\n\t" |
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70 | "brne L_dl2%=\n\t" |
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71 | "dec %1\n\t" "brne L_dl1%=\n\t":"=&w" (cnt) |
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72 | :"r"(time_ms), "r"((unsigned short) (delay_count)) |
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73 | ); |
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74 | } |
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75 | */ |
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76 | void timerInit(void) |
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77 | { |
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78 | u08 intNum; |
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79 | // detach all user functions from interrupts |
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80 | for(intNum=0; intNum<TIMER_NUM_INTERRUPTS; intNum++) |
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81 | timerDetach(intNum); |
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82 | |||
83 | // initialize all timers |
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84 | timer0Init(); |
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85 | timer1Init(); |
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86 | #ifdef TCNT2 // support timer2 only if it exists |
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87 | timer2Init(); |
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88 | #endif |
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89 | // enable interrupts |
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90 | sei(); |
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91 | } |
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92 | |||
93 | void timer0Init() |
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94 | { |
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95 | // initialize timer 0 |
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96 | timer0SetPrescaler( TIMER0PRESCALE ); // set prescaler |
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97 | outb(TCNT0, 0); // reset TCNT0 |
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98 | sbi(TIMSK, TOIE0); // enable TCNT0 overflow interrupt |
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99 | |||
100 | timer0ClearOverflowCount(); // initialize time registers |
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101 | } |
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102 | |||
103 | void timer1Init(void) |
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104 | { |
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105 | // initialize timer 1 |
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106 | timer1SetPrescaler( TIMER1PRESCALE ); // set prescaler |
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107 | outb(TCNT1H, 0); // reset TCNT1 |
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108 | outb(TCNT1L, 0); |
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109 | sbi(TIMSK, TOIE1); // enable TCNT1 overflow |
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110 | } |
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111 | |||
112 | #ifdef TCNT2 // support timer2 only if it exists |
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113 | void timer2Init(void) |
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114 | { |
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115 | // initialize timer 2 |
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116 | timer2SetPrescaler( TIMER2PRESCALE ); // set prescaler |
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117 | outb(TCNT2, 0); // reset TCNT2 |
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118 | sbi(TIMSK, TOIE2); // enable TCNT2 overflow |
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119 | |||
120 | timer2ClearOverflowCount(); // initialize time registers |
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121 | } |
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122 | #endif |
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123 | |||
124 | void timer0SetPrescaler(u08 prescale) |
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125 | { |
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126 | // set prescaler on timer 0 |
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127 | outb(TCCR0, (inb(TCCR0) & ~TIMER_PRESCALE_MASK) | prescale); |
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128 | } |
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129 | |||
130 | void timer1SetPrescaler(u08 prescale) |
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131 | { |
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132 | // set prescaler on timer 1 |
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133 | outb(TCCR1B, (inb(TCCR1B) & ~TIMER_PRESCALE_MASK) | prescale); |
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134 | } |
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135 | |||
136 | #ifdef TCNT2 // support timer2 only if it exists |
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137 | void timer2SetPrescaler(u08 prescale) |
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138 | { |
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139 | // set prescaler on timer 2 |
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140 | outb(TCCR2, (inb(TCCR2) & ~TIMER_PRESCALE_MASK) | prescale); |
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141 | } |
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142 | #endif |
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143 | |||
144 | u16 timer0GetPrescaler(void) |
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145 | { |
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146 | // get the current prescaler setting |
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147 | return (pgm_read_word(TimerPrescaleFactor+(inb(TCCR0) & TIMER_PRESCALE_MASK))); |
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148 | } |
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149 | |||
150 | u16 timer1GetPrescaler(void) |
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151 | { |
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152 | // get the current prescaler setting |
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153 | return (pgm_read_word(TimerPrescaleFactor+(inb(TCCR1B) & TIMER_PRESCALE_MASK))); |
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154 | } |
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155 | |||
156 | #ifdef TCNT2 // support timer2 only if it exists |
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157 | u16 timer2GetPrescaler(void) |
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158 | { |
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159 | //TODO: can we assume for all 3-timer AVR processors, |
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160 | // that timer2 is the RTC timer? |
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161 | |||
162 | // get the current prescaler setting |
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163 | return (pgm_read_word(TimerRTCPrescaleFactor+(inb(TCCR2) & TIMER_PRESCALE_MASK))); |
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164 | } |
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165 | #endif |
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166 | |||
167 | void timerAttach(u08 interruptNum, void (*userFunc)(void) ) |
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168 | { |
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169 | // make sure the interrupt number is within bounds |
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170 | if(interruptNum < TIMER_NUM_INTERRUPTS) |
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171 | { |
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172 | // set the interrupt function to run |
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173 | // the supplied user's function |
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174 | TimerIntFunc[interruptNum] = userFunc; |
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175 | } |
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176 | } |
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177 | |||
178 | void timerDetach(u08 interruptNum) |
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179 | { |
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180 | // make sure the interrupt number is within bounds |
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181 | if(interruptNum < TIMER_NUM_INTERRUPTS) |
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182 | { |
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183 | // set the interrupt function to run nothing |
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184 | TimerIntFunc[interruptNum] = 0; |
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185 | } |
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186 | } |
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187 | /* |
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188 | u32 timerMsToTics(u16 ms) |
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189 | { |
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190 | // calculate the prescaler division rate |
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191 | u16 prescaleDiv = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))); |
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192 | // calculate the number of timer tics in x milliseconds |
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193 | return (ms*(F_CPU/(prescaleDiv*256)))/1000; |
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194 | } |
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195 | |||
196 | u16 timerTicsToMs(u32 tics) |
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197 | { |
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198 | // calculate the prescaler division rate |
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199 | u16 prescaleDiv = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))); |
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200 | // calculate the number of milliseconds in x timer tics |
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201 | return (tics*1000*(prescaleDiv*256))/F_CPU; |
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202 | } |
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203 | */ |
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204 | void timerPause(unsigned short pause_ms) |
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205 | { |
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206 | // pauses for exactly <pause_ms> number of milliseconds |
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207 | u08 timerThres; |
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208 | u32 ticRateHz; |
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209 | u32 pause; |
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210 | |||
211 | // capture current pause timer value |
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212 | timerThres = inb(TCNT0); |
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213 | // reset pause timer overflow count |
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214 | TimerPauseReg = 0; |
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215 | // calculate delay for [pause_ms] milliseconds |
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216 | // prescaler division = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))) |
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217 | ticRateHz = F_CPU/timer0GetPrescaler(); |
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218 | // precision management |
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219 | // prevent overflow and precision underflow |
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220 | // -could add more conditions to improve accuracy |
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221 | if( ((ticRateHz < 429497) && (pause_ms <= 10000)) ) |
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222 | pause = (pause_ms*ticRateHz)/1000; |
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223 | else |
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224 | pause = pause_ms*(ticRateHz/1000); |
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225 | |||
226 | // loop until time expires |
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227 | while( ((TimerPauseReg<<8) | inb(TCNT0)) < (pause+timerThres) ) |
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228 | { |
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229 | if( TimerPauseReg < (pause>>8)); |
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230 | { |
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231 | // save power by idling the processor |
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232 | set_sleep_mode(SLEEP_MODE_IDLE); |
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233 | sleep_mode(); |
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234 | } |
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235 | } |
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236 | |||
237 | /* old inaccurate code, for reference |
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238 | |||
239 | // calculate delay for [pause_ms] milliseconds |
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240 | u16 prescaleDiv = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))); |
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241 | u32 pause = (pause_ms*(F_CPU/(prescaleDiv*256)))/1000; |
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242 | |||
243 | TimerPauseReg = 0; |
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244 | while(TimerPauseReg < pause); |
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245 | |||
246 | */ |
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247 | } |
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248 | |||
249 | void timer0ClearOverflowCount(void) |
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250 | { |
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251 | // clear the timer overflow counter registers |
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252 | Timer0Reg0 = 0; // initialize time registers |
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253 | } |
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254 | |||
255 | long timer0GetOverflowCount(void) |
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256 | { |
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257 | // return the current timer overflow count |
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258 | // (this is since the last timer0ClearOverflowCount() command was called) |
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259 | return Timer0Reg0; |
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260 | } |
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261 | |||
262 | #ifdef TCNT2 // support timer2 only if it exists |
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263 | void timer2ClearOverflowCount(void) |
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264 | { |
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265 | // clear the timer overflow counter registers |
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266 | Timer2Reg0 = 0; // initialize time registers |
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267 | } |
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268 | |||
269 | long timer2GetOverflowCount(void) |
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270 | { |
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271 | // return the current timer overflow count |
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272 | // (this is since the last timer2ClearOverflowCount() command was called) |
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273 | return Timer2Reg0; |
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274 | } |
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275 | #endif |
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276 | |||
277 | void timer1PWMInit(u08 bitRes) |
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278 | { |
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279 | // configures timer1 for use with PWM output |
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280 | // on OC1A and OC1B pins |
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281 | |||
282 | // enable timer1 as 8,9,10bit PWM |
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283 | if(bitRes == 9) |
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284 | { // 9bit mode |
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285 | sbi(TCCR1A,PWM11); |
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286 | cbi(TCCR1A,PWM10); |
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287 | } |
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288 | else if( bitRes == 10 ) |
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289 | { // 10bit mode |
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290 | sbi(TCCR1A,PWM11); |
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291 | sbi(TCCR1A,PWM10); |
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292 | } |
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293 | else |
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294 | { // default 8bit mode |
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295 | cbi(TCCR1A,PWM11); |
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296 | sbi(TCCR1A,PWM10); |
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297 | } |
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298 | |||
299 | // clear output compare value A |
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300 | outb(OCR1AH, 0); |
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301 | outb(OCR1AL, 0); |
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302 | // clear output compare value B |
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303 | outb(OCR1BH, 0); |
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304 | outb(OCR1BL, 0); |
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305 | } |
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306 | |||
307 | #ifdef WGM10 |
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308 | // include support for arbitrary top-count PWM |
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309 | // on new AVR processors that support it |
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310 | void timer1PWMInitICR(u16 topcount) |
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311 | { |
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312 | // set PWM mode with ICR top-count |
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313 | cbi(TCCR1A,WGM10); |
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314 | sbi(TCCR1A,WGM11); |
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315 | sbi(TCCR1B,WGM12); |
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316 | sbi(TCCR1B,WGM13); |
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317 | |||
318 | // set top count value |
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319 | ICR1 = topcount; |
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320 | |||
321 | // clear output compare value A |
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322 | OCR1A = 0; |
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323 | // clear output compare value B |
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324 | OCR1B = 0; |
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325 | |||
326 | } |
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327 | #endif |
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328 | |||
329 | void timer1PWMOff(void) |
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330 | { |
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331 | // turn off timer1 PWM mode |
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332 | cbi(TCCR1A,PWM11); |
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333 | cbi(TCCR1A,PWM10); |
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334 | // set PWM1A/B (OutputCompare action) to none |
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335 | timer1PWMAOff(); |
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336 | timer1PWMBOff(); |
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337 | } |
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338 | |||
339 | void timer1PWMAOn(void) |
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340 | { |
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341 | // turn on channel A (OC1A) PWM output |
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342 | // set OC1A as non-inverted PWM |
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343 | sbi(TCCR1A,COM1A1); |
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344 | cbi(TCCR1A,COM1A0); |
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345 | } |
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346 | |||
347 | void timer1PWMBOn(void) |
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348 | { |
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349 | // turn on channel B (OC1B) PWM output |
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350 | // set OC1B as non-inverted PWM |
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351 | sbi(TCCR1A,COM1B1); |
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352 | cbi(TCCR1A,COM1B0); |
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353 | } |
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354 | |||
355 | void timer1PWMAOff(void) |
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356 | { |
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357 | // turn off channel A (OC1A) PWM output |
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358 | // set OC1A (OutputCompare action) to none |
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359 | cbi(TCCR1A,COM1A1); |
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360 | cbi(TCCR1A,COM1A0); |
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361 | } |
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362 | |||
363 | void timer1PWMBOff(void) |
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364 | { |
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365 | // turn off channel B (OC1B) PWM output |
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366 | // set OC1B (OutputCompare action) to none |
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367 | cbi(TCCR1A,COM1B1); |
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368 | cbi(TCCR1A,COM1B0); |
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369 | } |
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370 | |||
371 | void timer1PWMASet(u16 pwmDuty) |
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372 | { |
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373 | // set PWM (output compare) duty for channel A |
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374 | // this PWM output is generated on OC1A pin |
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375 | // NOTE: pwmDuty should be in the range 0-255 for 8bit PWM |
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376 | // pwmDuty should be in the range 0-511 for 9bit PWM |
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377 | // pwmDuty should be in the range 0-1023 for 10bit PWM |
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378 | //outp( (pwmDuty>>8), OCR1AH); // set the high 8bits of OCR1A |
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379 | //outp( (pwmDuty&0x00FF), OCR1AL); // set the low 8bits of OCR1A |
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380 | OCR1A = pwmDuty; |
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381 | } |
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382 | |||
383 | void timer1PWMBSet(u16 pwmDuty) |
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384 | { |
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385 | // set PWM (output compare) duty for channel B |
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386 | // this PWM output is generated on OC1B pin |
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387 | // NOTE: pwmDuty should be in the range 0-255 for 8bit PWM |
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388 | // pwmDuty should be in the range 0-511 for 9bit PWM |
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389 | // pwmDuty should be in the range 0-1023 for 10bit PWM |
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390 | //outp( (pwmDuty>>8), OCR1BH); // set the high 8bits of OCR1B |
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391 | //outp( (pwmDuty&0x00FF), OCR1BL); // set the low 8bits of OCR1B |
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392 | OCR1B = pwmDuty; |
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393 | } |
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394 | |||
395 | //! Interrupt handler for tcnt0 overflow interrupt |
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396 | TIMER_INTERRUPT_HANDLER(SIG_OVERFLOW0) |
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397 | { |
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398 | Timer0Reg0++; // increment low-order counter |
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399 | |||
400 | // increment pause counter |
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401 | TimerPauseReg++; |
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402 | |||
403 | // if a user function is defined, execute it too |
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404 | if(TimerIntFunc[TIMER0OVERFLOW_INT]) |
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405 | TimerIntFunc[TIMER0OVERFLOW_INT](); |
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406 | } |
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407 | |||
408 | //! Interrupt handler for tcnt1 overflow interrupt |
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409 | TIMER_INTERRUPT_HANDLER(SIG_OVERFLOW1) |
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410 | { |
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411 | // if a user function is defined, execute it |
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412 | if(TimerIntFunc[TIMER1OVERFLOW_INT]) |
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413 | TimerIntFunc[TIMER1OVERFLOW_INT](); |
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414 | } |
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415 | |||
416 | #ifdef TCNT2 // support timer2 only if it exists |
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417 | //! Interrupt handler for tcnt2 overflow interrupt |
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418 | TIMER_INTERRUPT_HANDLER(SIG_OVERFLOW2) |
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419 | { |
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420 | Timer2Reg0++; // increment low-order counter |
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421 | |||
422 | // if a user function is defined, execute it |
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423 | if(TimerIntFunc[TIMER2OVERFLOW_INT]) |
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424 | TimerIntFunc[TIMER2OVERFLOW_INT](); |
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425 | } |
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426 | #endif |
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427 | |||
428 | #ifdef OCR0 |
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429 | // include support for Output Compare 0 for new AVR processors that support it |
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430 | //! Interrupt handler for OutputCompare0 match (OC0) interrupt |
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431 | TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE0) |
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432 | { |
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433 | // if a user function is defined, execute it |
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434 | if(TimerIntFunc[TIMER0OUTCOMPARE_INT]) |
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435 | TimerIntFunc[TIMER0OUTCOMPARE_INT](); |
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436 | } |
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437 | #endif |
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438 | |||
439 | //! Interrupt handler for CutputCompare1A match (OC1A) interrupt |
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440 | TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE1A) |
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441 | { |
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442 | // if a user function is defined, execute it |
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443 | if(TimerIntFunc[TIMER1OUTCOMPAREA_INT]) |
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444 | TimerIntFunc[TIMER1OUTCOMPAREA_INT](); |
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445 | } |
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446 | |||
447 | //! Interrupt handler for OutputCompare1B match (OC1B) interrupt |
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448 | TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE1B) |
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449 | { |
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450 | // if a user function is defined, execute it |
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451 | if(TimerIntFunc[TIMER1OUTCOMPAREB_INT]) |
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452 | TimerIntFunc[TIMER1OUTCOMPAREB_INT](); |
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453 | } |
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454 | |||
455 | //! Interrupt handler for InputCapture1 (IC1) interrupt |
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456 | TIMER_INTERRUPT_HANDLER(SIG_INPUT_CAPTURE1) |
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457 | { |
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458 | // if a user function is defined, execute it |
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459 | if(TimerIntFunc[TIMER1INPUTCAPTURE_INT]) |
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460 | TimerIntFunc[TIMER1INPUTCAPTURE_INT](); |
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461 | } |
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462 | |||
463 | //! Interrupt handler for OutputCompare2 match (OC2) interrupt |
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464 | TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE2) |
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465 | { |
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466 | // if a user function is defined, execute it |
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467 | if(TimerIntFunc[TIMER2OUTCOMPARE_INT]) |
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468 | TimerIntFunc[TIMER2OUTCOMPARE_INT](); |
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469 | } |
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