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| 1 | 6 | kaklik | /*! \file uartsw2.c \brief Software Interrupt-driven UART Driver. */ |
| 2 | //***************************************************************************** |
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| 3 | // |
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| 4 | // File Name : 'uartsw2.c' |
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| 5 | // Title : Software Interrupt-driven UART Driver |
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| 6 | // Author : Pascal Stang - Copyright (C) 2002-2004 |
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| 7 | // Created : 7/20/2002 |
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| 8 | // Revised : 4/27/2004 |
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| 9 | // Version : 0.6 |
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| 10 | // Target MCU : Atmel AVR Series (intended for the ATmega16 and ATmega32) |
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| 11 | // Editor Tabs : 4 |
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| 12 | // |
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| 13 | // This code is distributed under the GNU Public License |
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| 14 | // which can be found at http://www.gnu.org/licenses/gpl.txt |
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| 15 | // |
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| 16 | //***************************************************************************** |
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| 17 | |||
| 18 | #include <avr/io.h> |
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| 19 | #include <avr/interrupt.h> |
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| 20 | |||
| 21 | #include "global.h" |
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| 22 | #include "timer.h" |
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| 23 | #include "uartsw2.h" |
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| 24 | |||
| 25 | // Program ROM constants |
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| 26 | |||
| 27 | // Global variables |
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| 28 | |||
| 29 | // uartsw transmit status and data variables |
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| 30 | static volatile u08 UartswTxBusy; |
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| 31 | static volatile u08 UartswTxData; |
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| 32 | static volatile u08 UartswTxBitNum; |
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| 33 | |||
| 34 | // baud rate common to transmit and receive |
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| 35 | static volatile u08 UartswBaudRateDiv; |
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| 36 | |||
| 37 | // uartsw receive status and data variables |
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| 38 | static volatile u08 UartswRxBusy; |
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| 39 | static volatile u08 UartswRxData; |
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| 40 | static volatile u08 UartswRxBitNum; |
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| 41 | // receive buffer |
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| 42 | static cBuffer uartswRxBuffer; ///< uartsw receive buffer |
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| 43 | // automatically allocate space in ram for each buffer |
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| 44 | static char uartswRxData[UARTSW_RX_BUFFER_SIZE]; |
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| 45 | |||
| 46 | // functions |
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| 47 | |||
| 48 | //! enable and initialize the software uart |
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| 49 | void uartswInit(void) |
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| 50 | { |
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| 51 | // initialize the buffers |
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| 52 | uartswInitBuffers(); |
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| 53 | // initialize the ports |
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| 54 | sbi(UARTSW_TX_DDR, UARTSW_TX_PIN); |
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| 55 | #ifdef UARTSW_INVERT |
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| 56 | cbi(UARTSW_TX_PORT, UARTSW_TX_PIN); |
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| 57 | #else |
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| 58 | sbi(UARTSW_TX_PORT, UARTSW_TX_PIN); |
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| 59 | #endif |
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| 60 | cbi(UARTSW_RX_DDR, UARTSW_RX_PIN); |
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| 61 | cbi(UARTSW_RX_PORT, UARTSW_RX_PIN); |
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| 62 | // initialize baud rate |
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| 63 | uartswSetBaudRate(9600); |
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| 64 | |||
| 65 | // setup the transmitter |
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| 66 | UartswTxBusy = FALSE; |
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| 67 | // disable OC2 interrupt |
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| 68 | cbi(TIMSK, OCIE2); |
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| 69 | // attach TxBit service routine to OC2 |
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| 70 | timerAttach(TIMER2OUTCOMPARE_INT, uartswTxBitService); |
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| 71 | |||
| 72 | // setup the receiver |
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| 73 | UartswRxBusy = FALSE; |
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| 74 | // disable OC0 interrupt |
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| 75 | cbi(TIMSK, OCIE0); |
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| 76 | // attach RxBit service routine to OC0 |
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| 77 | timerAttach(TIMER0OUTCOMPARE_INT, uartswRxBitService); |
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| 78 | // INT2 trigger on rising/falling edge |
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| 79 | #ifdef UARTSW_INVERT |
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| 80 | sbi(MCUCSR, ISC2); // rising edge |
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| 81 | #else |
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| 82 | cbi(MCUCSR, ISC2); // falling edge |
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| 83 | #endif |
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| 84 | // enable INT2 interrupt |
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| 85 | sbi(GICR, INT2); |
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| 86 | |||
| 87 | // turn on interrupts |
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| 88 | sei(); |
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| 89 | } |
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| 90 | |||
| 91 | //! create and initialize the uart buffers |
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| 92 | void uartswInitBuffers(void) |
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| 93 | { |
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| 94 | // initialize the UART receive buffer |
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| 95 | bufferInit(&uartswRxBuffer, uartswRxData, UARTSW_RX_BUFFER_SIZE); |
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| 96 | } |
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| 97 | |||
| 98 | //! turns off software UART |
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| 99 | void uartswOff(void) |
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| 100 | { |
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| 101 | // disable interrupts |
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| 102 | cbi(TIMSK, OCIE2); |
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| 103 | cbi(TIMSK, OCIE0); |
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| 104 | cbi(GICR, INT2); |
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| 105 | // detach the service routines |
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| 106 | timerDetach(TIMER2OUTCOMPARE_INT); |
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| 107 | timerDetach(TIMER0OUTCOMPARE_INT); |
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| 108 | } |
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| 109 | |||
| 110 | void uartswSetBaudRate(u32 baudrate) |
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| 111 | { |
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| 112 | u16 div; |
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| 113 | |||
| 114 | // set timer prescaler |
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| 115 | if( baudrate > (F_CPU/64L*256L) ) |
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| 116 | { |
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| 117 | // if the requested baud rate is high, |
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| 118 | // set timer prescalers to div-by-64 |
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| 119 | timer2SetPrescaler(TIMERRTC_CLK_DIV64); |
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| 120 | timer0SetPrescaler(TIMER_CLK_DIV64); |
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| 121 | div = 64; |
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| 122 | } |
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| 123 | else |
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| 124 | { |
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| 125 | // if the requested baud rate is low, |
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| 126 | // set timer prescalers to div-by-256 |
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| 127 | timer2SetPrescaler(TIMERRTC_CLK_DIV256); |
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| 128 | timer0SetPrescaler(TIMER_CLK_DIV256); |
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| 129 | div = 256; |
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| 130 | } |
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| 131 | |||
| 132 | // calculate division factor for requested baud rate, and set it |
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| 133 | //UartswBaudRateDiv = (u08)(((F_CPU/64L)+(baudrate/2L))/(baudrate*1L)); |
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| 134 | //UartswBaudRateDiv = (u08)(((F_CPU/256L)+(baudrate/2L))/(baudrate*1L)); |
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| 135 | UartswBaudRateDiv = (u08)(((F_CPU/div)+(baudrate/2L))/(baudrate*1L)); |
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| 136 | } |
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| 137 | |||
| 138 | //! returns the receive buffer structure |
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| 139 | cBuffer* uartswGetRxBuffer(void) |
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| 140 | { |
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| 141 | // return rx buffer pointer |
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| 142 | return &uartswRxBuffer; |
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| 143 | } |
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| 144 | |||
| 145 | void uartswSendByte(u08 data) |
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| 146 | { |
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| 147 | // wait until uart is ready |
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| 148 | while(UartswTxBusy); |
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| 149 | // set busy flag |
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| 150 | UartswTxBusy = TRUE; |
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| 151 | // save data |
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| 152 | UartswTxData = data; |
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| 153 | // set number of bits (+1 for stop bit) |
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| 154 | UartswTxBitNum = 9; |
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| 155 | |||
| 156 | // set the start bit |
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| 157 | #ifdef UARTSW_INVERT |
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| 158 | sbi(UARTSW_TX_PORT, UARTSW_TX_PIN); |
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| 159 | #else |
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| 160 | cbi(UARTSW_TX_PORT, UARTSW_TX_PIN); |
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| 161 | #endif |
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| 162 | // schedule the next bit |
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| 163 | outb(OCR2, inb(TCNT2) + UartswBaudRateDiv); |
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| 164 | // enable OC2 interrupt |
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| 165 | sbi(TIMSK, OCIE2); |
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| 166 | } |
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| 167 | |||
| 168 | //! gets a byte (if available) from the uart receive buffer |
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| 169 | u08 uartswReceiveByte(u08* rxData) |
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| 170 | { |
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| 171 | // make sure we have a receive buffer |
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| 172 | if(uartswRxBuffer.size) |
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| 173 | { |
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| 174 | // make sure we have data |
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| 175 | if(uartswRxBuffer.datalength) |
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| 176 | { |
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| 177 | // get byte from beginning of buffer |
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| 178 | *rxData = bufferGetFromFront(&uartswRxBuffer); |
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| 179 | return TRUE; |
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| 180 | } |
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| 181 | else |
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| 182 | { |
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| 183 | // no data |
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| 184 | return FALSE; |
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| 185 | } |
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| 186 | } |
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| 187 | else |
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| 188 | { |
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| 189 | // no buffer |
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| 190 | return FALSE; |
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| 191 | } |
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| 192 | } |
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| 193 | |||
| 194 | void uartswTxBitService(void) |
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| 195 | { |
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| 196 | if(UartswTxBitNum) |
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| 197 | { |
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| 198 | // there are bits still waiting to be transmitted |
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| 199 | if(UartswTxBitNum > 1) |
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| 200 | { |
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| 201 | // transmit data bits (inverted, LSB first) |
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| 202 | #ifdef UARTSW_INVERT |
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| 203 | if( !(UartswTxData & 0x01) ) |
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| 204 | #else |
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| 205 | if( (UartswTxData & 0x01) ) |
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| 206 | #endif |
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| 207 | sbi(UARTSW_TX_PORT, UARTSW_TX_PIN); |
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| 208 | else |
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| 209 | cbi(UARTSW_TX_PORT, UARTSW_TX_PIN); |
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| 210 | // shift bits down |
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| 211 | UartswTxData = UartswTxData>>1; |
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| 212 | } |
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| 213 | else |
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| 214 | { |
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| 215 | // transmit stop bit |
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| 216 | #ifdef UARTSW_INVERT |
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| 217 | cbi(UARTSW_TX_PORT, UARTSW_TX_PIN); |
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| 218 | #else |
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| 219 | sbi(UARTSW_TX_PORT, UARTSW_TX_PIN); |
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| 220 | #endif |
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| 221 | } |
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| 222 | // schedule the next bit |
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| 223 | outb(OCR2, inb(OCR2) + UartswBaudRateDiv); |
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| 224 | // count down |
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| 225 | UartswTxBitNum--; |
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| 226 | } |
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| 227 | else |
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| 228 | { |
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| 229 | // transmission is done |
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| 230 | // clear busy flag |
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| 231 | UartswTxBusy = FALSE; |
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| 232 | // disable OC2 interrupt |
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| 233 | cbi(TIMSK, OCIE2); |
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| 234 | } |
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| 235 | } |
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| 236 | |||
| 237 | void uartswRxBitService(void) |
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| 238 | { |
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| 239 | // this function runs on either: |
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| 240 | // - a rising edge interrupt |
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| 241 | // - Timer 0 output compare |
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| 242 | if(!UartswRxBusy) |
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| 243 | { |
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| 244 | // UART was not previously busy, |
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| 245 | // this must be is a start bit |
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| 246 | |||
| 247 | // disable INT2 interrupt |
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| 248 | cbi(GICR, INT2); |
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| 249 | // schedule data bit sampling 1.5 bit periods from now |
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| 250 | outb(OCR0, inb(TCNT0) + UartswBaudRateDiv + UartswBaudRateDiv/2); |
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| 251 | // clear OC0 interrupt flag |
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| 252 | sbi(TIFR, OCF0); |
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| 253 | // enable OC0 interrupt |
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| 254 | sbi(TIMSK, OCIE0); |
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| 255 | // set busy flag |
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| 256 | UartswRxBusy = TRUE; |
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| 257 | // reset bit counter |
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| 258 | UartswRxBitNum = 0; |
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| 259 | // reset data |
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| 260 | UartswRxData = 0; |
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| 261 | } |
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| 262 | else |
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| 263 | { |
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| 264 | // start bit has already been received |
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| 265 | // we're in the data bits |
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| 266 | |||
| 267 | // shift data byte to make room for new bit |
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| 268 | UartswRxData = UartswRxData>>1; |
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| 269 | |||
| 270 | // sample the data line |
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| 271 | #ifdef UARTSW_INVERT |
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| 272 | if( !(inb(UARTSW_RX_PORTIN) & (1<<UARTSW_RX_PIN)) ) |
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| 273 | #else |
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| 274 | if( (inb(UARTSW_RX_PORTIN) & (1<<UARTSW_RX_PIN)) ) |
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| 275 | #endif |
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| 276 | { |
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| 277 | // serial line is marking |
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| 278 | // record '1' bit |
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| 279 | UartswRxData |= 0x80; |
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| 280 | } |
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| 281 | |||
| 282 | // increment bit counter |
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| 283 | UartswRxBitNum++; |
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| 284 | // schedule next bit sample |
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| 285 | outb(OCR0, inb(OCR0) + UartswBaudRateDiv); |
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| 286 | |||
| 287 | // check if we have a full byte |
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| 288 | if(UartswRxBitNum >= 8) |
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| 289 | { |
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| 290 | // save data in receive buffer |
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| 291 | bufferAddToEnd(&uartswRxBuffer, UartswRxData); |
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| 292 | // disable OC0 interrupt |
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| 293 | cbi(TIMSK, OCIE0); |
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| 294 | // clear INT2 interrupt flag |
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| 295 | sbi(GIFR, INTF2); |
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| 296 | // enable INT interrupt |
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| 297 | sbi(GICR, INT2); |
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| 298 | // clear busy flag |
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| 299 | UartswRxBusy = FALSE; |
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| 300 | } |
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| 301 | } |
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| 302 | } |
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| 303 | |||
| 304 | SIGNAL(SIG_INTERRUPT2) |
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| 305 | { |
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| 306 | // run RxBit service routine |
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| 307 | uartswRxBitService(); |
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| 308 | } |
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