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\chap Testing construction
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\sec Required parameters
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Wide dynamical range and high 3 intercept point are desired. The receiver must accept wide dynamic signals because radioastronomical signal in typically weak signal covered by strong man made noise signal.
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%\sec Sampling frequency
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%\sec System scalability
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%\secc Differential signaling
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\sec System description
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% \secc Frequency synthesis
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\secc Signal connectors
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Several widely used and commercially easily accessible differential connectors was considered.
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\begitems
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* <del>[[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
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* [[http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]
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* <del>[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>
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\enditems
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MiniSAS connector was chosen as the best for use in connection multiple ADC modules. This miniSAS connector is compatible with existing SATA cabling system. Translation between SATA and miniSAS is achieved by SAS to SATA adapter cable. This cable is used in servers to connecting SAS controller to multiple SATA hard disc in RAID systems.
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\secc Design of ADC modules
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For PCB layout KiCAD design suite was used. Used version has the CERN Push \& Shove routing capability integrated but was slightly unstable and sometimes falls on exception during routing. Design must be often saved due to this stability issues. But Open-source KiCAD works well compared to commercial solutions as MentorGraphics PADS or Cadence Orcad.
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\secc ADC modules interface
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All two ADCdual01A modules was connected to FPGA ML605 board trough
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\midinsert
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\picw=10cm \cinspic ./img/ML605-board.jpg
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\caption/f Used FPGA ML605 development board.
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\endinsert
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\secc Output data format
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\midinsert
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\ctable {cccccccccc}{
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\hfil
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& \multispan9 \hfil 160bit packet \hfil \crl \tskip4pt
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Data name & FRAME & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2 \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil \cr
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Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr
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Content & saw signal & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ \cr
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}
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\caption/t System device "/dev/xillybus_data2_r" data format
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\endinsert
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\sec Achieved parameters
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\secc Data reading and recording
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For reading data stream from ADC driver Gnuradio software was used. Gnuradio suite consist gnuradio-companion which is a graphical tool for creating signal flow graphs and generating flow-graph source code. This tool was used to create basic RAW data grabber to record and interactive wiev data stream output from ADC modules.
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\midinsert
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\picw=15cm \cinspic ./img/screenshots/Grabber.grc.png
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\caption/f ADC recorder flow graph created in gnuradio-companion.
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\endinsert
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\midinsert
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\picw=15cm \cinspic ./img/screenshots/Grabber_running.png
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\caption/f User interface window of running ADC grabber.
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\endinsert
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Interactive graber wiewer user interface shows live osciloscope-like time-value display for all data channels and live time-frequency scrolling display (waterfall wiev) for displaying frequency components of grabbed signal.
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%\sec Future improvements
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%\chap Example of usage
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%\sec Simple polarimeter station
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%\sec Basic interferometer station
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%\sec Simple passive Doppler radar
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%\chap Proposed final system
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%\sec Custom design of FPGA board
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%\sec Parralella board computer
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%\chap Conclusion
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