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\chap Trial design

The whole design of radioastronomy receiver digitalization unit is constructed to be used in a wide range of applications and tasks related to digitalisation of signal from radioastronomy receivers. A good illustrating problem for its use is a signal digitalisation from multiple antenna arrays. This design will eventually become a part of MLAB Advanced Radio Astronomy System. 

\sec Required parameters

Wide dynamical range and high 3 intercept points are desired. The receiver must accept wide dynamic signals because a typical radioastronomy signal has a form of a weak signal covered by a strong man-made noise signal.    

\begitems

  * Dynamical range better than 80 dB

  * Phase stability between channels 

  * Noise (all types)

  * Sampling jitter better than 100 metres

\enditems

\sec Sampling frequency

Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market. Combination of the required parameters -- dynamic range which needs at least 16bit and a minimum sampling frequency of 1 MSPS, leads to high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5 MSPS.  

\sec System scalability

For analog channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each I/Q channel in ACD module. ADC module must also have separate inputs for sampling and data output clocks. These parameters allow for conduction at relatively low digital data rates. Then the digital signal can be conducted even through long wires. 

Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes. (Failure detection, jitter measurement etc.)   

This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power.  There is another advantage of scalable data acquisition system -- economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.     

\secc Differential signalling 

The concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA or other flip-flops block and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such case any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time a long distance brings problems with the digital signal transmission between ADC and computational unit. This obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used. This technology have two advantages over PCB signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path. Moreover, the twisted pair may additionally be shielded by uninterrupted metal foil.              

\secc Phase matching

For multiple antenna radioastronomy projects, system phase stability is mandatory. It allows precise high resolution imaging of objects. 

High phase stability in our scalable design is achieved by centralised frequency generation  and distribution with multi-output LVPECL hubs, that have equiphased outputs for multiple devices. 

This design ensures that all devices have access to defined phase and known frequency.     

\sec System description

In this section testing system will be described.

\secc Frequency synthesis       

We have used centralised topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used while other working frequencies have been derived by its division. This central oscillator has a software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by specification.}

 This method has been used in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability on wide area for effective radioastronomy imaging. 

Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock delivered by FPGA from main local oscillator.  This signal should use high quality differential signaling cable -- SATA cable should be used for this purpose. 

\secc Signal cable connectors 

Several widely used and commercially easily accessible differential connectors were considered. 

\begitems

* HDMI % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>

* SATA  		%{http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]

* DisplayPort 		%[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>

* SAS/miniSAS

\enditems

MiniSAS connector was chosen as  the best to be used in connecting multiple ADC modules.  The miniSAS connector is compatible with existing SATA cabling system and aggregates multiple SATA cables to a single connector this cable type is shown on image \ref[img-miniSAS-cable]. Translation between SATA and miniSAS is achieved by SAS to SATA adapter cable which is used in servers to connecting SAS controller to multiple SATA hard disc in RAID systems thus is commercially available. 

One drawback is that miniSAS PCB connectors are manufactured in SMT versions only. But outer metal housing of connector is standard trough hole type. This mechanical design should degrade durability of this connector type. 

\midinsert

\clabel[img-miniSAS-cable]{Used miniSAS cable}

\picw=10cm \cinspic ./img/miniSAS_SATA_cable.jpg

\caption/f A type of miniSAS cable similar to used.

\endinsert

\secc Signal integrity requirements

Used ADC modules has DATA clock frequency eight times higher than sampling frequency in single line output mode. This implicates 40 MHz output bit rate. 

\secc Design of ADC modules

This modules have MLAB standard construction with four mounting holes in corner aligned in defined raster. 

Data serial data output of ADC module should be connected directly to FPGA for basic primary signal processing. Used ADC chip has selectable bit width of data output bus thus output SATA connectors has signals arranged to contain a single bit from every ADC channel.  This signal concept enables selection of proper bus bitwidth according to sampling rate. (Higher bus bit-width downgrades signalling speed and vice versa.)

For connection of this signaling layout, miniSAS to multiple SATA cable should be used.  

For PCB layout KiCAD design suite was used. Used version has the CERN Push \& Shove routing capability integrated but was slightly unstable and sometimes falls on exception during routing. Design must be often saved due to this stability issues. But Open-source KiCAD works well compared to commercial solutions as MentorGraphics PADS or Cadence Orcad.  And much better than widely used Eagle software.

New PCB footprints have been designed for FMC, SATA a and miniSAS connectors. These new footprints were committed to KiCAD github library repository. And they are now publicly accessible from official KiCAD repository at GitHub.  

\secc ADC selection

Several ADC signaling formats currently exist for communication with FPGA. 

\begitems

  * DDR LVDS

  * JEDEC 204B

  * JESD204A

  * Paralel LVDS

  * Serdes

  * serial LVDS

\enditems

Serial LVDS has been selected because uses lowest number of differencial pairs. This parameter is mandatory for construction complexity and reliability. \url{http://www.ti.com/lit/pdf/snaa110}

An ultrasound AFE chips should be ideal for this purpose -- this chips has front-end amplifiers and filters integrated. But theirs drawback is incapability of handling differential input signal and relatively low dynamic range (consists 12bit ADC). This IO has many ADC channels thus scaling are possible in factor of 4 receivers (8 analogue channels).

If we require separate output for every analogue channel and 16bit deph. Only several 2-Channel simultaneous sampling ADCs currently exists which meet these requirements.  These ADCs parameters are summarised in table \ref[ADC-type] 

\midinsert \clabel[ADC-types]{Available ADC types}

\ctable{lrrrrrcc}{

\hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr

SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8 \cr

SFDR [dB] & 99 & 90 & 90 & 90 & 90 & 90 & 90 \cr

S/H Bandwidth [MHz] & 200 & \multispan6 550 \cr

Sampling rate [MSPS] & 20 & 25 & 40 & 65 & 80 &  105 & 125 \cr

Configuration & \multispan7 SPI \cr

Package & \multispan7 52-Lead (7mm $×$ 8mm) QFN \cr

}

\caption/t Summary of available ADC types and theirs parameters. 

\endinsert

All parts in this category are compatible with one board layout. Main differences are in sampling frequency and signal to noise ratio. The slowest one has maximal sampling frequency 20 MHz. But all types have minimal sampling frequency 5 MSPS.  All types were configurable over serial interface (SPI).  SPI seems to be a standard for high-end ADC chips from main manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..). 

\secc ADC modules interface

All two ADCdual01A modules was connected to FPGA ML605 board trough FMC2DIFF01A adapter board. Construction of this adapter module suppose FMC LPC connector. And this board is not MLAB compatible design. But this board is designed to meet VITA 57 standard specification for boards which uses zone 1 and zone 3. 

This specification guarantee compatibility with others FPGA board which has FMC LPC connector for mezzane cards. Schematic diagram of this adapter board is included in appendix. 

Primary purpose of this PCB is to enable connection of ADC modules from space excluded from PC case.  (In PC box analog circuits cannot be realised without using of massive RFI mitigation techniques). 

Differential signaling connectors should be used for conducting digital signal over relatively long cable. Signalintegrity sensitive links (clocks) are equiped by output driver and translator to LVPECL logic for better signal transmission quality.  

\midinsert

\picw=10cm \cinspic ./img/ML605-board.jpg

\caption/f Used FPGA ML605 development board.

\endinsert

Several SATA connectors and two miniSAS connectors are populated on this board.  This set of connectors allows connection of any number of ADC modules in range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors. Other supporting signal should be routed directly to SATA connectors on adapter. 

Signal configuration used in testing construction is described in tables. 

\secc Output data format

\midinsert

\ctable {clllllllll}{

\hfil

 & \multispan9 \hfil 160bit packet \hfil \crl \tskip4pt

Data name &  FRAME  & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2  \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil  \cr

Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr

Content & saw signal & $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ \cr

}

\caption/t System device "/dev/xillybus_data2_r" data format

\endinsert

\sec Achieved parameters

\secc Data reading and recording 

For reading data stream from ADC driver Gnuradio software was used. Gnuradio suite consist gnuradio-companion which is a graphical tool for creating signal flow graphs and generating flow-graph source code. This tool was used to create basic RAW data grabber to record and interactive wiev data stream output from ADC modules. 

\midinsert

\picw=15cm \cinspic ./img/screenshots/Grabber.grc.png

\caption/f ADC recorder flow graph created in gnuradio-companion.

\endinsert

\midinsert

\picw=15cm \cinspic ./img/screenshots/Grabber_running.png

\caption/f User interface window of running ADC grabber.

\endinsert

Interactive graber wiewer user interface shows live osciloscope-like time-value display for all data channels and live time-frequency scrolling display (waterfall wiev) for displaying frequency components of grabbed signal. 

\secc ADC module parameters

Two pieces of ADC module design were realised and tested first piece denoted as ADC1 has LTC21190

ADC chip populated with LT660015 front-end operational apmlifier. This ADC1 module has 1kOhm resistors populated on inputs which gives to module internal attenuation of input signal. Value of this attenuation $A$ is described by formula 

$$

A = {1580 \times R_1 \over R_1 + R_2}

$$

\midinsert

\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png

\caption/f Sine signal from ADC1 module with LTC21190 and LT6600-5 devices.

\endinsert

T

ADC1 CH1  maximal input 705.7 mV

\midinsert

\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png

\caption/f Sine signal from ADC1 module with LTC21190 and LT6600-5 devices.

\endinsert

LTC2271

6600125

1k

ADC2 CH1 maximal input 380 mV

%\chap Example of usage

%\sec Simple polarimeter station

%\sec Basic interferometer station

%\sec Simple passive Doppler radar

\chap Proposed final system

Construction of final system which should be used for real radioastronomy observations will be described. This chapter is mainly theoretical analysis of systems which should be used for data handling. Realisation of these ideas are planed for future development after full evaluation and testing of actual functional example design. 

\sec Custom design of FPGA board

In beginning of the project coustom design of FPGA interface board was supposed. This FPGA board should include PCI express interface and should have lower price than functional example construction. This board should have MLAB compatible design which is backward compatible with existing or improved design of ADC modules. For connection of this board an another adapter board with PCIe host interface was supposed. 

Thunderbolt technology standard was supposed for use in this PC to PCIe -> FPGA module. Thunderbolt chips are currently available on the market for reasonable prices. But specification for these devices are accessible for licensed users only and Intel has mass market oriented licensing policy,   which makes this technology inaccessible for low quantity product design.  In consequence of this external PCI Express cabling and expansion slots should be better solution. 

But this systems and cables are still very expensive. For example (http://www.opalkelly.com/products/xem6110/) has price tag 995 USD at time of writing this thesis.

Therefore better approach must be found.

\sec Parralella board computer

Parallella is gon

\sec GPU based computational system 

A new GPU development board NVIDIA K1 has been released in recent time it is shown on image \ref[img-NVIDIA-K1]. This board are intended for use in computer vision, robotics, medicine, security, and automotive. This board has ideal parameters for signal processing for this relatively low price 192 USD.  But it is currently in pre-order release stage (in April 2014). 

\midinsert

\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}

\picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg

\caption/f The NVIDIA Jetson TK1 Development Kit \url{https://developer.nvidia.com/jetson-tk1}.

\endinsert

\chap Conclusion 

Special design of scalable data-aquisition system was proposed. This system has parameters 

\sec Possible future improvements

Several ADC module imperfections, such as useless separation of FRAME and DCO signal to two connectors, should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest.