Subversion Repositories svnkaklik

\chap Results obtained in the trial version

The trial version construction was tested for proper handling of sampling rates in the range of 5 MSPS to 15 MSPS, but it should work even above this limit. The system works on i7 8 cores computer with Ubuntu 12.04 LTS operating system. Data recording of input signal is impossible above the sampling rates of around 7 MSPS due to bottleneck at HDD speed limits, but it should be resolved by the use of SSD disk drive. However, such design has not been tested in our setup.

\sec Measured parameters

Two prototypes of ADC modules were assembled and tested. The first prototype, labeled ADC1, has LTC2190 ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which give it an ability of an internal attenuation of the input signal. The value of this attenuation $A$ is calculated by the following formula \ref[ADC1-gain]

\label[ADC1-gain]

$$

A = {806 \cdot R_1 \over R_1 + R_2} \eqmark

$$

Where the letters stand for the following:

\begitems

  * $A$ -  Gain of an input amplifier.

  * $R_1$ - Output impedance of signal source (usually 50 Ohm).

  * $R_2$ - Value of serial resistors at operational amplifier inputs.

\enditems

We have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply that $A = 0.815$. That value of A was further confirmed by the measurement.

In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator. Circuit diagram of the used transformer circuit is shown in picture \ref[balun-circuit]  and circuit realization in photograph \ref[SMA2SATA-nest].

\midinsert

\clabel[balun-circuit]{Balun transformer circuit}

\picw=10cm \cinspic ./img/SMA2SATA.pdf

\caption/f Simplified balun transformer circuit diagram.

\endinsert

The signal generator Agilent 33220A which we used, does not have optimal parameters for this type of dynamic range measurement. Signal distortion and spurious levels are only -70 dBc according to Agilent datasheet \cite[33220A-generator]. We have managed to measure an ADC saturation voltage of 705.7 mV (generator output) with this setup, mostly due to an impedance mismatch and uncalibrated measurement setup, with 1V ADC range selected by sense pin. This is a relatively large error, but the main result of our measurement, seen as a FFT plot shown in image \ref[ADC1-FFT], confirms $>$80 dB dynamic range at ADC module input.

\midinsert

\clabel[ADC1-FFT]{ADC1 sine test FFT}

\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png

\caption/f Sine signal sampled by ADC1 module with LTC2190 and LT6600-5 devices.

\endinsert

Similar test was performed at ADC2 module. For ADC2 we have to use formula with a different constant \ref[ADC1-gain]. The ADC2 module has LT6600-2.5 amplifiers populated on it with a gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well within the parameter tolerances of the used setup.

\label[ADC2-gain]

$$

A = {1580 \cdot R_1 \over R_1 + R_2} \eqmark

$$

Where the letters stand for the following:

\begitems

  * $A$ -  Gain of an input amplifier.

  * $R_1$ - Output impedance of signal source (usually 50 Ohm).

  * $R_2$ - Value of serial resistors at operational amplifier inputs.

\enditems

\midinsert

\clabel[ADC2-FFT]{ADC2 sine test FFT}

\picw=15cm \cinspic ./img/screenshots/ADC2_CH1_FFT.png

\caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices.

\endinsert

Computed FFT spectra for measured signal are shown in the images \ref[ADC2-FFT] and \ref[ADC1-FFT].  Both images confirm that ADCdual01A modules have input dynamical range of at least 80 dB.

\midinsert

\clabel[SMA2SATA-nest]{Used balun transformer}

\picw=15cm \cinspic ./img/SMA2SATA_nest1.JPG

\caption/f Balun transformer circuit used for ADC parameters measurement. It is constructed from H1012 transformer salvaged from an old Ethernet card.

\endinsert

\sec Example of usage

At current state the constructed radioastronomy digitization unit paired with SDRX01B receiver module could be used in several experiments. We describe overall ideas of these experiments and show preliminary results in cases where we obtain the data.  

\secc Simple polarimeter station

If we use two antennas with different linear polarization (Crossed Yagi antennas for example), we should determine polarization state of received signal. Such kind of measurement is useful if we need an additional information about reflection to distinguish between targets. This configuration needs more complicated antenna configuration and we had no experience with this type of observation, so we have not implemented this experiment.

\secc Basic interferometric station

Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in the image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N,  14$^\circ$ 25' 4.170'' E.

Antennae were equipped with LNA01A amplifiers. All coaxial cables had the same length of 5 meters. Antennae were isolated by common mode ferrite bead mounted on cable to minimise the signal coupling between antennas. Evaluation system consisted of SDGPSDO local oscillator subsystem used to tune the local oscillator frequency.

\midinsert

\clabel[block-schematic]{Receiver block schematic}

\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Basic_interferometer.png }

\par\nobreak \vskip\wd0 \vskip-\ht0

\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}

\caption/f Complete receiver block schematic of dual antenna interferometric station.

\endinsert

Despite of the schematic diagram proposed at beginning of system description \ref[expected-block-schematic].

We have used two separate oscillators -- one oscillator drives ENC signal to ADCs still through FPGA based divider and the other one drives it to SDRX01B mixer.

The reason for this modification was an attempt to simplify the frequency tuning during the experiment. A single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA schema. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA scheme is changed. Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver.

We have used ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators.

\midinsert

\clabel[phase-difference]{Phase difference}

\picw=10cm \cinspic ./img/screenshots/phase_difference.png

\caption/f Demonstration of phase difference between antennae.

\endinsert

For the simplest demonstration of phase difference between antennae, we have analysed part of the signal by complex conjugate multiplication between channels. Results of this analysis can be seen in the following picture \ref[phase-difference]. Points of the selected part of the signal create a clear vector, which illustrates the presence of the constant phase difference determined by RF source direction.

\secc Simple passive Doppler radar

If we use an existing transmitter with known carrier frequency and proper antenna,  we can detect flying object as signals surrounding the transmitter carrier frequency. We planned this experiment with the same station configuration as was described in section \ref[expected-block-schematic]. The ISS \glos{ISS}{International Space Station} as object and GRAVES radar transmitter were selected as adequate testing objects (We know ISS reflections from previous experiments). This experiment could be realised by previously described interferometer station,  but unfortunately we missed the suitable orbit pass due to technical lacks with station configuration.

\secc Meteor detection station

The same observational station configuration should be used for meteor detection system \cite[mlab-rmds]. We used the GRAVES radar as suitable signal source and monitored its carrier frequency. GRAVES radar is located in France therefore we could not see its direct carrier signal, but meteors reflect it signal and as consequence we could easily detect meteor presence as reflection appearance. One meteor detected by this method is shown in picture \ref[meteor-reflection].

\midinsert

\clabel[meteor-reflection]{Meteor reflection}

\picw=10cm \cinspic ./img/screenshots/observed_meteor.png

\caption/f Meteor reflection (the red spot in centre of image) received by an evaluation design.

\endinsert

\chap Proposition of the final system

The construction of the final system, that is supposed to be employed for real radioastronomy observations will be described in this chapter. It is mainly a theoretical analysis of the data handling systems. Realization of the described ideas might be possible as a part of our future development after we fully evaluate and test the current trial design.

The system requires proper handling of huge amounts of data and either huge and fast storage capacity is needed to store the captured signal data, or enormous computational power is required for online data processing and filtering. Several hardware approaches currently exist and are in use for data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially  constructed ASICs are used for this task.

\sec Custom design of FPGA board

In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than the trial design. It should be compatible with MLAB internal standards  which are further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface.

Thunderbolt technology standard was expected to be used in this PC to PCIe module communication which further communicates with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as they are only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need to preserve standard PC as a main computational platform.

However, these PCI express external systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing the thesis. Therefore, a better solution probably needs to be found.

An interface problem will by probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to an increased demand of embedded technologies, which require high computation capacity, low power consumption and small size -- especially smartphones. Many of those ARM based systems have interesting parameters of signal processing. These facts make Intel's ix86 architecture unattractive for future projects.

\sec Parralella board computer

Parallella is a new product created by Adapteva, Inc. \cite[parallella-board]. It represents a small supercomputer, that has been in development for almost two years with only testing series of boards produced until now (first single-board computers with 16-core Epiphany chip were shipped in December 2013) \cite[parallella-board]. The board has nearly ideal parameters for signal processing (as it provides around 50 GFLOPS of computational power). It is is equipped with Epiphany coprocessor which has 16 High Performance RISC CPU Cores,  Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and operating frequency of 866 MHz, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition to this, the board consumes only 3 Watts of power if both Zynq and Epiphany cores are running simultaneously.

The main disadvantage of Parralella board is its unknown lead time and an absence of SATA interface or other interface suitable for data storage connection. Fast data storage interface would be useful and would allow bulk processing of captured data. Following that, the results of data processing may be sent over the Ethernet interface to data storage server.

\midinsert

\clabel[img-parallella-board]{Parallella board overview}

\picw=15cm \cinspic ./img/ParallellaTopView31.png

\caption/f Top view on Parallella-16 board \cite[parallella16-board].

\endinsert

If Parallella board will be used as a radioastronomy data interface, there would be a demand for new ADC interface module. The interface module will use four PEC connectors mounted on the bottom of the Parallella board. This daughter module should have MLAB compatible design and should preferably be constructed in the form of separable modules for every Parallella's PEC connector.

\sec GPU based computational system

A new GPU development board NVIDIA K1, shown in the following picture \ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have good parameters for signal processing for a relatively low price of 192 USD.  Unfortunately, they are currently only in pre-order release stage (in April 2014).

\midinsert

\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}

\picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg

\caption/f The NVIDIA Jetson TK1 Development Kit \cite[nvidia-k1].

\endinsert

NVIDIA board differs from other boards in its category by a presence of PCI Experess connector. If we decide to use this development board in our radio astronomy digitalisation system, the PCI express  should be used for FPGA connection. A new custom design of FPGA board with Half mini-PCIE direct connector on PCB edge is impractical interface solution due to geometric constrains. Instead of this, the new FPGA module should be designed in standard MLAB fashion and connected to  NVIDIA Jetson TK1 via miniHDMI cable. Similar connection solution can be found in source \cite[fmc-sata].

% doplnit popis pripojeni FPGA desky s HDMI Kabelem.

\sec Other ARM based computation systems

Other embedded ARM based computers, for example ODROID-XU, lack a suitable high speed interface \cite[mlab-arm]. Their highest speed interface is USB 3.0 which has currently unsettled development support and needs commercial software tools for evaluation and testing.

From the summary analysis mentioned above, the Parrallella board seems to be a best candidate for computational board in radioastronomy data acquisition system, as it is optimised for high data flow processing. On one hand, Parrallella does not have much memory to cache the processing data but on the other hand it has wide bandwidth data channels instead. Other boards might provide much more computational power -- 300 GFLOPS in case of NVIDIA K1, but they are optimised for heavy computational tasks on limited amount of data which represents a typical problem in computer graphics. However, in our application we do not need such extreme computation power at data acquisition system level.

As a result we should presumably wait until Parallella becomes widely available. Following that, a new ADCdual interface board should be designed and prepared to be used in new scalable radio astronomy data acquisition system. In the meantime, before suitable computing hardware become accessible, the required applications and algorithms should be optimised using the proposed trial version with FPGA development board on standard PC host computer (having a PCI Express interface to development board).