| 1045 |
jacho |
1 |
D G "__PCM__" 0 7 ""4.106"" |
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2 |
D G "__DEVICE__" 0 7 "887" |
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3 |
D G "__DATE__" 0 7 ""25-3-13"" |
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4 |
D G "__TIME__" 0 7 ""12:15:41"" "Standard Header file for the PIC16F887 device ////////////////" |
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5 |
d G "PIN_A0" 1 20 "40" |
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6 |
d G "PIN_A1" 1 21 "41" |
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7 |
d G "PIN_A2" 1 22 "42" |
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8 |
d G "PIN_A3" 1 23 "43" |
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9 |
d G "PIN_A4" 1 24 "44" |
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10 |
d G "PIN_A5" 1 25 "45" |
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11 |
d G "PIN_A6" 1 26 "46" |
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12 |
d G "PIN_A7" 1 27 "47" |
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13 |
d G "PIN_B0" 1 29 "48" |
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14 |
d G "PIN_B1" 1 30 "49" |
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15 |
d G "PIN_B2" 1 31 "50" |
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16 |
d G "PIN_B3" 1 32 "51" |
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17 |
d G "PIN_B4" 1 33 "52" |
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18 |
d G "PIN_B5" 1 34 "53" |
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19 |
d G "PIN_B6" 1 35 "54" |
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20 |
d G "PIN_B7" 1 36 "55" |
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21 |
d G "PIN_C0" 1 38 "56" |
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22 |
d G "PIN_C1" 1 39 "57" |
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23 |
d G "PIN_C2" 1 40 "58" |
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24 |
d G "PIN_C3" 1 41 "59" |
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25 |
d G "PIN_C4" 1 42 "60" |
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26 |
d G "PIN_C5" 1 43 "61" |
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27 |
d G "PIN_C6" 1 44 "62" |
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28 |
d G "PIN_C7" 1 45 "63" |
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29 |
d G "PIN_D0" 1 47 "64" |
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30 |
d G "PIN_D1" 1 48 "65" |
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31 |
d G "PIN_D2" 1 49 "66" |
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32 |
d G "PIN_D3" 1 50 "67" |
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33 |
d G "PIN_D4" 1 51 "68" |
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34 |
d G "PIN_D5" 1 52 "69" |
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35 |
d G "PIN_D6" 1 53 "70" |
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36 |
d G "PIN_D7" 1 54 "71" |
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37 |
d G "PIN_E0" 1 56 "72" |
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38 |
d G "PIN_E1" 1 57 "73" |
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39 |
d G "PIN_E2" 1 58 "74" |
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40 |
d G "PIN_E3" 1 59 "75" |
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41 |
d G "FALSE" 1 62 "0" |
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42 |
d G "TRUE" 1 63 "1" |
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43 |
d G "BYTE" 1 65 "int8" |
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44 |
d G "BOOLEAN" 1 66 "int1" |
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45 |
d G "getc" 1 68 "getch" |
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46 |
d G "fgetc" 1 69 "getch" |
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47 |
d G "getchar" 1 70 "getch" |
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48 |
d G "putc" 1 71 "putchar" |
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49 |
d G "fputc" 1 72 "putchar" |
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50 |
d G "fgets" 1 73 "gets" |
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51 |
d G "fputs" 1 74 "puts" |
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52 |
d G "WDT_FROM_SLEEP" 1 79 "3" |
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53 |
d G "WDT_TIMEOUT" 1 80 "11" |
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54 |
d G "MCLR_FROM_SLEEP" 1 81 "19" |
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55 |
d G "MCLR_FROM_RUN" 1 82 "27" |
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56 |
d G "NORMAL_POWER_UP" 1 83 "25" |
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57 |
d G "BROWNOUT_RESTART" 1 84 "26" |
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58 |
d G "T0_INTERNAL" 1 91 "0" |
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59 |
d G "T0_EXT_L_TO_H" 1 92 "32" |
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60 |
d G "T0_EXT_H_TO_L" 1 93 "48" |
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61 |
d G "T0_DIV_1" 1 95 "8" |
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62 |
d G "T0_DIV_2" 1 96 "0" |
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63 |
d G "T0_DIV_4" 1 97 "1" |
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64 |
d G "T0_DIV_8" 1 98 "2" |
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65 |
d G "T0_DIV_16" 1 99 "3" |
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66 |
d G "T0_DIV_32" 1 100 "4" |
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67 |
d G "T0_DIV_64" 1 101 "5" |
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68 |
d G "T0_DIV_128" 1 102 "6" |
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69 |
d G "T0_DIV_256" 1 103 "7" |
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70 |
d G "T0_8_BIT" 1 106 "0" |
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71 |
d G "RTCC_INTERNAL" 1 108 "0" "The following are provided for compatibility" |
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72 |
d G "RTCC_EXT_L_TO_H" 1 109 "32" "with older compiler versions" |
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73 |
d G "RTCC_EXT_H_TO_L" 1 110 "48" |
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74 |
d G "RTCC_DIV_1" 1 111 "8" |
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75 |
d G "RTCC_DIV_2" 1 112 "0" |
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76 |
d G "RTCC_DIV_4" 1 113 "1" |
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77 |
d G "RTCC_DIV_8" 1 114 "2" |
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78 |
d G "RTCC_DIV_16" 1 115 "3" |
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79 |
d G "RTCC_DIV_32" 1 116 "4" |
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80 |
d G "RTCC_DIV_64" 1 117 "5" |
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81 |
d G "RTCC_DIV_128" 1 118 "6" |
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82 |
d G "RTCC_DIV_256" 1 119 "7" |
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83 |
d G "RTCC_8_BIT" 1 120 "0" |
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84 |
d G "WDT_18MS" 1 132 "8" |
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85 |
d G "WDT_36MS" 1 133 "9" |
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86 |
d G "WDT_72MS" 1 134 "10" |
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87 |
d G "WDT_144MS" 1 135 "11" |
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88 |
d G "WDT_288MS" 1 136 "12" |
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89 |
d G "WDT_576MS" 1 137 "13" |
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90 |
d G "WDT_1152MS" 1 138 "14" |
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91 |
d G "WDT_2304MS" 1 139 "15" |
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92 |
d G "WDT_ON" 1 143 "0x4100" |
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93 |
d G "WDT_OFF" 1 144 "0" |
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94 |
d G "WDT_DIV_16" 1 145 "0x100" |
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95 |
d G "WDT_DIV_8" 1 146 "0x300" |
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96 |
d G "WDT_DIV_4" 1 147 "0x500" |
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97 |
d G "WDT_DIV_2" 1 148 "0x700" |
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98 |
d G "WDT_TIMES_1" 1 149 "0x900" "Default" |
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99 |
d G "WDT_TIMES_2" 1 150 "0xB00" |
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100 |
d G "WDT_TIMES_4" 1 151 "0xD00" |
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101 |
d G "WDT_TIMES_8" 1 152 "0xF00" |
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102 |
d G "WDT_TIMES_16" 1 153 "0x1100" |
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103 |
d G "WDT_TIMES_32" 1 154 "0x1300" |
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104 |
d G "WDT_TIMES_64" 1 155 "0x1500" |
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105 |
d G "WDT_TIMES_128" 1 156 "0x1700" |
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106 |
d G "T1_DISABLED" 1 162 "0" |
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107 |
d G "T1_INTERNAL" 1 163 "5" |
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108 |
d G "T1_EXTERNAL" 1 164 "7" |
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109 |
d G "T1_EXTERNAL_SYNC" 1 165 "3" |
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110 |
d G "T1_CLK_OUT" 1 167 "8" |
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111 |
d G "T1_DIV_BY_1" 1 169 "0" |
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112 |
d G "T1_DIV_BY_2" 1 170 "0x10" |
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113 |
d G "T1_DIV_BY_4" 1 171 "0x20" |
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114 |
d G "T1_DIV_BY_8" 1 172 "0x30" |
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115 |
d G "T1_GATE" 1 174 "0x40" |
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116 |
d G "T1_GATE_INVERTED" 1 175 "0xC0" |
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117 |
d G "T2_DISABLED" 1 180 "0" |
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118 |
d G "T2_DIV_BY_1" 1 181 "4" |
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119 |
d G "T2_DIV_BY_4" 1 182 "5" |
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120 |
d G "T2_DIV_BY_16" 1 183 "6" |
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121 |
d G "CCP_OFF" 1 189 "0" |
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122 |
d G "CCP_CAPTURE_FE" 1 190 "4" |
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123 |
d G "CCP_CAPTURE_RE" 1 191 "5" |
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124 |
d G "CCP_CAPTURE_DIV_4" 1 192 "6" |
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125 |
d G "CCP_CAPTURE_DIV_16" 1 193 "7" |
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126 |
d G "CCP_COMPARE_SET_ON_MATCH" 1 194 "8" |
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127 |
d G "CCP_COMPARE_CLR_ON_MATCH" 1 195 "9" |
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128 |
d G "CCP_COMPARE_INT" 1 196 "0xA" |
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129 |
d G "CCP_COMPARE_RESET_TIMER" 1 197 "0xB" |
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130 |
d G "CCP_PWM" 1 198 "0xC" |
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131 |
d G "CCP_PWM_PLUS_1" 1 199 "0x1c" |
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132 |
d G "CCP_PWM_PLUS_2" 1 200 "0x2c" |
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133 |
d G "CCP_PWM_PLUS_3" 1 201 "0x3c" |
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134 |
d G "CCP_PWM_H_H" 1 206 "0x0c" |
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135 |
d G "CCP_PWM_H_L" 1 207 "0x0d" |
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136 |
d G "CCP_PWM_L_H" 1 208 "0x0e" |
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137 |
d G "CCP_PWM_L_L" 1 209 "0x0f" |
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138 |
d G "CCP_PWM_FULL_BRIDGE" 1 211 "0x40" |
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139 |
d G "CCP_PWM_FULL_BRIDGE_REV" 1 212 "0xC0" |
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140 |
d G "CCP_PWM_HALF_BRIDGE" 1 213 "0x80" |
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141 |
d G "CCP_SHUTDOWN_ON_COMP1" 1 215 "0x100000" |
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142 |
d G "CCP_SHUTDOWN_ON_COMP2" 1 216 "0x200000" |
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143 |
d G "CCP_SHUTDOWN_ON_COMP" 1 217 "0x300000" |
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144 |
d G "CCP_SHUTDOWN_ON_INT0" 1 218 "0x400000" |
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145 |
d G "CCP_SHUTDOWN_ON_COMP1_INT0" 1 219 "0x500000" |
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146 |
d G "CCP_SHUTDOWN_ON_COMP2_INT0" 1 220 "0x600000" |
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147 |
d G "CCP_SHUTDOWN_ON_COMP_INT0" 1 221 "0x700000" |
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148 |
d G "CCP_SHUTDOWN_AC_L" 1 223 "0x000000" |
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149 |
d G "CCP_SHUTDOWN_AC_H" 1 224 "0x040000" |
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150 |
d G "CCP_SHUTDOWN_AC_F" 1 225 "0x080000" |
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151 |
d G "CCP_SHUTDOWN_BD_L" 1 227 "0x000000" |
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152 |
d G "CCP_SHUTDOWN_BD_H" 1 228 "0x010000" |
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153 |
d G "CCP_SHUTDOWN_BD_F" 1 229 "0x020000" |
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154 |
d G "CCP_SHUTDOWN_RESTART" 1 231 "0x80000000" |
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155 |
d G "CCP_PULSE_STEERING_A" 1 233 "0x01000000" |
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156 |
d G "CCP_PULSE_STEERING_B" 1 234 "0x02000000" |
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157 |
d G "CCP_PULSE_STEERING_C" 1 235 "0x04000000" |
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158 |
d G "CCP_PULSE_STEERING_D" 1 236 "0x08000000" |
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159 |
d G "CCP_PULSE_STEERING_SYNC" 1 237 "0x10000000" |
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160 |
d G "SPI_MASTER" 1 245 "0x20" |
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161 |
d G "SPI_SLAVE" 1 246 "0x24" |
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162 |
d G "SPI_L_TO_H" 1 247 "0" |
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163 |
d G "SPI_H_TO_L" 1 248 "0x10" |
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164 |
d G "SPI_CLK_DIV_4" 1 249 "0" |
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165 |
d G "SPI_CLK_DIV_16" 1 250 "1" |
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166 |
d G "SPI_CLK_DIV_64" 1 251 "2" |
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167 |
d G "SPI_CLK_T2" 1 252 "3" |
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168 |
d G "SPI_SS_DISABLED" 1 253 "1" |
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169 |
d G "SPI_SAMPLE_AT_END" 1 255 "0x8000" |
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170 |
d G "SPI_XMIT_L_TO_H" 1 256 "0x4000" |
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171 |
d G "UART_ADDRESS" 1 262 "2" |
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172 |
d G "UART_DATA" 1 263 "4" |
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173 |
d G "UART_AUTODETECT" 1 264 "8" |
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174 |
d G "UART_AUTODETECT_NOWAIT" 1 265 "9" |
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175 |
d G "UART_WAKEUP_ON_RDA" 1 266 "10" |
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176 |
d G "UART_SEND_BREAK" 1 267 "13" |
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177 |
d G "NC_NC_NC_NC" 1 273 "0x00" |
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178 |
d G "NC_NC" 1 274 "0x00" |
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179 |
d G "CP1_A0_A3" 1 277 "0x00090080" |
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180 |
d G "CP1_A1_A3" 1 278 "0x000A0081" |
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181 |
d G "CP1_B3_A3" 1 279 "0x00880082" |
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182 |
d G "CP1_B1_A3" 1 280 "0x00280083" |
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183 |
d G "CP1_A0_VREF" 1 281 "0x00010084" |
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184 |
d G "CP1_A1_VREF" 1 282 "0x00020085" |
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185 |
d G "CP1_B3_VREF" 1 283 "0x00800086" |
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186 |
d G "CP1_B1_VREF" 1 284 "0x00200087" |
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187 |
d G "CP1_OUT_ON_A4" 1 286 "0x00000020" |
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188 |
d G "CP1_INVERT" 1 287 "0x00000010" |
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189 |
d G "CP1_ABSOLUTE_VREF" 1 288 "0x20000000" |
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190 |
d G "CP2_A0_A2" 1 291 "0x00058000" |
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191 |
d G "CP2_A1_A2" 1 292 "0x00068100" |
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192 |
d G "CP2_B3_A2" 1 293 "0x00848200" |
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193 |
d G "CP2_B1_A2" 1 294 "0x00248300" |
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194 |
d G "CP2_A0_VREF" 1 295 "0x00018400" |
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195 |
d G "CP2_A1_VREF" 1 296 "0x00028500" |
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196 |
d G "CP2_B3_VREF" 1 297 "0x00808600" |
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197 |
d G "CP2_B1_VREF" 1 298 "0x00208700" |
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198 |
d G "CP2_OUT_ON_A5" 1 300 "0x00002000" |
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199 |
d G "CP2_INVERT" 1 301 "0x00001000" |
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200 |
d G "CP2_ABSOLUTE_VREF" 1 302 "0x10000000" |
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201 |
d G "CP2_T1_SYNC" 1 305 "0x01000000" |
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202 |
d G "CP2_T1_GATE" 1 306 "0x02000000" |
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203 |
d G "VREF_LOW" 1 315 "0xa0" |
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204 |
d G "VREF_HIGH" 1 316 "0x80" |
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205 |
d G "OSC_31KHZ" 1 322 "1" |
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206 |
d G "OSC_125KHZ" 1 323 "0x11" |
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207 |
d G "OSC_250KHZ" 1 324 "0x21" |
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208 |
d G "OSC_500KHZ" 1 325 "0x31" |
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209 |
d G "OSC_1MHZ" 1 326 "0x41" |
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210 |
d G "OSC_2MHZ" 1 327 "0x51" |
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211 |
d G "OSC_4MHZ" 1 328 "0x61" |
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212 |
d G "OSC_8MHZ" 1 329 "0x71" |
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213 |
d G "OSC_INTRC" 1 330 "1" |
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214 |
d G "OSC_NORMAL" 1 331 "0" |
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215 |
d G "OSC_STATE_STABLE" 1 333 "4" |
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216 |
d G "OSC_31KHZ_STABLE" 1 334 "2" |
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217 |
d G "ADC_OFF" 1 342 "0" "ADC Off" |
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218 |
d G "ADC_CLOCK_DIV_2" 1 343 "0x100" |
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219 |
d G "ADC_CLOCK_DIV_8" 1 344 "0x40" |
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220 |
d G "ADC_CLOCK_DIV_32" 1 345 "0x80" |
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221 |
d G "ADC_CLOCK_INTERNAL" 1 346 "0xc0" "Internal 2-6us" |
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222 |
d G "sAN0" 1 350 "1" "| A0" |
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223 |
d G "sAN1" 1 351 "2" "| A1" |
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224 |
d G "sAN2" 1 352 "4" "| A2" |
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225 |
d G "sAN3" 1 353 "8" "| A3" |
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226 |
d G "sAN4" 1 354 "16" "| A5" |
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227 |
d G "sAN5" 1 355 "32" "| E0" |
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228 |
d G "sAN6" 1 356 "64" "| E1" |
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229 |
d G "sAN7" 1 357 "128" "| E2" |
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230 |
d G "sAN8" 1 358 "0x10000" "| B2" |
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231 |
d G "sAN9" 1 359 "0x20000" "| B3" |
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232 |
d G "sAN10" 1 360 "0x40000" "| B1" |
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233 |
d G "sAN11" 1 361 "0x80000" "| B4" |
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234 |
d G "sAN12" 1 362 "0x100000" "| B0" |
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235 |
d G "sAN13" 1 363 "0x200000" "| B5" |
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236 |
d G "NO_ANALOGS" 1 364 "0" "None" |
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237 |
d G "ALL_ANALOG" 1 365 "0x1F00FF" "A0 A1 A2 A3 A5 E0 E1 E2 B0 B1 B2 B3 B4 B5" |
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238 |
d G "VSS_VDD" 1 368 "0x0000" "| Range 0-Vdd" |
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239 |
d G "VSS_VREF" 1 369 "0x1000" "| Range 0-Vref" |
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240 |
d G "VREF_VREF" 1 370 "0x3000" "| Range Vref-Vref" |
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241 |
d G "VREF_VDD" 1 371 "0x2000" "| Range Vref-Vdd" |
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242 |
d G "ADC_START_AND_READ" 1 375 "7" "This is the default if nothing is specified" |
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243 |
d G "ADC_START_ONLY" 1 376 "1" |
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244 |
d G "ADC_READ_ONLY" 1 377 "6" |
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245 |
d G "L_TO_H" 1 389 "0x40" |
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246 |
d G "H_TO_L" 1 390 "0" |
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247 |
d G "GLOBAL" 1 392 "0x0BC0" |
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248 |
d G "INT_RTCC" 1 393 "0x000B20" |
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249 |
d G "INT_RB" 1 394 "0x01FF0B08" |
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250 |
d G "INT_EXT_L2H" 1 395 "0x50000B10" |
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251 |
d G "INT_EXT_H2L" 1 396 "0x60000B10" |
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252 |
d G "INT_EXT" 1 397 "0x000B10" |
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253 |
d G "INT_AD" 1 398 "0x008C40" |
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254 |
d G "INT_TBE" 1 399 "0x008C10" |
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255 |
d G "INT_RDA" 1 400 "0x008C20" |
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256 |
d G "INT_TIMER1" 1 401 "0x008C01" |
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257 |
d G "INT_TIMER2" 1 402 "0x008C02" |
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258 |
d G "INT_CCP1" 1 403 "0x008C04" |
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259 |
d G "INT_CCP2" 1 404 "0x008D01" |
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260 |
d G "INT_SSP" 1 405 "0x008C08" |
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261 |
d G "INT_BUSCOL" 1 406 "0x008D08" |
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262 |
d G "INT_EEPROM" 1 407 "0x008D10" |
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263 |
d G "INT_TIMER0" 1 408 "0x000B20" |
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264 |
d G "INT_OSC_FAIL" 1 409 "0x008D80" |
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265 |
d G "INT_COMP" 1 410 "0x008D20" |
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266 |
d G "INT_COMP2" 1 411 "0x008D40" |
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267 |
d G "INT_ULPWU" 1 412 "0x008D04" |
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268 |
d G "INT_RB0" 1 413 "0x0010B08" |
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269 |
d G "INT_RB1" 1 414 "0x0020B08" |
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270 |
d G "INT_RB2" 1 415 "0x0040B08" |
|
|
271 |
d G "INT_RB3" 1 416 "0x0080B08" |
|
|
272 |
d G "INT_RB4" 1 417 "0x0100B08" |
|
|
273 |
d G "INT_RB5" 1 418 "0x0200B08" |
|
|
274 |
d G "INT_RB6" 1 419 "0x0400B08" |
|
|
275 |
d G "INT_RB7" 1 420 "0x0800B08" |
|
|
276 |
F G "main" 0 3 "void()" |
|
|
277 |
F B "reset_cpu" 0 0 |
|
|
278 |
F B "abs" 1 0 |
|
|
279 |
F B "sleep_ulpwu" 1 0 |
|
|
280 |
F B "sleep" 0 0 |
|
|
281 |
F B "delay_cycles" 1 0 |
|
|
282 |
F B "read_bank" 2 0 |
|
|
283 |
F B "write_bank" 3 0 |
|
|
284 |
F B "shift_left" 2 2 |
|
|
285 |
F B "shift_right" 2 2 |
|
|
286 |
F B "rotate_left" 2 0 |
|
|
287 |
F B "rotate_right" 2 0 |
|
|
288 |
F B "_mul" 2 0 |
|
|
289 |
F B "memset" 3 0 |
|
|
290 |
F B "isamoung" 2 0 |
|
|
291 |
F B "isamong" 2 0 |
|
|
292 |
F B "bit_set" 2 0 |
|
|
293 |
F B "bit_clear" 2 0 |
|
|
294 |
F B "bit_test" 2 0 |
|
|
295 |
F B "toupper" 1 0 |
|
|
296 |
F B "tolower" 1 0 |
|
|
297 |
F B "swap" 1 0 |
|
|
298 |
F B "printf" 1 255 |
|
|
299 |
F B "fprintf" 1 255 |
|
|
300 |
F B "sprintf" 1 255 |
|
|
301 |
F B "make8" 2 0 |
|
|
302 |
F B "make16" 2 0 |
|
|
303 |
F B "make32" 1 255 |
|
|
304 |
F B "label_address" 1 1 |
|
|
305 |
F B "goto_address" 1 0 |
|
|
306 |
F B "_va_arg" 1 0 |
|
|
307 |
F B "offsetofbit" 2 2 |
|
|
308 |
F B "enable_interrupts" 1 0 |
|
|
309 |
F B "disable_interrupts" 1 0 |
|
|
310 |
F B "interrupt_active" 1 0 |
|
|
311 |
F B "clear_interrupt" 1 0 |
|
|
312 |
F B "jump_to_isr" 1 0 |
|
|
313 |
F B "ext_int_edge" 1 2 |
|
|
314 |
F B "read_eeprom" 1 0 |
|
|
315 |
F B "write_eeprom" 2 0 |
|
|
316 |
F B "read_program_eeprom" 1 0 |
|
|
317 |
F B "write_program_eeprom" 2 0 |
|
|
318 |
F B "write_program_memory" 4 0 |
|
|
319 |
F B "write_program_memory8" 4 0 |
|
|
320 |
F B "read_program_memory" 4 0 |
|
|
321 |
F B "read_program_memory8" 4 0 |
|
|
322 |
F B "erase_program_eeprom" 1 0 |
|
|
323 |
F B "strcpy" 2 0 |
|
|
324 |
F B "memcpy" 3 0 |
|
|
325 |
F B "strstr100" 2 0 |
|
|
326 |
F B "output_high" 1 0 |
|
|
327 |
F B "output_low" 1 0 |
|
|
328 |
F B "input" 1 0 |
|
|
329 |
F B "input_state" 1 0 |
|
|
330 |
F B "output_float" 1 0 |
|
|
331 |
F B "output_drive" 1 0 |
|
|
332 |
F B "output_bit" 1 1 |
|
|
333 |
F B "output_toggle" 1 0 |
|
|
334 |
F B "output_a" 1 0 |
|
|
335 |
F B "output_b" 1 0 |
|
|
336 |
F B "output_c" 1 0 |
|
|
337 |
F B "output_d" 1 0 |
|
|
338 |
F B "output_e" 1 0 |
|
|
339 |
F B "input_a" 0 0 |
|
|
340 |
F B "input_b" 0 0 |
|
|
341 |
F B "input_c" 0 0 |
|
|
342 |
F B "input_d" 0 0 |
|
|
343 |
F B "input_e" 0 0 |
|
|
344 |
F B "set_tris_a" 1 0 |
|
|
345 |
F B "set_tris_b" 1 0 |
|
|
346 |
F B "set_tris_c" 1 0 |
|
|
347 |
F B "set_tris_d" 1 0 |
|
|
348 |
F B "set_tris_e" 1 0 |
|
|
349 |
F B "get_tris_a" 0 0 |
|
|
350 |
F B "get_tris_b" 0 0 |
|
|
351 |
F B "get_tris_c" 0 0 |
|
|
352 |
F B "get_tris_d" 0 0 |
|
|
353 |
F B "get_tris_e" 0 0 |
|
|
354 |
F B "input_change_a" 0 0 |
|
|
355 |
F B "input_change_b" 0 0 |
|
|
356 |
F B "input_change_c" 0 0 |
|
|
357 |
F B "input_change_d" 0 0 |
|
|
358 |
F B "input_change_e" 0 0 |
|
|
359 |
F B "port_b_pullups" 1 0 |
|
|
360 |
F B "setup_counters" 2 0 |
|
|
361 |
F B "setup_wdt" 1 0 |
|
|
362 |
F B "restart_cause" 0 0 |
|
|
363 |
F B "restart_wdt" 0 0 |
|
|
364 |
F B "get_rtcc" 0 0 |
|
|
365 |
F B "set_rtcc" 1 0 |
|
|
366 |
F B "get_timer0" 0 0 |
|
|
367 |
F B "set_timer0" 1 0 |
|
|
368 |
F B "setup_comparator" 1 0 |
|
|
369 |
F B "setup_port_a" 1 0 |
|
|
370 |
F B "setup_adc_ports" 1 0 |
|
|
371 |
F B "setup_adc" 1 0 |
|
|
372 |
F B "set_adc_channel" 1 0 |
|
|
373 |
F B "read_adc" 0 1 |
|
|
374 |
F B "adc_done" 0 0 |
|
|
375 |
F B "setup_timer_0" 1 0 |
|
|
376 |
F B "setup_vref" 1 0 |
|
|
377 |
F B "setup_timer_1" 1 0 |
|
|
378 |
F B "get_timer1" 0 0 |
|
|
379 |
F B "set_timer1" 1 0 |
|
|
380 |
F B "setup_timer_2" 3 0 |
|
|
381 |
F B "get_timer2" 0 0 |
|
|
382 |
F B "set_timer2" 1 0 |
|
|
383 |
F B "setup_ccp1" 1 2 |
|
|
384 |
F B "set_pwm1_duty" 1 0 |
|
|
385 |
F B "setup_ccp2" 1 0 |
|
|
386 |
F B "set_pwm2_duty" 1 0 |
|
|
387 |
F B "setup_oscillator" 1 2 |
|
|
388 |
F B "setup_spi" 1 0 |
|
|
389 |
F B "spi_read" 0 1 |
|
|
390 |
F B "spi_write" 1 0 |
|
|
391 |
F B "spi_data_is_in" 0 0 |
|
|
392 |
F B "setup_spi2" 1 0 |
|
|
393 |
F B "spi_read2" 0 1 |
|
|
394 |
F B "spi_write2" 1 0 |
|
|
395 |
F B "spi_data_is_in2" 0 0 |
|
|
396 |
F B "brownout_enable" 1 0 |