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2 kaklik 1 
#nolist
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//
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// Komplete definition of all Special Feature Registers for CCS C compiler
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//
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//    PIC16F87
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//    PIC16F88
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//
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// (c)miho 2005
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//
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// History:
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//
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// 1.00 First Version, not verified yet
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// SFR Registers in Memory Bank 0
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//
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#byte INDF           = 0x00
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#byte TMR0           = 0x01
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#byte PCL            = 0x02
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#byte STATUS         = 0x03
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   #bit IRP          = STATUS.7
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   #bit RP1          = STATUS.6
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   #bit RP0          = STATUS.5
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   #bit TO           = STATUS.4
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   #bit PD           = STATUS.3
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   #bit Z            = STATUS.2
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   #bit DC           = STATUS.1
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   #bit C            = STATUS.0
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#byte FSR            = 0x04
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#byte PORTA          = 0x05
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#byte PORTB          = 0x06
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#byte PCLATH         = 0x0A
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#byte INTCON         = 0x0B
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   #bit GIE          = INTCON.7
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   #bit PEIE         = INTCON.6
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   #bit TMR0IE       = INTCON.5
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   #bit INT0IE       = INTCON.4
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   #bit RBIE         = INTCON.3
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   #bit TMR0IF       = INTCON.2
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   #bit INT0IF       = INTCON.1
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   #bit RBIF         = INTCON.0
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#byte PIR1           = 0x0C
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   #bit ADIF         = PIR1.6
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   #bit RCIF         = PIR1.5
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   #bit TXIF         = PIR1.4
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   #bit SSPIF        = PIR1.3
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   #bit CCP1IF       = PIR1.2
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   #bit TMR2IF       = PIR1.1
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   #bit TMR1IF       = PIR1.0
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#byte PIR2           = 0x0D
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   #bit OSFIF        = PIR2.7
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   #bit CMIF         = PIR2.6
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   #bit EEIF         = PIR2.4
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#byte TMR1L          = 0x0E
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#byte TMR1H          = 0x0F
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#byte T1CON          = 0x10
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   #bit T1RUN        = T1CON.6
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   #bit T1CKPS1      = T1CON.5
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   #bit T1CKPS0      = T1CON.4
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   #bit T1OSCEN      = T1CON.3
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   #bit T1SYNC       = T1CON.2
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   #bit TMR1CS       = T1CON.1
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   #bit TMR1ON       = T1CON.0
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#byte TMR2           = 0x11
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#byte T2CON          = 0x12
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   #bit TOUTPS3      = T2CON.6
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   #bit TOUTPS2      = T2CON.5
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   #bit TOUTPS1      = T2CON.4
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   #bit TOUTPS0      = T2CON.3
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   #bit TMR2ON       = T2CON.2
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   #bit T2CKPS1      = T2CON.1
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   #bit T2CKPS0      = T2CON.0
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#byte SSPBUF         = 0x13
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#byte SSPCON1        = 0x14
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   #bit WCOL         = SSPCON1.7
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   #bit SSPOV        = SSPCON1.6
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   #bit SSPEN        = SSPCON1.5
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   #bit CKP          = SSPCON1.4
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   #bit SSPM3        = SSPCON1.3
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   #bit SSPM2        = SSPCON1.2
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   #bit SSPM1        = SSPCON1.1
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   #bit SSPM0        = SSPCON1.0
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#byte CCPR1L         = 0x15
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#byte CCPR1H         = 0x16
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#byte CCP1CON        = 0x17
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   #bit CCP1X        = CCP1CON.5
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   #bit CCP1Y        = CCP1CON.4
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   #bit CCP1M3       = CCP1CON.3
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   #bit CCP1M2       = CCP1CON.2
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   #bit CCP1M1       = CCP1CON.1
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   #bit CCP1M0       = CCP1CON.0
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#byte RCSTA          = 0x18
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   #bit SPEN         = RCSTA.7
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   #bit RX9          = RCSTA.6
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   #bit SREN         = RCSTA.5
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   #bit CREN         = RCSTA.4
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   #bit ADDEN        = RCSTA.3
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   #bit FERR         = RCSTA.2
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   #bit OERR         = RCSTA.1
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   #bit RX9D         = RCSTA.0
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#byte TXREG          = 0x19
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#byte RCREG          = 0x1A
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#byte ADRESH         = 0x1E         // F88 only
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#byte ADCON0         = 0x1F         // F88 only
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   #bit ADCS1        = ADCON0.7
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   #bit ADCS0        = ADCON0.6
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   #bit CHS2         = ADCON0.5
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   #bit CHS1         = ADCON0.4
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   #bit CHS0         = ADCON0.3
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   #bit GO           = ADCON0.2
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   #bit ADON         = ADCON0.0
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// SFR Registers in Memory Bank 1
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//
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#byte INDF_1         = 0x80         // miror
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#byte OPTION         = 0x81
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   #bit RBPU         = OPTION.7
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   #bit INTEDG       = OPTION.6
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   #bit T0CS         = OPTION.5
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   #bit T0SE         = OPTION.4
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   #bit PSA          = OPTION.3
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   #bit PS2          = OPTION.2
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   #bit PS1          = OPTION.1
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   #bit PS0          = OPTION.0
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#byte PCL            = 0x82
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#byte STATUS_1       = 0x83         // mirror
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   #bit IRP_1        = STATUS_1.7
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   #bit RP1_1        = STATUS_1.6
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   #bit RP0_1        = STATUS_1.5
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   #bit TO_1         = STATUS_1.4
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   #bit PD_1         = STATUS_1.3
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   #bit Z_1          = STATUS_1.2
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   #bit DC_1         = STATUS_1.1
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   #bit C_1          = STATUS_1.0
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#byte FSR            = 0x84
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#byte TRISA          = 0x85
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#byte TRISB          = 0x86
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#byte PCLATH_1       = 0x8A         // mirror
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#byte INTCON_1       = 0x8B         // mirror
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   #bit GIE_1        = INTCON_1.7
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   #bit PEIE_1       = INTCON_1.6
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   #bit TMR0IE_1     = INTCON_1.5
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   #bit INT0IE_1     = INTCON_1.4
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   #bit RBIE_1       = INTCON_1.3
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   #bit TMR0IF_1     = INTCON_1.2
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   #bit INT0IF_1     = INTCON_1.1
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   #bit RBIF_1       = INTCON_1.0
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#byte PIE1           = 0x8C
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   #bit ADIE         = PIE1.6
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   #bit RCIE         = PIE1.5
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   #bit TXIE         = PIE1.4
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   #bit SSPIE        = PIE1.3
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   #bit CCP1IE       = PIE1.2
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   #bit TMR2IE       = PIE1.1
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   #bit TMR1IE       = PIE1.0
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#byte PIE2           = 0x8D
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   #bit OSFIE        = PIE2.7
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   #bit CMIE         = PIE2.6
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   #bit EEIE         = PIE2.4
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#byte PCON           = 0x8E
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   #bit POR          = PCON.1
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   #bit BOR          = PCON.0
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#byte OSCCON         = 0x8F
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   #bit IRCF2        = OSCCON.6
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   #bit IRCF1        = OSCCON.5
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   #bit IRCF0        = OSCCON.4
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   #bit OSTS         = OSCCON.3
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   #bit IOFS         = OSCCON.2
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   #bit SCS1         = OSCCON.1
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   #bit SCS0         = OSCCON.0
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#byte OSCTUNE        = 0x90
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   #bit TUN5         = OSCTUNE.5
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   #bit TUN4         = OSCTUNE.4
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   #bit TUN3         = OSCTUNE.3
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   #bit TUN2         = OSCTUNE.2
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   #bit TUN1         = OSCTUNE.1
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   #bit TUN0         = OSCTUNE.0
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#byte PR2            = 0x92
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#byte SSPADD         = 0x93
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#byte SSPSTAT        = 0x94
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   #bit SMP          = SSPSTAT.7
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   #bit CKE          = SSPSTAT.6
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   #bit DA           = SSPSTAT.5
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   #bit P            = SSPSTAT.4
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   #bit S            = SSPSTAT.3
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   #bit RW           = SSPSTAT.2
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   #bit UA           = SSPSTAT.1
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   #bit BF           = SSPSTAT.0
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#byte TXSTA          = 0x98
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   #bit CSRC         = TXSTA.7
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   #bit TX9          = TXSTA.6
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   #bit TXEN         = TXSTA.5
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   #bit SYNC         = TXSTA.4
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   #bit BRGH         = TXSTA.2
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   #bit TRMT         = TXSTA.1
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   #bit TX9D         = TXSTA.0
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#byte SPBRG          = 0x99
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#byte ANSEL          = 0x9B         // F88 only
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   #bit ANS6         = ANSEL.6
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   #bit ANS5         = ANSEL.5
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   #bit ANS4         = ANSEL.4
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   #bit ANS3         = ANSEL.3
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   #bit ANS2         = ANSEL.2
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   #bit ANS1         = ANSEL.1
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   #bit ANS0         = ANSEL.0
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#byte CMCON          = 0x9C
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   #bit C2OUT        = CMCON.7
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   #bit C1OUT        = CMCON.6
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   #bit C2INV        = CMCON.5
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   #bit C1INV        = CMCON.4
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   #bit CIS          = CMCON.3
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   #bit CM2          = CMCON.2
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   #bit CM1          = CMCON.1
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   #bit CM0          = CMCON.0
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#byte CVRCON         = 0x9D
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   #bit CVREN        = CVRCON.7
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   #bit CVROE        = CVRCON.6
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   #bit CVRR         = CVRCON.5
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   #bit CVR3         = CVRCON.3
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   #bit CVR2         = CVRCON.2
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   #bit CVR1         = CVRCON.1
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   #bit CVR0         = CVRCON.0
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#byte ADRESL         = 0x9E         // F88 only
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#byte ADCON1         = 0x9F         // F88 only
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   #bit ADFM         = ADCON1.7
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   #bit ADCS2        = ADCON1.6
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   #bit VCFG1        = ADCON1.5
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   #bit VCFG0        = ADCON1.4
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// SFR Registers in Memory Bank 2
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//
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#byte INDF_2         = 0x100        // mirror
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#byte TMR0_2         = 0x101        // mirror
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#byte PCL_2          = 0x102        // mirror
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#byte STATUS_2       = 0x103        // mirror
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   #bit IRP_2        = STATUS_2.7
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   #bit RP1_2        = STATUS_2.6
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   #bit RP0_2        = STATUS_2.5
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   #bit TO_2         = STATUS_2.4
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   #bit PD_2         = STATUS_2.3
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   #bit Z_2          = STATUS_2.2
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   #bit DC_2         = STATUS_2.1
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   #bit C_2          = STATUS_2.0
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#byte FSR_2          = 0x104        // mirror
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#byte WDTCON         = 0x105
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   #bit WDTPS3       = WDTCON.4
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   #bit WDTPS2       = WDTCON.3
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   #bit WDTPS1       = WDTCON.2
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   #bit WDTPS0       = WDTCON.1
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   #bit SWDTEN       = WDTCON.0
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#byte PORTB_2        = 0x106        // mirror
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#byte PCLATH_2       = 0x10A        // mirror
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#byte INTCON_2       = 0x10B        // mirror
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   #bit GIE_2        = INTCON_2.7
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   #bit PEIE_2       = INTCON_2.6
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   #bit TMR0IE_2     = INTCON_2.5
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   #bit INT0IE_2     = INTCON_2.4
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   #bit RBIE_2       = INTCON_2.3
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   #bit TMR0IF_2     = INTCON_2.2
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   #bit INT0IF_2     = INTCON_2.1
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   #bit RBIF_2       = INTCON_2.0
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#byte EEDATA         = 0x10C
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#byte EEADR          = 0x10D
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#byte EEDATH         = 0x10E
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#byte EEADRH         = 0x10F
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// SFR Registers in Memory Bank 3
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//
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#byte INDF_3         = 0x180        // mirror
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#byte OPTION_3       = 0x181        // mirror
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   #bit RBPU_3       = OPTION_3.7
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   #bit INTEDG_3     = OPTION_3.6
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   #bit T0CS_3       = OPTION_3.5
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   #bit T0SE_3       = OPTION_3.4
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   #bit PSA_3        = OPTION_3.3
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   #bit PS2_3        = OPTION_3.2
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   #bit PS1_3        = OPTION_3.1
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   #bit PS0_3        = OPTION_3.0
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#byte PCL_3          = 0x182        // mirror
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#byte STATUS_3       = 0x183        // mirror
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   #bit IRP_3        = STATUS_3.7
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   #bit RP1_3        = STATUS_3.6
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   #bit RP0_3        = STATUS_3.5
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   #bit TO_3         = STATUS_3.4
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   #bit PD_3         = STATUS_3.3
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   #bit Z_3          = STATUS_3.2
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   #bit DC_3         = STATUS_3.1
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   #bit C_3          = STATUS_3.0
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#byte FSR_3          = 0x184        // mirror
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#byte TRISB_3        = 0x186        // mirror
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#byte PLATH_3        = 0x18A        // mirror
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#byte INTCON_3       = 0x18B        // mirror
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   #bit GIE_3        = INTCON_3.7
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   #bit PEIE_3       = INTCON_3.6
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   #bit TMR0IE_3     = INTCON_3.5
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   #bit INT0IE_3     = INTCON_3.4
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   #bit RBIE_3       = INTCON_3.3
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   #bit TMR0IF_3     = INTCON_3.2
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   #bit INT0IF_3     = INTCON_3.1
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   #bit RBIF_3       = INTCON_3.0
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#byte EECON1         = 0x18C
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   #bit EEPGD        = EECON1.7
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   #bit FREE         = EECON1.4
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   #bit WRERR        = EECON1.3
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   #bit WREN         = EECON1.2
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   #bit WR           = EECON1.1
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   #bit RD           = EECON1.0
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#byte EECON2         = 0x18D
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#list