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6 kaklik 1
PADS Router  2005 SPac1, Routing report
2
Design: D:\KAKLIK\schemata\default_blz1.pcb
3
==============================================================================================
4
Wed Jun 21 21:08:06 2006
5
 
6
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
7
==============================================================================================
8
Pre-routing analysis 
9
 
10
Warning:Not enough vias for routing from the top to the bottom of the design.
11
	To correct the problem, define additional vias or enable vias for routing using
12
	the Via Biasing tab of the Design Properties dialog box.
13
==============================================================================================
14
Passes Processed:          Route, Optimize
15
Routed Connections:        39(+39)
16
Vias:                      0(+0)
17
Trace length:              18330(+18330) Mils
18
Test points:               0(+0)
19
Accessible nets:           0(+0)
20
Duration                   00:00:07
21
==============================================================================================
22
 
23
Pass:                      3 (Route)
24
Routed Connections:        39(+39)
25
Vias:                      0(+0)
26
Trace length:              18456(+18456) Mils
27
Duration                   00:00:02(+00:00:02)
28
==============================================================================================
29
 
30
Pass:                      4 (Optimize)
31
Vias:                      0(+0)
32
Trace length:              18330(-126) Mils
33
Rerouted:                  0
34
Duration                   00:00:07(+00:00:05)
35
==============================================================================================
36
Wed Jun 21 21:08:28 2006
37
 
38
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
39
==============================================================================================
40
Pre-routing analysis 
41
 
42
Warning:Not enough vias for routing from the top to the bottom of the design.
43
	To correct the problem, define additional vias or enable vias for routing using
44
	the Via Biasing tab of the Design Properties dialog box.
45
==============================================================================================
46
Passes Processed:          Route, Optimize
47
Routed Connections:        39(+0)
48
Vias:                      0(+0)
49
Trace length:              18239(-91) Mils
50
Test points:               0(+0)
51
Accessible nets:           0(+0)
52
Duration                   00:00:05
53
==============================================================================================
54
 
55
Pass:                      3 (Route)
56
Routed Connections:        39(+0)
57
Vias:                      0(+0)
58
Trace length:              18330(+0) Mils
59
Duration                   00:00:00(+00:00:00)
60
==============================================================================================
61
 
62
Pass:                      4 (Optimize)
63
Vias:                      0(+0)
64
Trace length:              18239(-91) Mils
65
Rerouted:                  0
66
Duration                   00:00:05(+00:00:04)
67
==============================================================================================
68
Wed Jun 21 21:08:58 2006
69
 
70
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
71
==============================================================================================
72
Pre-routing analysis 
73
 
74
Warning:Not enough vias for routing from the top to the bottom of the design.
75
	To correct the problem, define additional vias or enable vias for routing using
76
	the Via Biasing tab of the Design Properties dialog box.
77
==============================================================================================
78
Passes Processed:          Route, Optimize
79
Routed Connections:        39(+4)
80
Vias:                      0(+0)
81
Trace length:              18197(+1112) Mils
82
Test points:               0(+0)
83
Accessible nets:           0(+0)
84
Duration                   00:00:05
85
==============================================================================================
86
 
87
Pass:                      3 (Route)
88
Routed Connections:        39(+4)
89
Vias:                      0(+0)
90
Trace length:              18286(+1201) Mils
91
Duration                   00:00:01(+00:00:00)
92
==============================================================================================
93
 
94
Pass:                      4 (Optimize)
95
Vias:                      0(+0)
96
Trace length:              18197(-89) Mils
97
Rerouted:                  0
98
Duration                   00:00:05(+00:00:04)
99
==============================================================================================
100
Wed Jun 21 21:09:09 2006
101
 
102
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
103
==============================================================================================
104
Pre-routing analysis 
105
 
106
Warning:Not enough vias for routing from the top to the bottom of the design.
107
	To correct the problem, define additional vias or enable vias for routing using
108
	the Via Biasing tab of the Design Properties dialog box.
109
==============================================================================================
110
Passes Processed:          Route, Optimize
111
Routed Connections:        39(+0)
112
Vias:                      0(+0)
113
Trace length:              18197(+0) Mils
114
Test points:               0(+0)
115
Accessible nets:           0(+0)
116
Duration                   00:00:05
117
==============================================================================================
118
 
119
Pass:                      3 (Route)
120
Routed Connections:        39(+0)
121
Vias:                      0(+0)
122
Trace length:              18197(+0) Mils
123
Duration                   00:00:00(+00:00:00)
124
==============================================================================================
125
 
126
Pass:                      4 (Optimize)
127
Vias:                      0(+0)
128
Trace length:              18197(+0) Mils
129
Rerouted:                  0
130
Duration                   00:00:05(+00:00:04)
131
==============================================================================================
132
Wed Jun 21 21:10:07 2006
133
 
134
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
135
==============================================================================================
136
Pre-routing analysis 
137
 
138
Warning:Not enough vias for routing from the top to the bottom of the design.
139
	To correct the problem, define additional vias or enable vias for routing using
140
	the Via Biasing tab of the Design Properties dialog box.
141
==============================================================================================
142
Passes Processed:          Route, Optimize
143
Routed Connections:        39(+7)
144
Vias:                      0(+0)
145
Trace length:              17634(+3285) Mils
146
Test points:               0(+0)
147
Accessible nets:           0(+0)
148
Duration                   00:00:06
149
==============================================================================================
150
 
151
Pass:                      3 (Route)
152
Routed Connections:        39(+7)
153
Vias:                      0(+0)
154
Trace length:              17653(+3304) Mils
155
Duration                   00:00:01(+00:00:00)
156
==============================================================================================
157
 
158
Pass:                      4 (Optimize)
159
Vias:                      0(+0)
160
Trace length:              17634(-19) Mils
161
Rerouted:                  0
162
Duration                   00:00:06(+00:00:05)
163
==============================================================================================
164
Wed Jun 21 21:11:11 2006
165
 
166
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
167
==============================================================================================
168
Pre-routing analysis 
169
 
170
Warning:Not enough vias for routing from the top to the bottom of the design.
171
	To correct the problem, define additional vias or enable vias for routing using
172
	the Via Biasing tab of the Design Properties dialog box.
173
==============================================================================================
174
Passes Processed:          Route, Optimize
175
Routed Connections:        39(+9)
176
Vias:                      0(+0)
177
Trace length:              17264(+3659) Mils
178
Test points:               0(+0)
179
Accessible nets:           0(+0)
180
Duration                   00:00:05
181
==============================================================================================
182
 
183
Pass:                      3 (Route)
184
Routed Connections:        39(+9)
185
Vias:                      0(+0)
186
Trace length:              17347(+3742) Mils
187
Duration                   00:00:01(+00:00:00)
188
==============================================================================================
189
 
190
Pass:                      4 (Optimize)
191
Vias:                      0(+0)
192
Trace length:              17264(-83) Mils
193
Rerouted:                  0
194
Duration                   00:00:05(+00:00:04)
195
==============================================================================================
196
Wed Jun 21 21:11:18 2006
197
 
198
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
199
==============================================================================================
200
Pre-routing analysis 
201
 
202
Warning:Not enough vias for routing from the top to the bottom of the design.
203
	To correct the problem, define additional vias or enable vias for routing using
204
	the Via Biasing tab of the Design Properties dialog box.
205
==============================================================================================
206
Passes Processed:          Route, Optimize
207
Routed Connections:        39(+0)
208
Vias:                      0(+0)
209
Trace length:              17297(+33) Mils
210
Test points:               0(+0)
211
Accessible nets:           0(+0)
212
Duration                   00:00:04
213
==============================================================================================
214
 
215
Pass:                      3 (Route)
216
Routed Connections:        39(+0)
217
Vias:                      0(+0)
218
Trace length:              17264(+0) Mils
219
Duration                   00:00:00(+00:00:00)
220
==============================================================================================
221
 
222
Pass:                      4 (Optimize)
223
Vias:                      0(+0)
224
Trace length:              17297(+33) Mils
225
Rerouted:                  0
226
Duration                   00:00:04(+00:00:04)
227
==============================================================================================
228
Wed Jun 21 21:11:41 2006
229
 
230
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
231
==============================================================================================
232
Pre-routing analysis 
233
 
234
Warning:Not enough vias for routing from the top to the bottom of the design.
235
	To correct the problem, define additional vias or enable vias for routing using
236
	the Via Biasing tab of the Design Properties dialog box.
237
==============================================================================================
238
Passes Processed:          Route, Optimize
239
Routed Connections:        38(+3)
240
Vias:                      0(+0)
241
Trace length:              16203(+3778) Mils
242
Test points:               0(+0)
243
Accessible nets:           0(+0)
244
Duration                   00:00:08
245
==============================================================================================
246
 
247
Pass:                      3 (Route)
248
Routed Connections:        38(+3)
249
Vias:                      0(+0)
250
Trace length:              16222(+3797) Mils
251
Duration                   00:00:02(+00:00:02)
252
==============================================================================================
253
 
254
Pass:                      4 (Optimize)
255
Vias:                      0(+0)
256
Trace length:              16203(-19) Mils
257
Rerouted:                  0
258
Duration                   00:00:08(+00:00:06)
259
==============================================================================================
260
Wed Jun 21 21:11:50 2006
261
 
262
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
263
==============================================================================================
264
Pre-routing analysis 
265
 
266
Warning:Not enough vias for routing from the top to the bottom of the design.
267
	To correct the problem, define additional vias or enable vias for routing using
268
	the Via Biasing tab of the Design Properties dialog box.
269
==============================================================================================
270
Passes Processed:          Route, Optimize
271
Routed Connections:        38(+0)
272
Vias:                      0(+0)
273
Trace length:              16203(+0) Mils
274
Test points:               0(+0)
275
Accessible nets:           0(+0)
276
Duration                   00:00:05
277
==============================================================================================
278
 
279
Pass:                      3 (Route)
280
Routed Connections:        38(+0)
281
Vias:                      0(+0)
282
Trace length:              16203(+0) Mils
283
Duration                   00:00:01(+00:00:01)
284
==============================================================================================
285
 
286
Pass:                      4 (Optimize)
287
Vias:                      0(+0)
288
Trace length:              16203(+0) Mils
289
Rerouted:                  0
290
Duration                   00:00:05(+00:00:04)
291
==============================================================================================
292
Wed Jun 21 21:12:24 2006
293
 
294
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
295
==============================================================================================
296
Pre-routing analysis 
297
 
298
Warning:Not enough vias for routing from the top to the bottom of the design.
299
	To correct the problem, define additional vias or enable vias for routing using
300
	the Via Biasing tab of the Design Properties dialog box.
301
==============================================================================================
302
Passes Processed:          Route, Optimize
303
Routed Connections:        39(+1)
304
Vias:                      0(+0)
305
Trace length:              18010(+1245) Mils
306
Test points:               0(+0)
307
Accessible nets:           0(+0)
308
Duration                   00:00:16
309
==============================================================================================
310
 
311
Pass:                      3 (Route)
312
Routed Connections:        39(+1)
313
Vias:                      0(+0)
314
Trace length:              18165(+1400) Mils
315
Duration                   00:00:01(+00:00:00)
316
==============================================================================================
317
 
318
Pass:                      4 (Optimize)
319
Vias:                      0(+0)
320
Trace length:              18010(-155) Mils
321
Rerouted:                  0
322
Duration                   00:00:16(+00:00:15)
323
==============================================================================================
324
Wed Jun 21 21:12:54 2006
325
 
326
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
327
==============================================================================================
328
Pre-routing analysis 
329
 
330
Warning:Not enough vias for routing from the top to the bottom of the design.
331
	To correct the problem, define additional vias or enable vias for routing using
332
	the Via Biasing tab of the Design Properties dialog box.
333
==============================================================================================
334
Passes Processed:          Route, Optimize
335
Routed Connections:        39(+0)
336
Vias:                      0(+0)
337
Trace length:              17141(-129) Mils
338
Test points:               0(+0)
339
Accessible nets:           0(+0)
340
Duration                   00:00:07
341
==============================================================================================
342
 
343
Pass:                      3 (Route)
344
Routed Connections:        39(+0)
345
Vias:                      0(+0)
346
Trace length:              17270(+0) Mils
347
Duration                   00:00:00(+00:00:00)
348
==============================================================================================
349
 
350
Pass:                      4 (Optimize)
351
Vias:                      0(+0)
352
Trace length:              17141(-129) Mils
353
Rerouted:                  0
354
Duration                   00:00:07(+00:00:07)
355
==============================================================================================
356
Wed Jun 21 21:13:26 2006
357
 
358
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
359
==============================================================================================
360
Pre-routing analysis 
361
 
362
Warning:Not enough vias for routing from the top to the bottom of the design.
363
	To correct the problem, define additional vias or enable vias for routing using
364
	the Via Biasing tab of the Design Properties dialog box.
365
==============================================================================================
366
Passes Processed:          Route, Optimize
367
Routed Connections:        38(+0)
368
Vias:                      0(+0)
369
Trace length:              17100(+1) Mils
370
Test points:               0(+0)
371
Accessible nets:           0(+0)
372
Duration                   00:00:04
373
==============================================================================================
374
 
375
Pass:                      3 (Route)
376
Routed Connections:        38(+0)
377
Vias:                      0(+0)
378
Trace length:              17099(+0) Mils
379
Duration                   00:00:01(+00:00:01)
380
==============================================================================================
381
 
382
Pass:                      4 (Optimize)
383
Vias:                      0(+0)
384
Trace length:              17100(+1) Mils
385
Rerouted:                  0
386
Duration                   00:00:04(+00:00:03)
387
==============================================================================================
388
Wed Jun 21 21:13:49 2006
389
 
390
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
391
==============================================================================================
392
Pre-routing analysis 
393
 
394
Warning:Not enough vias for routing from the top to the bottom of the design.
395
	To correct the problem, define additional vias or enable vias for routing using
396
	the Via Biasing tab of the Design Properties dialog box.
397
==============================================================================================
398
Passes Processed:          Route, Optimize
399
Routed Connections:        38(+0)
400
Vias:                      0(+0)
401
Trace length:              17114(-81) Mils
402
Test points:               0(+0)
403
Accessible nets:           0(+0)
404
Duration                   00:00:04
405
==============================================================================================
406
 
407
Pass:                      3 (Route)
408
Routed Connections:        38(+0)
409
Vias:                      0(+0)
410
Trace length:              17195(+0) Mils
411
Duration                   00:00:01(+00:00:01)
412
==============================================================================================
413
 
414
Pass:                      4 (Optimize)
415
Vias:                      0(+0)
416
Trace length:              17114(-81) Mils
417
Rerouted:                  0
418
Duration                   00:00:04(+00:00:03)
419
==============================================================================================
420
Wed Jun 21 21:14:22 2006
421
 
422
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
423
==============================================================================================
424
Pre-routing analysis 
425
 
426
Warning:Not enough vias for routing from the top to the bottom of the design.
427
	To correct the problem, define additional vias or enable vias for routing using
428
	the Via Biasing tab of the Design Properties dialog box.
429
==============================================================================================
430
Passes Processed:          Route, Optimize
431
Routed Connections:        39(+1)
432
Vias:                      0(+0)
433
Trace length:              18523(+1285) Mils
434
Test points:               0(+0)
435
Accessible nets:           0(+0)
436
Duration                   00:00:05
437
==============================================================================================
438
 
439
Pass:                      3 (Route)
440
Routed Connections:        39(+1)
441
Vias:                      0(+0)
442
Trace length:              19299(+2061) Mils
443
Duration                   00:00:01(+00:00:00)
444
==============================================================================================
445
 
446
Pass:                      4 (Optimize)
447
Vias:                      0(+0)
448
Trace length:              18523(-776) Mils
449
Rerouted:                  0
450
Duration                   00:00:05(+00:00:04)
451
==============================================================================================
452
Wed Jun 21 21:14:28 2006
453
 
454
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
455
==============================================================================================
456
Pre-routing analysis 
457
 
458
Warning:Not enough vias for routing from the top to the bottom of the design.
459
	To correct the problem, define additional vias or enable vias for routing using
460
	the Via Biasing tab of the Design Properties dialog box.
461
==============================================================================================
462
Passes Processed:          Route, Optimize
463
Routed Connections:        39(+0)
464
Vias:                      0(+0)
465
Trace length:              18523(+0) Mils
466
Test points:               0(+0)
467
Accessible nets:           0(+0)
468
Duration                   00:00:04
469
==============================================================================================
470
 
471
Pass:                      3 (Route)
472
Routed Connections:        39(+0)
473
Vias:                      0(+0)
474
Trace length:              18523(+0) Mils
475
Duration                   00:00:00(+00:00:00)
476
==============================================================================================
477
 
478
Pass:                      4 (Optimize)
479
Vias:                      0(+0)
480
Trace length:              18523(+0) Mils
481
Rerouted:                  0
482
Duration                   00:00:04(+00:00:03)
483
==============================================================================================
484
Wed Jun 21 21:15:23 2006
485
 
486
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
487
==============================================================================================
488
Pre-routing analysis 
489
 
490
Warning:Not enough vias for routing from the top to the bottom of the design.
491
	To correct the problem, define additional vias or enable vias for routing using
492
	the Via Biasing tab of the Design Properties dialog box.
493
==============================================================================================
494
Passes Processed:          Route, Optimize
495
Routed Connections:        39(+11)
496
Vias:                      0(+0)
497
Trace length:              16987(+4341) Mils
498
Test points:               0(+0)
499
Accessible nets:           0(+0)
500
Duration                   00:00:05
501
==============================================================================================
502
 
503
Pass:                      3 (Route)
504
Routed Connections:        39(+11)
505
Vias:                      0(+0)
506
Trace length:              17038(+4392) Mils
507
Duration                   00:00:01(+00:00:00)
508
==============================================================================================
509
 
510
Pass:                      4 (Optimize)
511
Vias:                      0(+0)
512
Trace length:              16987(-51) Mils
513
Rerouted:                  0
514
Duration                   00:00:05(+00:00:04)
515
==============================================================================================
516
Wed Jun 21 21:15:30 2006
517
 
518
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
519
==============================================================================================
520
Pre-routing analysis 
521
 
522
Warning:Not enough vias for routing from the top to the bottom of the design.
523
	To correct the problem, define additional vias or enable vias for routing using
524
	the Via Biasing tab of the Design Properties dialog box.
525
==============================================================================================
526
Passes Processed:          Route, Optimize
527
Routed Connections:        39(+0)
528
Vias:                      0(+0)
529
Trace length:              16987(+0) Mils
530
Test points:               0(+0)
531
Accessible nets:           0(+0)
532
Duration                   00:00:05
533
==============================================================================================
534
 
535
Pass:                      3 (Route)
536
Routed Connections:        39(+0)
537
Vias:                      0(+0)
538
Trace length:              16987(+0) Mils
539
Duration                   00:00:00(+00:00:00)
540
==============================================================================================
541
 
542
Pass:                      4 (Optimize)
543
Vias:                      0(+0)
544
Trace length:              16987(+0) Mils
545
Rerouted:                  0
546
Duration                   00:00:05(+00:00:04)
547
==============================================================================================
548
Wed Jun 21 21:15:37 2006
549
 
550
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
551
==============================================================================================
552
Pre-routing analysis 
553
 
554
Warning:Not enough vias for routing from the top to the bottom of the design.
555
	To correct the problem, define additional vias or enable vias for routing using
556
	the Via Biasing tab of the Design Properties dialog box.
557
==============================================================================================
558
Passes Processed:          Route, Optimize
559
Routed Connections:        39(+0)
560
Vias:                      0(+0)
561
Trace length:              16987(+0) Mils
562
Test points:               0(+0)
563
Accessible nets:           0(+0)
564
Duration                   00:00:05
565
==============================================================================================
566
 
567
Pass:                      3 (Route)
568
Routed Connections:        39(+0)
569
Vias:                      0(+0)
570
Trace length:              16987(+0) Mils
571
Duration                   00:00:00(+00:00:00)
572
==============================================================================================
573
 
574
Pass:                      4 (Optimize)
575
Vias:                      0(+0)
576
Trace length:              16987(+0) Mils
577
Rerouted:                  0
578
Duration                   00:00:05(+00:00:04)
579
==============================================================================================
580
Wed Jun 21 21:15:44 2006
581
 
582
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
583
==============================================================================================
584
Pre-routing analysis 
585
 
586
Warning:Not enough vias for routing from the top to the bottom of the design.
587
	To correct the problem, define additional vias or enable vias for routing using
588
	the Via Biasing tab of the Design Properties dialog box.
589
==============================================================================================
590
Passes Processed:          Route, Optimize
591
Routed Connections:        39(+0)
592
Vias:                      0(+0)
593
Trace length:              16987(+0) Mils
594
Test points:               0(+0)
595
Accessible nets:           0(+0)
596
Duration                   00:00:05
597
==============================================================================================
598
 
599
Pass:                      3 (Route)
600
Routed Connections:        39(+0)
601
Vias:                      0(+0)
602
Trace length:              16987(+0) Mils
603
Duration                   00:00:00(+00:00:00)
604
==============================================================================================
605
 
606
Pass:                      4 (Optimize)
607
Vias:                      0(+0)
608
Trace length:              16987(+0) Mils
609
Rerouted:                  0
610
Duration                   00:00:05(+00:00:04)
611
==============================================================================================
612
Wed Jun 21 21:26:09 2006
613
 
614
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
615
==============================================================================================
616
Pre-routing analysis 
617
 
618
Warning:Not enough vias for routing from the top to the bottom of the design.
619
	To correct the problem, define additional vias or enable vias for routing using
620
	the Via Biasing tab of the Design Properties dialog box.
621
==============================================================================================
622
Passes Processed:          Route, Optimize
623
Routed Connections:        39(+4)
624
Vias:                      0(+0)
625
Trace length:              17122(+1362) Mils
626
Test points:               0(+0)
627
Accessible nets:           0(+0)
628
Duration                   00:00:05
629
==============================================================================================
630
 
631
Pass:                      3 (Route)
632
Routed Connections:        39(+4)
633
Vias:                      0(+0)
634
Trace length:              17122(+1362) Mils
635
Duration                   00:00:01(+00:00:00)
636
==============================================================================================
637
 
638
Pass:                      4 (Optimize)
639
Vias:                      0(+0)
640
Trace length:              17122(+0) Mils
641
Rerouted:                  0
642
Duration                   00:00:05(+00:00:04)
643
==============================================================================================
644
Wed Jun 21 21:26:16 2006
645
 
646
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
647
==============================================================================================
648
Pre-routing analysis 
649
 
650
Warning:Not enough vias for routing from the top to the bottom of the design.
651
	To correct the problem, define additional vias or enable vias for routing using
652
	the Via Biasing tab of the Design Properties dialog box.
653
==============================================================================================
654
Passes Processed:          Route, Optimize
655
Routed Connections:        39(+0)
656
Vias:                      0(+0)
657
Trace length:              17122(+0) Mils
658
Test points:               0(+0)
659
Accessible nets:           0(+0)
660
Duration                   00:00:05
661
==============================================================================================
662
 
663
Pass:                      3 (Route)
664
Routed Connections:        39(+0)
665
Vias:                      0(+0)
666
Trace length:              17122(+0) Mils
667
Duration                   00:00:00(+00:00:00)
668
==============================================================================================
669
 
670
Pass:                      4 (Optimize)
671
Vias:                      0(+0)
672
Trace length:              17122(+0) Mils
673
Rerouted:                  0
674
Duration                   00:00:05(+00:00:04)
675
==============================================================================================
676
Wed Jun 21 21:26:35 2006
677
 
678
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
679
==============================================================================================
680
Pre-routing analysis 
681
 
682
Warning:Not enough vias for routing from the top to the bottom of the design.
683
	To correct the problem, define additional vias or enable vias for routing using
684
	the Via Biasing tab of the Design Properties dialog box.
685
==============================================================================================
686
Passes Processed:          Route, Optimize
687
Routed Connections:        39(+2)
688
Vias:                      0(+0)
689
Trace length:              17143(+747) Mils
690
Test points:               0(+0)
691
Accessible nets:           0(+0)
692
Duration                   00:00:05
693
==============================================================================================
694
 
695
Pass:                      3 (Route)
696
Routed Connections:        39(+2)
697
Vias:                      0(+0)
698
Trace length:              17158(+762) Mils
699
Duration                   00:00:00(+00:00:00)
700
==============================================================================================
701
 
702
Pass:                      4 (Optimize)
703
Vias:                      0(+0)
704
Trace length:              17143(-15) Mils
705
Rerouted:                  0
706
Duration                   00:00:05(+00:00:04)
707
==============================================================================================
708
Wed Jun 21 21:26:42 2006
709
 
710
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
711
==============================================================================================
712
Pre-routing analysis 
713
 
714
Warning:Not enough vias for routing from the top to the bottom of the design.
715
	To correct the problem, define additional vias or enable vias for routing using
716
	the Via Biasing tab of the Design Properties dialog box.
717
==============================================================================================
718
Passes Processed:          Route, Optimize
719
Routed Connections:        39(+0)
720
Vias:                      0(+0)
721
Trace length:              17143(+0) Mils
722
Test points:               0(+0)
723
Accessible nets:           0(+0)
724
Duration                   00:00:05
725
==============================================================================================
726
 
727
Pass:                      3 (Route)
728
Routed Connections:        39(+0)
729
Vias:                      0(+0)
730
Trace length:              17143(+0) Mils
731
Duration                   00:00:00(+00:00:00)
732
==============================================================================================
733
 
734
Pass:                      4 (Optimize)
735
Vias:                      0(+0)
736
Trace length:              17143(+0) Mils
737
Rerouted:                  0
738
Duration                   00:00:05(+00:00:04)
739
==============================================================================================
740
Wed Jun 21 21:28:12 2006
741
 
742
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
743
==============================================================================================
744
Pre-routing analysis 
745
 
746
Warning:Not enough vias for routing from the top to the bottom of the design.
747
	To correct the problem, define additional vias or enable vias for routing using
748
	the Via Biasing tab of the Design Properties dialog box.
749
==============================================================================================
750
Passes Processed:          Route, Optimize
751
Routed Connections:        39(+6)
752
Vias:                      0(+0)
753
Trace length:              18223(+3788) Mils
754
Test points:               0(+0)
755
Accessible nets:           0(+0)
756
Duration                   00:00:04
757
==============================================================================================
758
 
759
Pass:                      3 (Route)
760
Routed Connections:        39(+6)
761
Vias:                      0(+0)
762
Trace length:              18232(+3797) Mils
763
Duration                   00:00:01(+00:00:01)
764
==============================================================================================
765
 
766
Pass:                      4 (Optimize)
767
Vias:                      0(+0)
768
Trace length:              18223(-9) Mils
769
Rerouted:                  0
770
Duration                   00:00:04(+00:00:02)
771
==============================================================================================
772
Wed Jun 21 21:28:17 2006
773
 
774
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
775
==============================================================================================
776
Pre-routing analysis 
777
 
778
Warning:Not enough vias for routing from the top to the bottom of the design.
779
	To correct the problem, define additional vias or enable vias for routing using
780
	the Via Biasing tab of the Design Properties dialog box.
781
==============================================================================================
782
Passes Processed:          Route, Optimize
783
Routed Connections:        39(+0)
784
Vias:                      0(+0)
785
Trace length:              18027(-196) Mils
786
Test points:               0(+0)
787
Accessible nets:           0(+0)
788
Duration                   00:00:04
789
==============================================================================================
790
 
791
Pass:                      3 (Route)
792
Routed Connections:        39(+0)
793
Vias:                      0(+0)
794
Trace length:              18223(+0) Mils
795
Duration                   00:00:00(+00:00:00)
796
==============================================================================================
797
 
798
Pass:                      4 (Optimize)
799
Vias:                      0(+0)
800
Trace length:              18027(-196) Mils
801
Rerouted:                  0
802
Duration                   00:00:03(+00:00:03)
803
==============================================================================================
804
Wed Jun 21 21:28:47 2006
805
 
806
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
807
==============================================================================================
808
Pre-routing analysis 
809
 
810
Warning:Not enough vias for routing from the top to the bottom of the design.
811
	To correct the problem, define additional vias or enable vias for routing using
812
	the Via Biasing tab of the Design Properties dialog box.
813
==============================================================================================
814
Passes Processed:          Route, Optimize
815
Routed Connections:        39(+39)
816
Vias:                      0(+0)
817
Trace length:              18066(+18066) Mils
818
Test points:               0(+0)
819
Accessible nets:           0(+0)
820
Duration                   00:00:08
821
==============================================================================================
822
 
823
Pass:                      3 (Route)
824
Routed Connections:        39(+39)
825
Vias:                      0(+0)
826
Trace length:              18165(+18165) Mils
827
Duration                   00:00:03(+00:00:02)
828
==============================================================================================
829
 
830
Pass:                      4 (Optimize)
831
Vias:                      0(+0)
832
Trace length:              18066(-99) Mils
833
Rerouted:                  0
834
Duration                   00:00:08(+00:00:05)
835
==============================================================================================
836
Wed Jun 21 21:35:48 2006
837
 
838
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
839
==============================================================================================
840
Pre-routing analysis 
841
 
842
Warning:Not enough vias for routing from the top to the bottom of the design.
843
	To correct the problem, define additional vias or enable vias for routing using
844
	the Via Biasing tab of the Design Properties dialog box.
845
==============================================================================================
846
Passes Processed:          Route, Optimize
847
Routed Connections:        39(+3)
848
Vias:                      0(+0)
849
Trace length:              17526(+1871) Mils
850
Test points:               0(+0)
851
Accessible nets:           0(+0)
852
Duration                   00:00:08
853
==============================================================================================
854
 
855
Pass:                      3 (Route)
856
Routed Connections:        39(+3)
857
Vias:                      0(+0)
858
Trace length:              17492(+1837) Mils
859
Duration                   00:00:01(+00:00:01)
860
==============================================================================================
861
 
862
Pass:                      4 (Optimize)
863
Vias:                      0(+0)
864
Trace length:              17526(+34) Mils
865
Rerouted:                  0
866
Duration                   00:00:08(+00:00:07)
867
==============================================================================================
868
Wed Jun 21 21:36:04 2006
869
 
870
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
871
==============================================================================================
872
Pre-routing analysis 
873
 
874
Warning:Not enough vias for routing from the top to the bottom of the design.
875
	To correct the problem, define additional vias or enable vias for routing using
876
	the Via Biasing tab of the Design Properties dialog box.
877
==============================================================================================
878
Passes Processed:          Route, Optimize
879
Routed Connections:        39(+0)
880
Vias:                      0(+0)
881
Trace length:              17526(+0) Mils
882
Test points:               0(+0)
883
Accessible nets:           0(+0)
884
Duration                   00:00:06
885
==============================================================================================
886
 
887
Pass:                      3 (Route)
888
Routed Connections:        39(+0)
889
Vias:                      0(+0)
890
Trace length:              17526(+0) Mils
891
Duration                   00:00:00(+00:00:00)
892
==============================================================================================
893
 
894
Pass:                      4 (Optimize)
895
Vias:                      0(+0)
896
Trace length:              17526(+0) Mils
897
Rerouted:                  0
898
Duration                   00:00:06(+00:00:06)
899
==============================================================================================
900
Wed Jun 21 21:37:07 2006
901
 
902
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
903
==============================================================================================
904
Pre-routing analysis 
905
 
906
Warning:Not enough vias for routing from the top to the bottom of the design.
907
	To correct the problem, define additional vias or enable vias for routing using
908
	the Via Biasing tab of the Design Properties dialog box.
909
==============================================================================================
910
Passes Processed:          Route, Optimize
911
Routed Connections:        39(+4)
912
Vias:                      0(+0)
913
Trace length:              18099(+2886) Mils
914
Test points:               0(+0)
915
Accessible nets:           0(+0)
916
Duration                   00:00:04
917
==============================================================================================
918
 
919
Pass:                      3 (Route)
920
Routed Connections:        39(+4)
921
Vias:                      0(+0)
922
Trace length:              18403(+3190) Mils
923
Duration                   00:00:01(+00:00:01)
924
==============================================================================================
925
 
926
Pass:                      4 (Optimize)
927
Vias:                      0(+0)
928
Trace length:              18099(-304) Mils
929
Rerouted:                  0
930
Duration                   00:00:04(+00:00:03)
931
==============================================================================================
932
Wed Jun 21 21:38:08 2006
933
 
934
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
935
==============================================================================================
936
Pre-routing analysis 
937
 
938
Warning:Not enough vias for routing from the top to the bottom of the design.
939
	To correct the problem, define additional vias or enable vias for routing using
940
	the Via Biasing tab of the Design Properties dialog box.
941
==============================================================================================
942
Passes Processed:          Route, Optimize
943
Routed Connections:        39(+7)
944
Vias:                      0(+0)
945
Trace length:              17550(+2325) Mils
946
Test points:               0(+0)
947
Accessible nets:           0(+0)
948
Duration                   00:00:07
949
==============================================================================================
950
 
951
Pass:                      3 (Route)
952
Routed Connections:        39(+7)
953
Vias:                      0(+0)
954
Trace length:              17712(+2487) Mils
955
Duration                   00:00:01(+00:00:01)
956
==============================================================================================
957
 
958
Pass:                      4 (Optimize)
959
Vias:                      0(+0)
960
Trace length:              17550(-162) Mils
961
Rerouted:                  0
962
Duration                   00:00:07(+00:00:06)
963
==============================================================================================
964
Wed Jun 21 21:38:15 2006
965
 
966
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
967
==============================================================================================
968
Pre-routing analysis 
969
 
970
Warning:Not enough vias for routing from the top to the bottom of the design.
971
	To correct the problem, define additional vias or enable vias for routing using
972
	the Via Biasing tab of the Design Properties dialog box.
973
==============================================================================================
974
Passes Processed:          Route, Optimize
975
Routed Connections:        39(+0)
976
Vias:                      0(+0)
977
Trace length:              17550(+0) Mils
978
Test points:               0(+0)
979
Accessible nets:           0(+0)
980
Duration                   00:00:06
981
==============================================================================================
982
 
983
Pass:                      3 (Route)
984
Routed Connections:        39(+0)
985
Vias:                      0(+0)
986
Trace length:              17550(+0) Mils
987
Duration                   00:00:00(+00:00:00)
988
==============================================================================================
989
 
990
Pass:                      4 (Optimize)
991
Vias:                      0(+0)
992
Trace length:              17550(+0) Mils
993
Rerouted:                  0
994
Duration                   00:00:06(+00:00:06)
995
==============================================================================================
996
Wed Jun 21 21:39:28 2006
997
 
998
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
999
==============================================================================================
1000
Pre-routing analysis 
1001
 
1002
Warning:Not enough vias for routing from the top to the bottom of the design.
1003
	To correct the problem, define additional vias or enable vias for routing using
1004
	the Via Biasing tab of the Design Properties dialog box.
1005
==============================================================================================
1006
Passes Processed:          Route, Optimize
1007
Routed Connections:        39(+0)
1008
Vias:                      0(+0)
1009
Trace length:              17550(+0) Mils
1010
Test points:               0(+0)
1011
Accessible nets:           0(+0)
1012
Duration                   00:00:06
1013
==============================================================================================
1014
 
1015
Pass:                      3 (Route)
1016
Routed Connections:        39(+0)
1017
Vias:                      0(+0)
1018
Trace length:              17550(+0) Mils
1019
Duration                   00:00:00(+00:00:00)
1020
==============================================================================================
1021
 
1022
Pass:                      4 (Optimize)
1023
Vias:                      0(+0)
1024
Trace length:              17550(+0) Mils
1025
Rerouted:                  0
1026
Duration                   00:00:06(+00:00:06)
1027
==============================================================================================
1028
Wed Jun 21 21:41:21 2006
1029
 
1030
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
1031
==============================================================================================
1032
Pre-routing analysis 
1033
 
1034
Warning:Not enough vias for routing from the top to the bottom of the design.
1035
	To correct the problem, define additional vias or enable vias for routing using
1036
	the Via Biasing tab of the Design Properties dialog box.
1037
==============================================================================================
1038
Passes Processed:          Route, Optimize
1039
Routed Connections:        39(+10)
1040
Vias:                      0(+0)
1041
Trace length:              17178(+2753) Mils
1042
Test points:               0(+0)
1043
Accessible nets:           0(+0)
1044
Duration                   00:00:06
1045
==============================================================================================
1046
 
1047
Pass:                      3 (Route)
1048
Routed Connections:        39(+10)
1049
Vias:                      0(+0)
1050
Trace length:              17250(+2825) Mils
1051
Duration                   00:00:01(+00:00:00)
1052
==============================================================================================
1053
 
1054
Pass:                      4 (Optimize)
1055
Vias:                      0(+0)
1056
Trace length:              17178(-72) Mils
1057
Rerouted:                  0
1058
Duration                   00:00:06(+00:00:06)
1059
==============================================================================================
1060
Wed Jun 21 21:41:31 2006
1061
 
1062
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
1063
==============================================================================================
1064
Pre-routing analysis 
1065
 
1066
Warning:Not enough vias for routing from the top to the bottom of the design.
1067
	To correct the problem, define additional vias or enable vias for routing using
1068
	the Via Biasing tab of the Design Properties dialog box.
1069
==============================================================================================
1070
Passes Processed:          Route, Optimize
1071
Routed Connections:        39(+0)
1072
Vias:                      0(+0)
1073
Trace length:              17178(+0) Mils
1074
Test points:               0(+0)
1075
Accessible nets:           0(+0)
1076
Duration                   00:00:06
1077
==============================================================================================
1078
 
1079
Pass:                      3 (Route)
1080
Routed Connections:        39(+0)
1081
Vias:                      0(+0)
1082
Trace length:              17178(+0) Mils
1083
Duration                   00:00:00(+00:00:00)
1084
==============================================================================================
1085
 
1086
Pass:                      4 (Optimize)
1087
Vias:                      0(+0)
1088
Trace length:              17178(+0) Mils
1089
Rerouted:                  0
1090
Duration                   00:00:06(+00:00:05)
1091
==============================================================================================
1092
Wed Jun 21 21:42:14 2006
1093
 
1094
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
1095
==============================================================================================
1096
Pre-routing analysis 
1097
 
1098
Warning:Not enough vias for routing from the top to the bottom of the design.
1099
	To correct the problem, define additional vias or enable vias for routing using
1100
	the Via Biasing tab of the Design Properties dialog box.
1101
==============================================================================================
1102
Passes Processed:          Route, Optimize
1103
Routed Connections:        39(+2)
1104
Vias:                      0(+0)
1105
Trace length:              17146(+430) Mils
1106
Test points:               0(+0)
1107
Accessible nets:           0(+0)
1108
Duration                   00:00:06
1109
==============================================================================================
1110
 
1111
Pass:                      3 (Route)
1112
Routed Connections:        39(+2)
1113
Vias:                      0(+0)
1114
Trace length:              17146(+430) Mils
1115
Duration                   00:00:01(+00:00:00)
1116
==============================================================================================
1117
 
1118
Pass:                      4 (Optimize)
1119
Vias:                      0(+0)
1120
Trace length:              17146(+0) Mils
1121
Rerouted:                  0
1122
Duration                   00:00:06(+00:00:05)
1123
==============================================================================================
1124
Wed Jun 21 21:42:25 2006
1125
 
1126
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
1127
==============================================================================================
1128
Passes Processed:          Route, Optimize
1129
Routed Connections:        39(+10)
1130
Vias:                      0(+0)
1131
Trace length:              16965(+2836) Mils
1132
Test points:               0(+0)
1133
Accessible nets:           0(+0)
1134
Duration                   00:00:03
1135
==============================================================================================
1136
 
1137
Pass:                      3 (Route)
1138
Routed Connections:        39(+10)
1139
Vias:                      0(+0)
1140
Trace length:              16980(+2851) Mils
1141
Duration                   00:00:01(+00:00:01)
1142
==============================================================================================
1143
 
1144
Pass:                      4 (Optimize)
1145
Vias:                      0(+0)
1146
Trace length:              16965(-15) Mils
1147
Rerouted:                  0
1148
Duration                   00:00:02(+00:00:01)
1149
==============================================================================================
1150
Wed Jun 21 21:42:34 2006
1151
 
1152
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
1153
==============================================================================================
1154
Pre-routing analysis 
1155
 
1156
Warning:Not enough vias for routing from the top to the bottom of the design.
1157
	To correct the problem, define additional vias or enable vias for routing using
1158
	the Via Biasing tab of the Design Properties dialog box.
1159
==============================================================================================
1160
Passes Processed:          Route, Optimize
1161
Routed Connections:        39(+0)
1162
Vias:                      0(+0)
1163
Trace length:              16965(+0) Mils
1164
Test points:               0(+0)
1165
Accessible nets:           0(+0)
1166
Duration                   00:00:05
1167
==============================================================================================
1168
 
1169
Pass:                      3 (Route)
1170
Routed Connections:        39(+0)
1171
Vias:                      0(+0)
1172
Trace length:              16965(+0) Mils
1173
Duration                   00:00:00(+00:00:00)
1174
==============================================================================================
1175
 
1176
Pass:                      4 (Optimize)
1177
Vias:                      0(+0)
1178
Trace length:              16965(+0) Mils
1179
Rerouted:                  0
1180
Duration                   00:00:04(+00:00:04)
1181
==============================================================================================
1182
Wed Jun 21 21:42:58 2006
1183
 
1184
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
1185
==============================================================================================
1186
Pre-routing analysis 
1187
 
1188
Warning:Not enough vias for routing from the top to the bottom of the design.
1189
	To correct the problem, define additional vias or enable vias for routing using
1190
	the Via Biasing tab of the Design Properties dialog box.
1191
==============================================================================================
1192
Passes Processed:          Route, Optimize
1193
Routed Connections:        39(+4)
1194
Vias:                      0(+0)
1195
Trace length:              18810(+5337) Mils
1196
Test points:               0(+0)
1197
Accessible nets:           0(+0)
1198
Duration                   00:00:07
1199
==============================================================================================
1200
 
1201
Pass:                      3 (Route)
1202
Routed Connections:        39(+4)
1203
Vias:                      0(+0)
1204
Trace length:              18862(+5389) Mils
1205
Duration                   00:00:01(+00:00:01)
1206
==============================================================================================
1207
 
1208
Pass:                      4 (Optimize)
1209
Vias:                      0(+0)
1210
Trace length:              18810(-52) Mils
1211
Rerouted:                  0
1212
Duration                   00:00:07(+00:00:05)
1213
==============================================================================================
1214
Wed Jun 21 21:43:08 2006
1215
 
1216
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
1217
==============================================================================================
1218
Pre-routing analysis 
1219
 
1220
Warning:Not enough vias for routing from the top to the bottom of the design.
1221
	To correct the problem, define additional vias or enable vias for routing using
1222
	the Via Biasing tab of the Design Properties dialog box.
1223
==============================================================================================
1224
Passes Processed:          Route, Optimize
1225
Routed Connections:        39(+0)
1226
Vias:                      0(+0)
1227
Trace length:              18810(+0) Mils
1228
Test points:               0(+0)
1229
Accessible nets:           0(+0)
1230
Duration                   00:00:05
1231
==============================================================================================
1232
 
1233
Pass:                      3 (Route)
1234
Routed Connections:        39(+0)
1235
Vias:                      0(+0)
1236
Trace length:              18810(+0) Mils
1237
Duration                   00:00:00(+00:00:00)
1238
==============================================================================================
1239
 
1240
Pass:                      4 (Optimize)
1241
Vias:                      0(+0)
1242
Trace length:              18810(+0) Mils
1243
Rerouted:                  0
1244
Duration                   00:00:05(+00:00:05)
1245
==============================================================================================
1246
Wed Jun 21 21:44:18 2006
1247
 
1248
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
1249
==============================================================================================
1250
Pre-routing analysis 
1251
 
1252
Warning:Not enough vias for routing from the top to the bottom of the design.
1253
	To correct the problem, define additional vias or enable vias for routing using
1254
	the Via Biasing tab of the Design Properties dialog box.
1255
==============================================================================================
1256
Passes Processed:          Route, Optimize
1257
Routed Connections:        39(+3)
1258
Vias:                      0(+0)
1259
Trace length:              18825(+1125) Mils
1260
Test points:               0(+0)
1261
Accessible nets:           0(+0)
1262
Duration                   00:00:06
1263
==============================================================================================
1264
 
1265
Pass:                      3 (Route)
1266
Routed Connections:        39(+3)
1267
Vias:                      0(+0)
1268
Trace length:              18825(+1125) Mils
1269
Duration                   00:00:01(+00:00:00)
1270
==============================================================================================
1271
 
1272
Pass:                      4 (Optimize)
1273
Vias:                      0(+0)
1274
Trace length:              18825(+0) Mils
1275
Rerouted:                  0
1276
Duration                   00:00:05(+00:00:05)
1277
==============================================================================================
1278
Wed Jun 21 21:45:11 2006
1279
 
1280
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
1281
==============================================================================================
1282
Pre-routing analysis 
1283
 
1284
Warning:Not enough vias for routing from the top to the bottom of the design.
1285
	To correct the problem, define additional vias or enable vias for routing using
1286
	the Via Biasing tab of the Design Properties dialog box.
1287
==============================================================================================
1288
Passes Processed:          Route, Optimize
1289
Routed Connections:        39(+0)
1290
Vias:                      0(+0)
1291
Trace length:              18825(+0) Mils
1292
Test points:               0(+0)
1293
Accessible nets:           0(+0)
1294
Duration                   00:00:05
1295
==============================================================================================
1296
 
1297
Pass:                      3 (Route)
1298
Routed Connections:        39(+0)
1299
Vias:                      0(+0)
1300
Trace length:              18825(+0) Mils
1301
Duration                   00:00:00(+00:00:00)
1302
==============================================================================================
1303
 
1304
Pass:                      4 (Optimize)
1305
Vias:                      0(+0)
1306
Trace length:              18825(+0) Mils
1307
Rerouted:                  0
1308
Duration                   00:00:05(+00:00:05)
1309
==============================================================================================
1310
Wed Jun 21 21:46:32 2006
1311
 
1312
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
1313
==============================================================================================
1314
Pre-routing analysis 
1315
 
1316
Warning:Not enough vias for routing from the top to the bottom of the design.
1317
	To correct the problem, define additional vias or enable vias for routing using
1318
	the Via Biasing tab of the Design Properties dialog box.
1319
==============================================================================================
1320
Passes Processed:          Route, Optimize
1321
Routed Connections:        39(+5)
1322
Vias:                      0(+0)
1323
Trace length:              18804(+1048) Mils
1324
Test points:               0(+0)
1325
Accessible nets:           0(+0)
1326
Duration                   00:00:06
1327
==============================================================================================
1328
 
1329
Pass:                      3 (Route)
1330
Routed Connections:        39(+5)
1331
Vias:                      0(+0)
1332
Trace length:              18824(+1068) Mils
1333
Duration                   00:00:01(+00:00:00)
1334
==============================================================================================
1335
 
1336
Pass:                      4 (Optimize)
1337
Vias:                      0(+0)
1338
Trace length:              18804(-20) Mils
1339
Rerouted:                  0
1340
Duration                   00:00:06(+00:00:05)
1341
==============================================================================================
1342
Wed Jun 21 21:47:06 2006
1343
 
1344
Autorouting D:\KAKLIK\schemata\default_blz1.pcb
1345
==============================================================================================
1346
Pre-routing analysis 
1347
 
1348
Warning:Not enough vias for routing from the top to the bottom of the design.
1349
	To correct the problem, define additional vias or enable vias for routing using
1350
	the Via Biasing tab of the Design Properties dialog box.
1351
==============================================================================================
1352
Passes Processed:          Route, Optimize
1353
Routed Connections:        39(+0)
1354
Vias:                      0(+0)
1355
Trace length:              18804(+0) Mils
1356
Test points:               0(+0)
1357
Accessible nets:           0(+0)
1358
Duration                   00:00:05
1359
==============================================================================================
1360
 
1361
Pass:                      3 (Route)
1362
Routed Connections:        39(+0)
1363
Vias:                      0(+0)
1364
Trace length:              18804(+0) Mils
1365
Duration                   00:00:00(+00:00:00)
1366
==============================================================================================
1367
 
1368
Pass:                      4 (Optimize)
1369
Vias:                      0(+0)
1370
Trace length:              18804(+0) Mils
1371
Rerouted:                  0
1372
Duration                   00:00:05(+00:00:05)
1373
==============================================================================================