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**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
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** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
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**** CIRCUIT DESCRIPTION
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******************************************************************************
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** Creating circuit file "test.cir"
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** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
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*Libraries:
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* Profile Libraries :
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* Local Libraries :
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* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_10.5_Demo\tools\PSpice\PSpice.ini file:
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.lib "nom.lib"
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*Analysis directives:
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.AC LIN 5000 10000 30000
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.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
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.INC "..\SCHEMATIC1.net"
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**** INCLUDING SCHEMATIC1.net ****
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* source RECEIVER
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C_C1 0 N03478 15nF
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V_V2 N03432 0 DC 0Vdc AC 1Vac
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R_R1 0 N03490 100
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E_U1 N03510 0 VALUE {LIMIT(V(N03718,N03634)*1E6,-15V,+15V)} _U1 N03718
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+ N03634 1G
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R_R4 N03718 N03462 6.8k
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R_R5 0 N03718 6.8k
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C_C5 N03478 N03718 100nF
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C_C2 N03518 N03510 1n
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R_R6 N03774 N03782 20k
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R_R7 0 N03774 100000k
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V_V1 N03462 0 12Vdc
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R_R2 N03634 N03510 100k
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L_L1 N03462 N03478 3900uH
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C_C3 N03634 N03510 270pF
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X_TX1 N03518 0 N03782 N03774 SCHEMATIC1_TX1
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J_J1 N03478 N03432 N03490 JbreakN
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C_C4 N03622 N03634 1nF
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R_R3 0 N03622 10k
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.subckt SCHEMATIC1_TX1 1 2 3 4
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L1_TX1 1 2 1000
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L2_TX1 3 4 1000
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K_TX1 L1_TX1 L2_TX1 1 KRM8PL_3C8
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.ends SCHEMATIC1_TX1
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**** RESUMING test.cir ****
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.END
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**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
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** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
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**** Junction FET MODEL PARAMETERS
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******************************************************************************
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JbreakN
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NJF
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VTO -2
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BETA 100.000000E-06
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**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
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** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
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**** Ferromagnetic Core MODEL PARAMETERS
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******************************************************************************
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KRM8PL_3C8
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LEVEL 2
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AREA .63
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PATH 3.84
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MS 415.200000E+03
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A 44.82
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C .4112
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K 25.74
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**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
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** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
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**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C
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******************************************************************************
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NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
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(N03432) 0.0000 (N03462) 12.0000 (N03478) 12.0000 (N03490) .0385
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(N03510) 6.0000 (N03518) 0.0000 (N03622) 0.0000 (N03634) 6.0000
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(N03718) 6.0000 (N03774) 0.0000 (N03782) 0.0000
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VOLTAGE SOURCE CURRENTS
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NAME CURRENT
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V_V2 1.206E-11
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V_V1 -1.267E-03
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TOTAL POWER DISSIPATION 1.52E-02 WATTS
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JOB CONCLUDED
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**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
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** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
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**** JOB STATISTICS SUMMARY
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******************************************************************************
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Total job time (using Solver 1) = .89
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