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//dokumenty/skolni/diplomka/conclusion.tex
5,3 → 5,7
\sec Possible future improvements
Several ADC module imperfections, such as useless separation of FRAME and DCO signal to two connectors, should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest.
\bibchap
\usebbl/c mybase