| 48,17 → 48,22 |
|---|
| |
| \sec System description |
| |
| In this section testing system will be described. |
| In this section testing system based on Xilinx ML605 development board \ref[ML605-development-board] will be described. This board was used in previous finished project and was unused until now, but FPGA parrameters are more than enough we need in fast data aquisition system. |
| |
| \secc Frequency synthesis |
| |
| We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO], while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis. Thus is described in separate document} |
| We have used new methods of software frequency monitoring and compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide baseline scale for effective radioastronomy imaging. |
| We have used new methods of software frequency monitoring and compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide baseline scales for effective radioastronomy imaging. |
| |
| GPSDO device consists the Si570 chip with LVPECL output. Phase jitter of GPSDO is determined mainly by Si570 phase noise. Parameters of used Si570 from source \cite[si570-chip] are summarized in table \ref[LO-noise]. |
| |
| GPSDO design included in data acquisition system has special feature -- generates time marks for precise time-stamping of received signal. Timestamps are created by disabling of local oscillator outputs connected to SDRX01B receivers for 100 us. As result rectangle click in ADC input signal is created which appears as horizontal line in spectrogram. |
| Timestamps should be seen in image \ref[meteor-reflection] (above and below meteor reflection). |
| |
| \midinsert \clabel[LO-noise]{Available ADC types} |
| Time-marking should be improved in future by digitalization of GPS signal received by antenna on observational station. GPS signal can be then directly sampled by dedicated receiver and one separate ADC module. Datafile then consists samples from channels of radio-astronomy receivers along with GPS signal containing precise time information. |
| |
| |
| \midinsert \clabel[LO-noise]{Phase noise of used local oscillator} |
| \ctable{lcc}{ |
| & \multispan2 \hfil Phase Noise [dBc/Hz] \hfil \cr |
| Offset Frequency & $F_{out}$ 156.25 MHz & $F_{out}$ 622.08 MHz \cr |
| 75,13 → 80,11 |
|---|
| |
| Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from main local oscillator. This signal should use high quality differential signaling cable -- we should use SATA cable for this purpose. FPGA may slightly affect clock signal quality by additive noise, but has negligible effect in application where developed system will be used. |
| |
| GPSDO design included in data acquisition system has special feature -- generates time marks for precise time-stamping of received signal. Timestamps are created by disabling of local oscillator for 100 us as result rectangle click in input signal is created which appears as horizontal line in spectrogram. |
| Timestamps should be seen in image \ref[meteor-reflection] (above and below meteor reflection). |
| |
| Time-marking should be improved in future by digitalization of GPS signal received by antenna on observational station. GPS signal can be then directly sampled by dedicated receiver an separate ADC module. Datafile then consists samples from channels of radio-astronomy receivers along with GPS signal containing precise time information. |
| |
| \secc Signal cable connectors |
| |
| \label[signal-cables] |
| |
| Several widely used and commercially easily accessible differential connectors were considered to be use in our design. |
| |
| \begitems |
| 91,10 → 94,9 |
|---|
| * SAS/miniSAS |
| \enditems |
| |
| At the end, MiniSAS connector was chosen as the best option to be used in connecting together multiple ADC modules. It is compatible with existing SATA cabling systems and aggregates multiple SATA cables to a single connector. It can be seen on the following picture \ref[img-miniSAS-cable]. A transition between SATA and miniSAS is achieved by SAS to SATA adapter cable which is commonly used in servers to connect SAS controller to multiple SATA hard disc in RAID systems and thus is commercially easily available. |
| The main drawback of miniSAS PCB connectors lies in the fact, that they are manufactured in SMT versions only. The outer metal housing of connector is designed to be mounted using a standard through-hole mounting scheme, a design that unfortunately decreases the durability of the connector. |
| At the end, MiniSAS connector was chosen as the best option to be used in connecting together multiple ADC modules. A transition between SATA and miniSAS is achieved by SAS to SATA adapter cable which is commonly used in servers to connect SAS controller to multiple SATA hard disc in RAID systems and thus is commercially easily available. It is compatible with existing SATA cabling systems and aggregates multiple SATA cables to a single connector, it has SPI configuration lines which can be seen on the following picture \ref[img-miniSAS-cable] as standard pinheader connector. |
| The main drawback of miniSAS PCB connectors lies in the fact, that they are manufactured in SMT versions only, SMT design may eventually decrease the durability of the connector even if outer metal housing of connector is designed to be mounted using a standard through-hole mounting method. |
| |
| |
| \midinsert |
| \clabel[img-miniSAS-cable]{Used miniSAS cable} |
| \picw=5cm \cinspic ./img/miniSAS_SATA_cable.jpg |
| 102,28 → 104,23 |
|---|
| \endinsert |
| |
| \secc Signal integrity requirements |
| |
| \label[diff-signaling] |
| |
| We use ADC modules that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. This imply $ 1/4 \cdot 10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate $t_s$ will be 4.95 m. Although we do not have any cables in system with comparable lengths, worst data bit skew described by data sheets of used components is $0.3 \cdot t_s$, which is 1.485 m. Therefore length matching is not critical in our current design operated on lowest sampling speed. Length matching becomes critical in future version with higher sampling rates, then cable length must be matched. However SATA cabling technology is prepared for that case and matched SATA cables are standard merchandise. |
| We use ADC devices that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. This imply $ 1/4 \cdot 10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate $t_s$ will be 4.95 m. Although we do not have any cables in system with comparable lengths, worst data bit skew described by data sheets of used components is $0.3 \cdot t_s$, which is 1.485 m. Therefore length matching is not critical in our current design operated on lowest sampling speed. Length matching becomes critical in future version with higher sampling rates, then cable length must be matched. However SATA cabling technology is prepared for that case and matched SATA cables are standard merchandise. |
| |
| \secc ADC modules design |
| |
| \midinsert |
| \clabel[adcdual-preview]{Preview of designed ADCdual PCB} |
| \picw=10cm \cinspic ./img/ADCdual_Top.png |
| \picw=10cm \cinspic ./img/ADCdual_Bottom.png |
| \caption/f FPGA ML605 development board. |
| \caption/f Modelled previews of designed and realised PCB of ADCdual01A modules. Differential pairs routing are clearly visible. |
| \endinsert |
| |
| <<<<<<< .mine |
| |
| |
| |
| ======= |
| |
| >>>>>>> .r1124 |
| \secc ADC selection |
| |
| There exist several ADC signaling formats currently used in communication with FPGA. |
| There exist several standard ADC signaling formats currently used in communication with FPGA. |
| |
| \begitems |
| * DDR LVDS |
| 134,42 → 131,38 |
|---|
| * serial LVDS |
| \enditems |
| |
| Because we need to use the smallest number of cables, the choice fell on the serial LVDS format. Small number of differential pairs is an important parameter determining the construction complexity and reliability\cite[serial-lvds]. |
| Because we need to use the smallest number of cables, the choice fell on the serial LVDS format. Small number of differential pairs is an important parameter determining the construction complexity and reliability\cite[serial-lvds]. No much many currently existing ADC devices have this kind of digital interface. An ultrasound AFE device chips seems to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though - it is incapable of handling differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC) and has many single ended ADC channels. Consequently scaling is possible only by a factor of 4 receivers (making 8 analogue single ended channels). |
| |
| An ultrasound AFE chip seems to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though - it is incapable of handling differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC). Because this IO has many ADC channels the scaling is possible only by a factor of 4 receivers (making 8 analogue channels). |
| If we add a requirement of separate output for every analogue channel and a 16bit depth we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these requirements. We have summarized those ADCs in the following table \ref[ADC-types] |
| |
| If we require a separate output for every analogue channel and a 16bit depth we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these requirements. We have summarized the ADCs in the following table \ref[ADC-type] |
| |
| \midinsert \clabel[ADC-types]{Available ADC types} |
| \midinsert |
| \typosize[9/11] \def\tabiteml{ }\let\tabitemr=\tabiteml |
| \clabel[ADC-types]{Available ADC types} |
| \ctable{lccccccc}{ |
| \hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr |
| SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8 \cr |
| SFDR [dB] & 99 & 90 & 90 & 90 & 90 & 90 & 90 \cr |
| S/H Bandwidth [MHz] & 200 & \multispan6 550 \cr |
| Sampling rate [MSPS] & 20 & 25 & 40 & 65 & 80 & 105 & 125 \cr |
| Configuration & \multispan7 SPI \cr |
| Package & \multispan7 52-Lead (7mm $\times$ 8mm) QFN \cr |
| SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8 \cr |
| SFDR [dB] & 99 & 90 & 90 & 90 & 90 & 90 & 90 \cr |
| S/H Bandwidth [MHz] & 200 & \multispan6 550 \strut \cr |
| Sampling rate [MSPS] & 20 & 25 & 40 & 65 & 80 & 105 & 125 \cr |
| Configuration & \multispan7 SPI \strut \cr |
| Package & \multispan7 \hfil 52-Lead (7mm $\times$ 8mm) QFN \hfil \strut \cr |
| } |
| \caption/t The summary of available ADC types and theirs characteristics. |
| \endinsert |
| |
| All parts in this category are compatible with one board layout. Main differences lay in the sampling frequency and signal to noise ratio, with the slowest having a maximum sampling frequency of 20 MHz. However all of them have a minimal sampling frequency of 5 MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..). |
| All parts in this category are compatible with one board layout. Main differences lay in the sampling frequency and signal to noise ratio, with the slowest having a maximum sampling frequency of 20 MHz. However all of them have a minimal sampling frequency of 5 MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..). We selected two slowest types for our evaluation design. Then PCB for this part have been designed. |
| We decided that ADCdual01A modules have a standard MLAB construction layout with four mounting holes in corners aligned in defined raster of 400 mils. |
| |
| Data serial data outputs of ADC modules should be connected directly by LVDS signalling levels conducted by SATA cables to FPGAs for the basic primary signal processing. The ADC chips used in the modules has a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel. This creates a signal concept enabling a selection of a proper bus bit-width according to the sampling rate (higher bus bit-width downgrades signalling speed and vice versa.) |
| |
| In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable should be used as described in section \ref[signal-cables]. |
| |
| The ADC modules have a standard MLAB construction scheme with four mounting holes in corners aligned in defined raster. |
| |
| Data serial data outputs of ADC modules should be connected directly to FPGAs for the basic primary signal processing. The ADC chip used in the modules has a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel. This creates a signal concept enabling a selection of a proper bus bit-width according to the sampling rate (higher bus bit-width downgrades signalling speed and vice versa.) |
| |
| In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable should be used. |
| |
| A KiCAD design suite had been chosen for PCB layout. However, the version is, despite having integrated CERN Push \& Shove routing capability, slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad, the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software. |
| |
| As a part of work on the thesis, new PCB footprints for FMC, SATA a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub. |
| As a part of work on the thesis, new PCB footprints for FMC, SATA, ADCs a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub. |
| |
| ADCdual01A module has several digital data output formats. Difference between these modes lays in the number of differential pairs used. |
| |
| ADCdual01A module has several digital data output formats. Difference between these modes lays in the number of differential pairs used |
| |
| \begitems |
| * 1-lane mode |
| * 2-lane mode |
| 194,13 → 187,13 |
|---|
| \midinsert |
| \picw=10cm \cinspic ./img/FMC2DIFF_top.png |
| \picw=10cm \cinspic ./img/FMC2DIFF_Bottom.png |
| \caption/f FPGA ML605 development board. |
| \caption/f Modelled prewievs of designed and realised PCB of FMC2DIFF01A module. |
| \endinsert |
| |
| Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter module expects the presence of FMC LPC connector and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions]. |
| Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter expects the presence of FMC LPC connector on host side and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions]. |
| This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the appendix. |
| |
| The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques). |
| The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case with ML605 development board. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques). |
| Differential signaling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality. |
| |
| LVPECL level signal connectors on FMC2DIFF01A board are dedicated for clock signals. We selected the SY55855V and SY55857L dual translators. Dual configuration in useful due to fact that SATA cable contains two differential pairs. |
| 211,9 → 204,10 |
|---|
| |
| The SY55857L is a fully differential, high-speed dual translator optimized to accept any logic standard from single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is guaranteed for speeds up to 2.5Gbps (2.5GHz toggle frequency). The SY55857L does not internally terminate its inputs, as different interfacing standards have different termination requirements\cite[SY55857L-chip]. |
| |
| Inputs of both used chips are terminated accordingly to used logic. The LVDS input is terminated differentially by 100 $\Omega$ resistor between positive and negative inputs. PECL input is terminated by Thevenin resistor network. Thevenin termination method was selected as optimal due to absence of proper power voltage (1,3 V) for direct termination by 50 $\Omega$ resistors. Termination on FPGA side is realized directly by settings proper digital logic on input pins. |
| Inputs of both used chips are terminated accordingly to used logic. The LVDS input is terminated differentially by 100 $\Omega$ resistor between positive and negative inputs. PECL input is terminated by Thevenin resistor network. Thevenin termination method was selected as optimal due to absence of proper power voltage (1,3 V) for direct termination by 50 $\Omega$ resistors. Termination on FPGA side is realized directly by settings proper digital logic type on input pins. |
| |
| \midinsert |
| \clabel[ML605-development-board]{ML605 development board} |
| \picw=10cm \cinspic ./img/ML605-board.jpg |
| \caption/f FPGA ML605 development board. |
| \endinsert |
| 224,12 → 218,12 |
|---|
| \caption/f Definition of VITA57 regions. |
| \endinsert |
| |
| % doplnit presny pocet konektoru |
| |
| Several SATA connectors and two miniSAS connectors are populated on this board. This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter. |
| |
| Lengths of differential pairs routed on PCB of the module are not matched between the pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless, signals within differential pairs themselves are matched for length. Internal signal tracing of the length matchting of differential pairs is mandatory in order to avoid a dynamic logic hazard conditions on digital signals. Thus clocks' signals are routed in the most precise way on all designed boards. |
| Lengths of differential pairs routed on PCB of the module are not matched between the pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless, signals within differential pairs themselves are matched for length. Internal signal trace length matching of differential pairs is mandatory in order to minimize jitter and avoid a dynamic logic hazard conditions on digital signals in worst case. Thus clocks signals are routed in the most precise way on all designed boards. |
| |
| |
| Signal configuration used in our trial design is described in the following tables \ref[minisas-interface], \ref[SPI-system] and \ref[clock-interconnections]. |
| |
| |
| 249,7 → 243,6 |
|---|
| \caption/t miniSAS (FMC2DIFF01A J7) signal connections between modules. |
| \endinsert |
| |
| SPI interface is used in an unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back is not possible, thus the configuration written to registers in ADC module cannot be validated. We have not observed any problems with this system, but it may be a possible source of failures. |
| |
| \midinsert \clabel[SPI-system]{SPI configuration interface connections} |
| \ctable {ccc} |
| 267,7 → 260,9 |
|---|
| \caption/t SPI system interconnections |
| \endinsert |
| |
| SPI interface is used in an unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back is not possible, thus the configuration written to registers in ADC module cannot be validated. We have not observed any problems with this system, but it may be a possible source of failures. |
| |
| |
| \midinsert \clabel[clock-interconnections]{System clock interconnections} |
| \ctable {lccc} |
| { |
| 280,20 → 275,16 |
|---|
| \caption/t Clock system interconnections |
| \endinsert |
| |
| |
| |
| \secc FPGA function |
| |
| <<<<<<< .mine |
| Several tasks in separate FPGA blocks are performed by FPGA. In first FPGA prepares sampling clock for ADCdual01A modules by division of main local oscillator. This task is separate block in FPGA and runs asynchronously to other logic. Second block is SPI configuration module, which sends configuration words to ADC modules it is activated by opening of Xillybus interface file. Third block is main module, which resolve ADC - PC communication itself it communicates via PCIe, collect data from ADC hardware and creates data packet \ref[xillybus-interface]. Last block is activated after ADC configuration. |
| ======= |
| Several tasks in our design are performed by FPGA. Firstly, FPGA prepares a sampling clock for ADCdual01A modules this task is separate block in FPGA and runs asynchronously compared to other logical circuits. The second block is a SPI configuration module, which sends the content of configuration registers to the ADC modules after opening of Xillybus interface file. The third block represents the main module which resolves ADC - PC communication itself. The last block is activated after ADC configuration. |
| >>>>>>> .r1124 |
| Several tasks in separate FPGA blocks are performed by FPGA. In first block FPGA prepares sampling clock for ADCdual01A modules by division of main local oscillator. This task is separate block in FPGA and runs asynchronously to other logical circuits. Second block is SPI configuration module, which sends configuration words to ADC modules it is activated by opening of Xillybus interface file. Third block represents the main module, which resolves ADC - PC communication itself it communicates via PCIe, collect data from ADC hardware and creates data packet \ref[xillybus-interface]. Last block is activated after ADC configuration via SPI. |
| |
| Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in system device file named "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are described in the table below \ref[xillybus-interface]. |
| |
| \midinsert \clabel[xillybus-interface]{Grabber binary output format} |
| \ctable {clllllllll}{ |
| \midinsert |
| \typosize[9/11] \def\tabiteml{ }\let\tabitemr=\tabiteml |
| \clabel[xillybus-interface]{Grabber binary output format} |
| \ctable {lccccccccc}{ |
| \hfil & \multispan9 \hfil 160bit packet \hfil \crl \tskip4pt |
| Data name & FRAME & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2 \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil \cr |
| Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr |
| 302,15 → 293,17 |
|---|
| \caption/t System device "/dev/xillybus_data2_r" data format |
| \endinsert |
| |
| Data packet block which is carried on PCI Express is described by table \ref[xillybus-interface]. The data packet consist several 32bit words. First word contain FRAME number and it is filled by saw signal for now, which increments with every data packet transmission. Following data words contains samples from ADCs for first and second channel. Samples from every channel is transmitted in pairs of two samples. Number of ADC channels is expandable according to number of physically connected channels. An CRC word may be added in future at end of transmission packet for data integrity validation. |
| Data packet block which is carried on PCI Express is described by table \ref[xillybus-interface]. The data packet consist several 32bit words. First word contain FRAME number and it is filled by saw signal for now, with increment step of every data packet transmission. Following data words contains samples from ADCs for first and second channel. Samples from every channel is transmitted in pairs of two samples. Number of ADC channels is expandable according to number of physically connected channels. An CRC word may be added in future at end of transmission packet for data integrity validation. |
| |
| FRAME word at beginning of data packet filled with incrementing and overflowing saw signal is used for ensure that no data samples ale lost during data transfers from FPGA. FRAME signal may be used in future for pairing the ADC samples data packet with another data packet in future. This new additional data packet should carry meta-data information about sample time jitter, current accuracy of local oscillator frequency etc. |
| FRAME word at beginning of data packet now filled with incrementing and overflowing saw signal is used for ensure that no data samples ale lost during data transfers from FPGA. FRAME signal may be used in future for pairing the ADC samples data packet with another data packet in future. This new additional data packet should carry meta-data information about sample time jitter, current accuracy of local oscillator frequency etc. |
| |
| Detailed description of currently implemented FPGA functions can be found in separate paper \cite[fpga-middleware]. HDL source codes for FPGA at state which was used are included on enclosed CD. Future development versions are publicly available from MLAB sources repository. |
| |
| % doplnit odkaz na mlab repozitar |
| |
| \secc Data reading and recording |
| |
| In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion which is a graphical tool for creating signal-flow graphs and generating flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view the data stream output from ADC modules. |
| In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view waterfall plots the data streams output from ADC modules. |
| |
| \midinsert |
| \picw=15cm \cinspic ./img/screenshots/Grabber.grc.png |
| 322,7 → 315,7 |
|---|
| \caption/f User interface window of a running ADC grabber. |
| \endinsert |
| |
| The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. |
| The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. Signal is grabbed to file with exactly the same format, as it is described in table \ref[xillybus-interface]. |
| |
| |
| \sec Achieved parameters |
| 334,7 → 327,7 |
|---|
| |
| \label[ADC1-gain] |
| $$ |
| A = {806 \cdot R_1 \over R_1 + R_2} |
| A = {806 \cdot R_1 \over R_1 + R_2} \eqmark |
| $$ |
| |
| Where the letters stand for: |
| 359,7 → 352,7 |
|---|
| |
| \label[ADC2-gain] |
| $$ |
| A = {1580 \cdot R_1 \over R_1 + R_2} |
| A = {1580 \cdot R_1 \over R_1 + R_2} \eqmark |
| $$ |
| |
| Where the letters stand for: |
| 383,7 → 376,7 |
|---|
| |
| \sec Basic interferometric station |
| |
| Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4\' 36.102\" N, 14$^\circ$ 25\' 4.170\" E. |
| Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N, 14$^\circ$ 25' 4.170'' E. |
| Antennae were equipped by LNA01A amplifiers. All coaxial cables have the same length of 5 meters. Antennae were isolated by common mode ferrite bead mounted on cable to minimise the signal coupling between antennas. Evaluation system consists of SDGPSDO local oscillator subsystem used to tune the local oscillator frequency. |
| |
| \midinsert |
| 397,8 → 390,8 |
|---|
| Despite of schematic diagram proposed on beginning of system description.... |
| We used two separate oscillators -- one oscillator drives encode signal to ADCs still through FPGA based divider and other one drives SDRX01B mixer. |
| Reason for this modification is simplification of frequency tuning during experiment. It is because single oscillator may be used only with proper setting of FPGA divider, this divider may be modified only by recompilation of FPGA code and loading/flashing new FPGA schema. Due to fact that FPGA was connected to PCI express and kernel drivers and hardware must be reinitialized, reboot of PC is required. Instead of this procedure, we set the FPGA divider to constant division of factor 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver. |
| We use ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators. |
| |
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| \midinsert |
| \clabel[meteor-reflection]{Meteor reflection} |
| \picw=10cm \cinspic ./img/screenshots/observed_meteor.png |
| 413,9 → 406,7 |
|---|
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| For simplest demonstration of phase difference between antennas, we analyse part of signal by complex conjugate multiplication between channels. Result of this analysis can be seen on picture \ref[phase-difference]. Points of selected part of signal creates clear vector, which illustrates the presence of phase difference. |
| |
| We use ACOUNT02A device for frequency checking on both local oscillators. |
| |
| |
| %\sec Simple passive Doppler radar |
| |
| %\sec Simple polarimeter station |
| 428,7 → 419,7 |
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| \sec Custom design of FPGA board |
| |
| In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than trial design. It should be compatible with MLAB which is further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface. |
| In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than trial design. It should be compatible with MLAB internal standards which is further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface. |
| Thunderbolt technology standard was expected to be used in this PC to PCIe module which further communicate with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as specification is only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need preserve standard PC as main computational platform. |
| |
| However, these PCI express external systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing of thesis. |
| 438,9 → 429,9 |
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| \sec Parralella board computer |
| |
| Parallella is new product from Adapteva, Inc. \cite[parallella-board], this small supercomputer have been in development almost two years and only testing series of boards have been produced until now (first single-board computers with 16-core Epiphany chip were shipped December 2013) \cite[parallella-board]. This board have near ideal parameters for signal processing (provides around 50 GFLOPS of computational power). The board is equipped by Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and 866 MHz operating frequency, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. Completely this board provides In addition of that this board consume only 3 Watts of power if both Zynq and Epiphany cores are running. |
| Parallella is new product from Adapteva, Inc. \cite[parallella-board], this small supercomputer have been in development almost two years and only testing series of boards have been produced until now (first single-board computers with 16-core Epiphany chip were shipped December 2013) \cite[parallella-board]. This board have near ideal parameters for signal processing (provides around 50 GFLOPS of computational power). The board is equipped by Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and 866 MHz operating frequency, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition of that this board consume only 3 Watts of power if both Zynq and Epiphany cores are running. |
| |
| Main disadvantage of Parralella board is is unknown lead time and absence of SATA interface or other interface for data storage connection. Fast data storage interface would be useful and allows bulk processing of captured data. Then a result from data processing will be sent over the Ethernet interface to data storage server. |
| Main disadvantage of Parralella board is is unknown lead time and absence of SATA interface or other interface for data storage connection. Fast data storage interface would be useful and allows bulk processing of captured data. Then a result from data processing will be sent over the Ethernet interface to data storage server. |
| |
| \midinsert |
| \clabel[img-parallella-board]{Parallella board overview} |
| 452,7 → 443,7 |
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| \sec GPU based computational system |
| |
| A new GPU development board NVIDIA K1, shown in the following picture \ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have ideal parameters for signal processing for a relatively low price of 192 USD. Unfortunately, they are currently only in pre-order release stage (in April 2014). |
| A new GPU development board NVIDIA K1, shown in the following picture \ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have good parameters for signal processing for a relatively low price of 192 USD. Unfortunately, they are currently only in pre-order release stage (in April 2014). |
| |
| \midinsert |
| \clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit} |