| 230,7 → 230,7 |
|---|
| |
| Several SATA connectors and two miniSAS connectors are populated on this board. This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter. |
| |
| Lengths of differential pairs routed on PCB of the module are not matched between the pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless, signals within differential pairs themselves are matched for length. Internal signal trace length matching of differential pairs is mandatory in order to minimize jitter and avoid a dynamic logic hazard conditions on digital signals in worst case. Thus clocks signals are routed in the most precise way on all designed boards. |
| Lengths of differential pairs routed on PCB of the module are not matched between the pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless, signals within differential pairs themselves are matched for length. Internal signal trace length matching of differential pairs is mandatory in order to minimize jitter and avoid a dynamic logic hazard conditions on digital signals, that represents the worst scenario. Thus the clocks' signals are routed in the most precise way on all designed boards. |
| |
| Signal configuration used in our trial design is described in the following tables \ref[minisas-interface], \ref[SPI-system] and \ref[clock-interconnections]. |
| |
| 285,9 → 285,9 |
|---|
| |
| \secc FPGA function |
| |
| Several tasks in separate FPGA blocks are performed by FPGA. In first block FPGA prepares sampling clock for ADCdual01A modules by division of main local oscillator. This task is separate block in FPGA and runs asynchronously to other logical circuits. Second block is SPI configuration module, which sends configuration words to ADC modules it is activated by opening of Xillybus interface file. Third block represents the main module, which resolves ADC - PC communication itself it communicates via PCIe, collect data from ADC hardware and creates data packet \ref[xillybus-interface]. Last block is activated after ADC configuration via SPI. |
| Several tasks in separate FPGA blocks are performed by FPGA. In the first block the FPGA prepares a sampling clock for ADCdual01A modules by dividing the signal from the main local oscillator. This task represents a separate block in FPGA and runs asynchronously to other logical circuits. Second block is a SPI configuration module, which sends configuration words to ADC modules and it is activated by opening of Xillybus interface file. Third block represents the main module, which resolves ADC - PC communication itself and it communicates via PCIe, collect data from ADC hardware and creates data packet \ref[xillybus-interface]. Last block is activated after the ADC is configurated via SPI. |
| |
| Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in system device file named "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are described in the table below \ref[xillybus-interface]. |
| Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in a system device file named "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are shown in the table below \ref[xillybus-interface]. |
| |
| \midinsert |
| \def\tabiteml{ }\let\tabitemr=\tabiteml |
| 301,17 → 301,17 |
|---|
| \caption/t System device "/dev/xillybus_data2_r" data format |
| \endinsert |
| |
| Data packet block which is carried on PCI Express is described by table \ref[xillybus-interface]. The data packet consist several 32bit words. First word contain FRAME number and it is filled by saw signal for now, with increment step of every data packet transmission. Following data words contains samples from ADCs for first and second channel. Samples from every channel is transmitted in pairs of two samples. Number of ADC channels is expandable according to number of physically connected channels. An CRC word may be added in future at end of transmission packet for data integrity validation. |
| Data packet block which is carried on PCI Express isa described in the table \ref[xillybus-interface]. The data packet consist of several 32bit words. The first word contains FRAME number and it is filled with saw signal for now, with incremental step taking place every data packet transmission. The following data words contain samples from ADCs' first and second channel. Samples from every channel are transmitted in pairs of two samples. Number of ADC channels is expandable according to the number of physically connected channels. An CRC word may possibly be added in the future to the end of the transmission packet for data integrity validation. |
| |
| FRAME word at beginning of data packet now filled with incrementing and overflowing saw signal is used for ensure that no data samples ale lost during data transfers from FPGA. FRAME signal may be used in future for pairing the ADC samples data packet with another data packet in future. This new additional data packet should carry meta-data information about sample time jitter, current accuracy of local oscillator frequency etc. |
| FRAME word at the beginning of data packet, now filled with incrementing and overflowing saw signal, is used to ensure that no data samples ale lost during the data transfers from FPGA. FRAME signal may be used in the future for pairing the ADC samples' data packet with another data packet. This new additional data packet should carry meta-data information about the sample time jitter, current accuracy of the local oscillator frequency etc. |
| |
| Detailed description of currently implemented FPGA functions can be found in separate paper \cite[fpga-middleware]. HDL source codes for FPGA at state which was used are included on enclosed CD. Future development versions are publicly available from MLAB sources repository. |
| Detailed description of the currently implemented FPGA functions can be found in a separate paper \cite[fpga-middleware]. HDL source codes for FPGA at a state in which it was used are included on the enclosed CD. More recent development versions are publicly available from MLAB sources repository. |
| |
| % doplnit odkaz na mlab repozitar |
| |
| \secc Data reading and recording |
| |
| In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view waterfall plots the data streams output from ADC modules. |
| In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool has been used to create a basic RAW data grabber to record and interactively view waterfall plots using the data streams output from ADC modules. |
| |
| \midinsert |
| \clabel[grabber-flow-graph]{Gnuradio flow graph for signal grabbing} |
| 326,16 → 326,16 |
|---|
| \caption/f User interface window of a running ADC grabber. |
| \endinsert |
| |
| The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. Signal is grabbed to file with exactly the same format, as it is described in table \ref[xillybus-interface]. |
| The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. Signal is grabbed to file with exactly the same format, as described in the table \ref[xillybus-interface]. |
| |
| |
| \chap Achieved parameters |
| |
| Trial design construction was tested for proper handling of sampling rates in range of 5 MSPS to 15 MSPS it should work above this limit. System works on i7 8 cores computer with Ubuntu 12.04 LTS operating system. Data recording of input signal is impossible above sampling rates around 7 MSPS due to bottleneck at HDD speed limits, it should be resolved by use of SSD disk drive. But it is not tested in our setup. |
| The trial version construction was tested for proper handling of sampling rates in the range of 5 MSPS to 15 MSPS, but it should work above this limit. System works on i7 8 cores computer with Ubuntu 12.04 LTS operating system. Data recording of input signal is impossible above the sampling rates around 7 MSPS due to bottleneck at HDD speed limits, but it should be resolved by the use of SSD disk drive. However, such design has not been tested in our setup. |
| |
| \sec Measured parameters |
| |
| Two prototypes of ADC modules were assembled and tested. The first prototype, labeled ADC1, has LTC2190 ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which give it an ability of an internal attenuation of the input signal. The value of this attenuation $A$ is described by the following formula \ref[ADC1-gain] |
| Two prototypes of ADC modules were assembled and tested. The first prototype, labeled ADC1, has LTC2190 ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which give it an ability of an internal attenuation of the input signal. The value of this attenuation $A$ is calculated by the following formula \ref[ADC1-gain] |
| |
| \label[ADC1-gain] |
| $$ |
| 342,7 → 342,7 |
|---|
| A = {806 \cdot R_1 \over R_1 + R_2} \eqmark |
| $$ |
| |
| Where the letters stand for: |
| Where the letters stand for the following: |
| \begitems |
| * $A$ - Gain of an input amplifier. |
| * $R_1$ - Output impedance of signal source (usually 50 Ohm). |
| 349,8 → 349,8 |
|---|
| * $R_2$ - Value of serial resistors at operational amplifier inputs. |
| \enditems |
| |
| We have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply that $A = 0.815$. That value of A is further confirmed by the measurement. |
| In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator. Circuit diagram of used transformer circuit is shown in picture \ref[balun-circuit] and circuit realization in photograph \ref[SMA2SATA-nest]. |
| We have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply that $A = 0.815$. That value of A was further confirmed by the measurement. |
| In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator. Circuit diagram of the used transformer circuit is shown in picture \ref[balun-circuit] and circuit realization in photograph \ref[SMA2SATA-nest]. |
| |
| \midinsert |
| \clabel[balun-circuit]{Balun transformer circuit} |
| 358,7 → 358,7 |
|---|
| \caption/f Simplified balun transformer circuit diagram. |
| \endinsert |
| |
| The signal generator Agilent 33220A which we used does not have optimal parameters for this type of dynamic range measurement. Signal distortion and spurious levels are only -70 dBc according to Agilent datasheet \cite[33220A-generator]. We have managed to measure an ADC saturation voltage of 705.7 mV (generator output) with this setup, mostly due to an impedance mismatch and uncalibrated measurement setup, with 1V ADC range selected by sense pin. This is a relatively large error, but the main result of our measurement, seen as a FFT plot shown in image \ref[ADC1-FFT], confirms $>$80 dB dynamic range at ADC module input. |
| The signal generator Agilent 33220A which we used, does not have optimal parameters for this type of dynamic range measurement. Signal distortion and spurious levels are only -70 dBc according to Agilent datasheet \cite[33220A-generator]. We have managed to measure an ADC saturation voltage of 705.7 mV (generator output) with this setup, mostly due to an impedance mismatch and uncalibrated measurement setup, with 1V ADC range selected by sense pin. This is a relatively large error, but the main result of our measurement, seen as a FFT plot shown in image \ref[ADC1-FFT], confirms $>$80 dB dynamic range at ADC module input. |
| |
| \midinsert |
| \clabel[ADC1-FFT]{ADC1 sine test FFT} |
| 367,7 → 367,7 |
|---|
| \endinsert |
| |
| |
| Similar test was performed at ADC2 module. For ADC2 we have to use formula with a different constant \ref[ADC1-gain]. The ADC2 module has LT6600-2.5 amplifiers populated on it with gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances of used setup. |
| Similar test was performed at ADC2 module. For ADC2 we have to use formula with a different constant \ref[ADC1-gain]. The ADC2 module has LT6600-2.5 amplifiers populated on it with a gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well within the parameter tolerances of the used setup. |
| |
| \label[ADC2-gain] |
| $$ |
| 374,7 → 374,7 |
|---|
| A = {1580 \cdot R_1 \over R_1 + R_2} \eqmark |
| $$ |
| |
| Where the letters stand for: |
| Where the letters stand for the following: |
| \begitems |
| * $A$ - Gain of an input amplifier. |
| * $R_1$ - Output impedance of signal source (usually 50 Ohm). |
| 387,7 → 387,7 |
|---|
| \caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices. |
| \endinsert |
| |
| Computed FFT spectra for measured signal are shown in the images \ref[ADC2-FFT] and \ref[ADC1-FFT]. Both images confirm that ADCdual01A modules have input dynamical range of 80 dB at least. |
| Computed FFT spectra for measured signal are shown in the images \ref[ADC2-FFT] and \ref[ADC1-FFT]. Both images confirm that ADCdual01A modules have input dynamical range of at least 80 dB. |
| |
| \midinsert |
| \clabel[SMA2SATA-nest]{Used balun transformer} |
| 403,8 → 403,8 |
|---|
| |
| \secc Basic interferometric station |
| |
| Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N, 14$^\circ$ 25' 4.170'' E. |
| Antennae were equipped by LNA01A amplifiers. All coaxial cables have the same length of 5 meters. Antennae were isolated by common mode ferrite bead mounted on cable to minimise the signal coupling between antennas. Evaluation system consists of SDGPSDO local oscillator subsystem used to tune the local oscillator frequency. |
| Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in the image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N, 14$^\circ$ 25' 4.170'' E. |
| Antennae were equipped with LNA01A amplifiers. All coaxial cables had the same length of 5 meters. Antennae were isolated by common mode ferrite bead mounted on cable to minimise the signal coupling between antennas. Evaluation system consisted of SDGPSDO local oscillator subsystem used to tune the local oscillator frequency. |
| |
| \midinsert |
| \clabel[block-schematic]{Receiver block schematic} |
| 417,14 → 417,14 |
|---|
| % doplnit schema skutecne pouziteho systemu |
| |
| Despite of the schematic diagram proposed at beginning of system description.... |
| We used two separate oscillators -- one oscillator drives encode signal to ADCs still through FPGA based divider and other one drives SDRX01B mixer. |
| The reason for this modification is a simplification of frequency tuning during the experiment. It is because a single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA schema. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA scheme is changed. Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver. |
| We use ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators. |
| We have used two separate oscillators -- one oscillator drives encoded signal to ADCs still through FPGA based divider and the other one drives it to SDRX01B mixer. |
| The reason for this modification was an attempt to simplify the frequency tuning during the experiment. A single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA schema. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA scheme is changed. Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver. |
| We have used ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators. |
| |
| \midinsert |
| \clabel[meteor-reflection]{Meteor reflection} |
| \picw=10cm \cinspic ./img/screenshots/observed_meteor.png |
| \caption/f Meteor reflection received by evaluation setup. |
| \caption/f Meteor reflection received by an evaluation setup. |
| \endinsert |
| |
| \midinsert |
| 433,7 → 433,7 |
|---|
| \caption/f Demonstration of phase difference between antennae. |
| \endinsert |
| |
| For the simplest demonstration of phase difference between antennae, we have analysed part of the signal by complex conjugate multiplication between channels. Results of this analysis can be seen in the following picture \ref[phase-difference]. Points of the selected part of signal create a clear vector, which illustrates the presence of the phase difference. |
| For the simplest demonstration of phase difference between antennae, we have analysed part of the signal by complex conjugate multiplication between channels. Results of this analysis can be seen in the following picture \ref[phase-difference]. Points of the selected part of the signal create a clear vector, which illustrates the presence of the phase difference. |
| |
| |
| \secc Simple passive Doppler radar |
| 447,23 → 447,26 |
|---|
| |
| \chap Proposition of the final system |
| |
| The construction of a final system, that is supposed to be employed for real radioastronomy observations will be described in this chapter. It is mainly a theoretical analysis of the data handling systems. Realization of the described ideas might be possible as a part of our future development after we fully evaluate and test the current trial design. |
| The construction of the final system, that is supposed to be employed for real radioastronomy observations will be described in this chapter. It is mainly a theoretical analysis of the data handling systems. Realization of the described ideas might be possible as a part of our future development after we fully evaluate and test the current trial design. |
| |
| The system requires proper handling of huge amounts of data and either huge and fast storage capacity is needed for store captured signal data, or enormous computational power is required for online data processing and filtering. Several hardware approach currently exist and are in use for data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially constructed ASICs are used for this task. |
| The system requires proper handling of huge amounts of data and either huge and fast storage capacity is needed to store the captured signal data, or enormous computational power is required for online data processing and filtering. Several hardware approaches currently exist and are in use for data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially constructed ASICs are used for this task. |
| |
| \sec Custom design of FPGA board |
| |
| In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than the trial design. It should be compatible with MLAB internal standards which is further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface. |
| Thunderbolt technology standard was expected to be used in this PC to PCIe module which further communicate with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as specification is only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need preserve standard PC as main computational platform. |
| In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than the trial design. It should be compatible with MLAB internal standards which are further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface. |
| Thunderbolt technology standard was expected to be used in this PC to PCIe module communication which further communicates with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as they are only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need to preserve standard PC as a main computational platform. |
| |
| However, these PCI express external systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing of thesis. |
| Therefore, a better solution probably needs to be found. |
| However, these PCI express external systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing the thesis. Therefore, a better solution probably needs to be found. |
| |
| An interface problem will by probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to an increased demand of embedded technologies, which require high computation capacity, low power consumption and small size -- especially smartphones. Many of those ARM based systems have interesting parameters of signal processing. These facts make Intel's ix86 architecture unattractive for future projects. |
| |
| \sec Parralella board computer |
| |
| <<<<<<< .mine |
| Parallella is a new product created by Adapteva, Inc. \cite[parallella-board]. It represents a small supercomputer, that has been in development for almost two years with only testing series of boards produced until now (first single-board computers with 16-core Epiphany chip were shipped in December 2013) \cite[parallella-board]. The board has nearly ideal parameters for signal processing (as it provides around 50 GFLOPS of computational power). It is is equipped with Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and operating frequency of 866 MHz, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition to this, the board consumes only 3 Watts of power if both Zynq and Epiphany cores are running simultaneously. |
| ======= |
| Parallella is a new product created by Adapteva, Inc. \cite[parallella-board]. It represents a small supercomputer, that has been in development for almost two years with only testing series of boards produced until now (first single-board computers with 16-core Epiphany chip were shipped in December 2013) \cite[parallella-board]. The board has nearly ideal parameters for signal processing (as it provides around 50 GFLOPS of computational power). It is is equipped with Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and operating frequency of 866 MHz, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition to this, the board consumes only 3 Watts of power if both Zynq and Epiphany cores are running simultaniously. |
| >>>>>>> .r1135 |
| |
| The main disadvantage of Parralella board is its unknown lead time and an absence of SATA interface or other interface suitable for data storage connection. Fast data storage interface would be useful and would allow bulk processing of captured data. Following that, the results of data processing may be sent over the Ethernet interface to data storage server. |
| |
| 473,7 → 476,7 |
|---|
| \caption/f Top view on Parallella-16 board \cite[parallella16-board]. |
| \endinsert |
| |
| If Parallella board will be used as a radioastronomy data interface, there would be a demand for new ADC interface module. The interface module will use four PEC connectors mounted on the bottom of the Parallella board. This daughter module should have MLAB compatible design and should preferably be constructed as separable modules for every Parallella's PEC connectors. |
| If Parallella board will be used as a radioastronomy data interface, there would be a demand for new ADC interface module. The interface module will use four PEC connectors mounted on the bottom of the Parallella board. This daughter module should have MLAB compatible design and should preferably be constructed in the form of separable modules for every Parallella's PEC connector. |
| |
| \sec GPU based computational system |
| |
| 485,7 → 488,7 |
|---|
| \caption/f The NVIDIA Jetson TK1 Development Kit \cite[nvidia-k1]. |
| \endinsert |
| |
| NVIDIA board differs from other boards in its category by a presence of PCI Experess connector. If we decide to use this development board in our radio astronomy digitalisation system, the PCI express should be used for FPGA connection. A new FPGA board with PCI Express direct PCB connector |
| NVIDIA board differs from other boards in its category by a presence of PCI Experess connector. If we decide to use this development board in our radio astronomy digitalisation system, the PCI express should be used for FPGA connection. A new FPGA board with PCI Express direct PCB connector |
| |
| % doplnit popis pripojeni FPGA desky s HDMI Kabelem. |
| |
| 494,6 → 497,6 |
|---|
| Other embedded ARM based computers, for example ODROID-XU, lack a suitable high speed interface. Their highest speed interface is USB 3.0 which has currently unsettled development support and needs commercial software tools for evaluation and testing. |
| |
| |
| From the summary analysis mentioned above, the Parrallella board should be a best candidate for computational board in radioastronomy data acquisition system, as it is optimised for high data flow processing. On one hand, Parrallella does not have much memory to cache the processing data but on the other hand it has wide bandwidth data channels instead. Other boards might provide much more computational power -- 300 GFLOPS in case of NVIDIA K1, but they are optimised for heavy computational tasks on limited amount of data which represents a typical problem in computer graphics. However, in our application we do not need such extreme computation power at data acquisition system level. |
| As a result we should presumably wait until Parallella becomes widely available. Following that, a new ADCdual interface board should be designed and prepared to be used in new scalable radio astronomy data acquisition system. In the meantime, before suitable computing hardware become accessible, the required applications and algorithms should be optimised using the proposed trial design. with FPGA development board on standard PC host computer with PCI Express interface to development board. |
| From the summary analysis mentioned above, the Parrallella board seems to be a best candidate for computational board in radioastronomy data acquisition system, as it is optimised for high data flow processing. On one hand, Parrallella does not have much memory to cache the processing data but on the other hand it has wide bandwidth data channels instead. Other boards might provide much more computational power -- 300 GFLOPS in case of NVIDIA K1, but they are optimised for heavy computational tasks on limited amount of data which represents a typical problem in computer graphics. However, in our application we do not need such extreme computation power at data acquisition system level. |
| As a result we should presumably wait until Parallella becomes widely available. Following that, a new ADCdual interface board should be designed and prepared to be used in new scalable radio astronomy data acquisition system. In the meantime, before suitable computing hardware become accessible, the required applications and algorithms should be optimised using the proposed trial version with FPGA development board on standard PC host computer (having a PCI Express interface to development board). |
| |