| 7,7 → 7,7 |
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| \caption/f Expected realisation of signal digitalisation unit. |
| \caption/f Expected realization of signal digitalisation unit. |
| \endinsert |
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| \sec Required parameters |
| 33,20 → 33,20 |
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| The sampling frequency has not been a limiting factor in the trial version. Generally, the sampling frequency is mostly limited by the sampling frequencies of the analog-to-digital conversion chips available on the market and by the interface bandwidth. The combination of required parameters -- dynamic range needing 16 bits at least and a minimum sampling frequency of 1 Mega-Samples Per Second (MSPS\glos{MSPS}{Mega-Samples Per Second}) -- leads to the need of the high-end ADC chips. However, they do not support such low sampling frequencies at all. Their minimum sampling frequency is 5$\ $MSPS. |
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| We calculated the minimal data bandwidth data rate for eight receivers, 2~bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/s. Such data rate is at the limit of the actual writing speed of a classical hard disk drive (HDD\glos{HDD}{Hard disk drive}) and it is almost a double the real bandwidth of USB~2.0\glos{USB 2.0}{Universal Serial Bus version 2.0} interface. As a result of these facts, we must use a faster interface. Such a faster interface is especially needed in cases in which we require faster sampling rates than ADC's minimal 5$\ $MSPS sample rate. |
| We calculated the minimal data bandwidth data rate for eight receivers, 2~bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/sec. Such a data rate is at the limit of the actual writing speed of a classical hard disk drive (HDD\glos{HDD}{Hard disk drive}) and it is almost a double the real bandwidth of USB~2.0\glos{USB 2.0}{Universal Serial Bus version 2.0} interface. As a result of these facts, we must use a faster interface. Such a faster interface is especially needed in cases in which we require faster sampling rates than ADC's minimal 5$\ $MSPS sample rate. |
| The most perspective interface for use in our type of application is USB 3.0 or PCI Express interface. However, USB 3.0 is a relatively new technology without good development tools currently available. We have used PCI Express \glos{PCI Express}{Peripheral Component Interconnect Express} interface as the simplest and the most reliable solution. |
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| \sec System scalability |
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| For analogue channels' scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each analogue channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow for conduction at relatively low digital data rates. As a result, the digital signal can be conducted even through long wires. Modular concept allows a separation from central logical unit which supports optimization of number analogue channels. |
| Special parameters of ADC modules are required to secure scalability of analog channels. Ideally, there should be a separate output for each analog channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow the operation at relatively low digital data rates. As a result, the digital signal can be conducted even via long wires. The modular architecture enables the separation from a central logical unit which supports optimization of a number of analog channels. |
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| Clock and data signals will be then handled distinctively in our modular scalable design. Selected ADC chips are guaranteed to have defined clock skew between the sampling and data output clocks. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.), but these redundant signals are not used for data sampling. If more robustness is required in the final application, DCO \glos{DCO}{Data Clock Output} and FR signals may be collected from other modules and routed through an voting logic which will correct possible signal defects. |
| Clock and data signals will be handled distinctively in our modular scalable design. Selected ADC chips are guaranteed to have the defined clock skew between the sampling and the data output clocks. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement, etc.), but these redundant signals are not used for data sampling. If more robustness is required in the final application then Data Clock Output (DCO\glos{DCO}{Data Clock Output}) and FR signals may be collected from other modules and routed through a voting logic which corrects possible signal defects. |
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| This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power. There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations. |
| This system concept allows for scalability, which is limited technically by a number of differential signals on the host side and its computational power. There is another advantage of the scalable data acquisition system -- an economic one. Observatories or end users can make a choice how much money are they willing to spent on the radioastronomy receiver system. This freedom of choice is especially useful for scientific sites without previous experience in radioastronomy observations. |
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| \secc Differential signalling |
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| The above mentioned concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA \glos{FPGA}{Field-programmable gate array}, Ethernet or other flip-flops blocks and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such cases any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time, a long distance brings problems with the digital signal transmission between ADC and computational unit. But this obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used, such as massively produced and cheap SATA \glos{SATA}{Serial ATA} \glos{ATA}{AT Attachment} cables. This technology has two advantages over PCB \glos{PCB}{printed circuit board} signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path and second, the twisted pair may additionally be shielded by uninterrupted metal foil. |
| The above mentioned concept of the scalable design requires a relatively long circuit traces between ADC and the digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has the advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA\glos{FPGA}{Field-programmable gate array}, Ethernet or other flip-flops blocks and circuit traces, which work usually at high frequencies and emit the wide-band noise with relatively low power. In such cases, any increase in a distance between the noise source and the analog signal source increases S/N significantly. However, at the same time, a long distance introcuces problems with the digital signal transmission between ADC and the computational unit. However, this obstacle should be resolved more easily in a free-space than on board routing. The high-quality differential signalling shielded cables should be used, such as massively produced and cheap SATA\glos{SATA}{Serial ATA}\glos{ATA}{AT Attachment} cables. This technology has two advantages over PCB\glos{PCB}{printed circuit board} signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path. Second, the twisted pair may additionally be shielded by uninterrupted metal foil. |
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| \secc Phase matching |
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