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/dokumenty/skolni/diplomka/appendix.tex
25,13 → 25,14
%\cinspic ./img/zadani.jpg
%\nextoddpage
\app Circuit diagram of ADCdual01A module
\label[adc-scheme] \app Circuit diagram of ADCdual01A module
%\picw=1.3\hsize \rotpic SCH/ADCdual.pdf
\adddocument{SCH/ADCdual}
\app Circuit diagram of FMC2DIFF module
\label[fmc-scheme] \app Circuit diagram of FMC2DIFF module
%\picw=1.3\hsize \rotpic SCH/FMC2DIFF.pdf
\adddocument{SCH/FMC2DIFF}

/dokumenty/skolni/diplomka/description.tex
1,6 → 1,6
\chap Trial version of the receiver, design and implementation
\chap Trial version of the digitizer
The whole design of the radioastronomic receiver digitization unit is meant to be used in a wide range of applications and tasks related to digitization of a signal. A good illustrating problem for its use is the signal digitization from multiple antenna arrays.
The whole design of the radioastronomic receiver digitization unit is meant to be used in a wide range of applications and tasks related to digitization of a signal. A good illustrating problem for its use is the signal digitization from multiple antenna arrays. Design and implementation of the system is presented in this chapter.
\midinsert
\clabel[expected-block-schematic]{Expected system block schematic}
31,9 → 31,9
\sec Sampling frequency
The sampling frequency has not been a limiting factor in the trial version. Generally, the sampling frequency is mostly limited by the sampling frequencies of the analog-to-digital conversion chips available on the market and by the interface bandwidth. The combination of required parameters -- dynamic range needing 16 bits at least and a minimum sampling frequency of 1 Mega-Samples Per Second (MSPS\glos{MSPS}{Mega-Samples Per Second}) -- leads to the need of the high-end ADC chips. However, they do not support such low sampling frequencies at all. Their minimum sampling frequency is 5$\ $MSPS.
The sampling frequency has not been a limiting factor in the trial version. Generally, the sampling frequency is mostly limited by the sampling frequencies of the analog-to-digital conversion chips available on the market and by the interface bandwidth. The combination of required parameters -- dynamic range needing 16 bits at least and a minimum sampling frequency of 1 Mega-Samples Per Second (MSPS\glos{MSPS}{Mega-Samples Per Second}) -- leads to the need of the high-end ADC chips. However, they support minimum sampling frequency 5$\ $MSPS.
We calculated the minimal data bandwidth data rate for eight receivers, 2~bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/sec. Such a data rate is at the limit of the actual writing speed of a classical hard disk drive (HDD\glos{HDD}{Hard disk drive}) and it is almost a double the real bandwidth of USB~2.0\glos{USB 2.0}{Universal Serial Bus version 2.0} interface. As a result of these facts, we must use a faster interface. Such a faster interface is especially needed in cases in which we require faster sampling rates than ADC's minimal 5$\ $MSPS sample rate.
We calculated the minimal data bandwidth rate for eight receivers, 2~bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/sec. Such a data rate is at the limit of the actual writing speed of a classical hard disk drive (HDD\glos{HDD}{Hard disk drive}) and it is almost a double the real bandwidth of USB~2.0\glos{USB 2.0}{Universal Serial Bus version 2.0} interface. As a result of these facts, we must use a faster interface. Such a faster interface is especially needed in cases in which we require faster sampling rates than ADC's minimal 5$\ $MSPS sample rate.
The most perspective interface for use in our type of application is USB 3.0 or PCI Express interface. However, USB 3.0 is a relatively new technology without good development tools currently available. We have used PCI Express \glos{PCI Express}{Peripheral Component Interconnect Express} interface as the simplest and the most reliable solution.
\sec System scalability
46,26 → 46,26
\secc Differential signalling
The above mentioned concept of the scalable design requires a relatively long circuit traces between ADC and the digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has the advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA\glos{FPGA}{Field-programmable gate array}, Ethernet or other flip-flops blocks and circuit traces, which work usually at high frequencies and emit the wide-band noise with relatively low power. In such cases, any increase in a distance between the noise source and the analog signal source increases S/N significantly. However, at the same time, a long distance introcuces problems with the digital signal transmission between ADC and the computational unit. However, this obstacle should be resolved more easily in a free-space than on board routing. The high-quality differential signalling shielded cables should be used, such as massively produced and cheap SATA\glos{SATA}{Serial ATA}\glos{ATA}{AT Attachment} cables. This technology has two advantages over PCB\glos{PCB}{printed circuit board} signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path. Second, the twisted pair may additionally be shielded by uninterrupted metal foil.
The above mentioned concept of the scalable design requires a relatively long circuit traces between ADC and the digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has the advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA\glos{FPGA}{Field-programmable gate array}, Ethernet or other flip-flops blocks and circuit traces work usually at high frequencies and emit the wide-band noise with relatively low power. In such cases, any increase in a distance between the noise source and the analog signal source increases S/N significantly. However, at the same time, a long distance introcuces problems with the digital signal transmission between ADC and the computational unit. This obstacle should be resolved more easily in a free-space than on board routing. The high-quality differential signalling shielded cables should be used, such as massively produced and cheap SATA\glos{SATA}{Serial ATA}\glos{ATA}{AT Attachment} cables. This technology has two advantages over PCB\glos{PCB}{printed circuit board} signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path. Second, the twisted pair may additionally be shielded by uninterrupted metal foil.
\secc Phase matching
The system phase stability is a mandatory condition for multi-antennas radioastronomy projects. It allows a precise, high resolution imaging of objects, increases signal to noise ratios in several observation methods and enables using of advanced algorithms for signal processing.
The high phase stability is achieved in our scalable design through centralized frequency generation and distribution with multi-output Low Voltage Emitter-coupled logic (LVPECL\glos{LVPECL}{Low Voltage Emitter-coupled logic}) hubs (CLKHUB02A), which have equiphased outputs for multiple devices. LVPECL logic is used on every system critical clock signal distribution hub. LVPECL logic has the advantage over the Low-voltage differential signaling (LVDS\glos{LVDS}{Low-voltage differential signaling}) in the signal integrity robustness. LVPECL uses higher logical levels and higher signalling currents. The power consumption of LVPECL logic is nearly constant over the operating frequency range due to the use of bipolar transistors. This arrangement minimizes voltage glitches which are typical for CMOS\glos{CMOS}{Complementary metal–oxide–semiconductor} logic. One drawback of its parameters is a high power consumption of LVPECL logic, which reaches tens of milliamperes per device easily.
The high phase stability is achieved in our scalable design through centralized frequency generation and distribution with multi-output Low Voltage Emitter-coupled logic (LVPECL\glos{LVPECL}{Low Voltage Emitter-coupled logic}) hubs (CLKHUB02A), which have equiphased outputs for multiple devices. The LVPECL logic is used on every system critical clock signal distribution hub. This logic has the advantage over the Low-voltage differential signaling (LVDS\glos{LVDS}{Low-voltage differential signaling}) in the signal integrity robustness. It uses higher logical levels and higher signalling currents. The power consumption of LVPECL logic is nearly constant over the operating frequency range due to the use of bipolar transistors. This arrangement minimizes voltage glitches which are typical for CMOS\glos{CMOS}{Complementary metal–oxide–semiconductor} logic. One drawback of its parameters is a high power consumption of LVPECL logic, which reaches tens of milliamperes per device easily.
This design ensures that all system devices have access to the defined phase and the known frequency.
\sec System description
This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board]. The board had been used in a previous project and has not been used since. However, the FPGA parameters are more than sufficient of what we need for fast data acquisition system.
This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board], available at the workplace. This FPGA parameters are more than sufficient of what we need for the fast data acquisition system being developed.
\secc Frequency synthesis
We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO]. The other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS\glos{GPS}{Global Positioning System} disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma project as a related project, but it is not explicitly required by the thesis itself and thus it is described in a separate document.}
We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator (GPSDO\glos{GPSDO}{GPS disciplined oscillator}) has been used \cite[MLAB-GPSDO]. The other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS\glos{GPS}{Global Positioning System} disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma project as a related project, but it is not explicitly required by the thesis itself and thus it is described in a separate document.}
We have used new methods of software frequency monitoring and compensation in order to meet modern requirements on the radioastronomy equipment, which needs the precise frequency and phase stability over a wide baseline scales for effective radioastronomy imaging.
The GPSDO device consists of Si570 chip with LVPECL output. The phase jitter of the GPS disciplined oscillator (GPSDO\glos{GPSDO}{GPS disciplined oscillator}) is determined mainly by Si570 phase noise. Parameters of the Si570 are summarized in Table~\ref[LO-noise] (source \cite[si570-chip] ).
The GPSDO device consists of Si570 chip with LVPECL output. The phase jitter of the GPS disciplined oscillator is determined mainly by Si570 phase noise. Parameters of the Si570 are summarized in Table~\ref[LO-noise] (source \cite[si570-chip] ).
GPSDO design, which is included in the data acquisition system, has a special feature -- it generates time marks for a precise time-stamping of the received signal. Time-stamps are created by disabling the local oscillator outputs, connected to SDRX01B receivers, for 100 $\mu$s. As the result, a rectangular click in the ADC input signal is created, which appears as a horizontal line in the spectrogram.
Time-stamps should be seen in the image in Figure~\ref[meteor-reflection] (above and below the meteor reflection).
85,7 → 85,7
10 [MHz] & –147 & –146 \cr
100 [MHz] & n/a & –148 \cr
}
\caption/t The phase noise of the used Silicon Laboratories Si570 chip. Offset frequency is measured from carrier frequency. Values shown in the table are given for two different carrier frequencies.
\caption/t The phase noise of the used Silicon Laboratories Si570 chip. Offset frequency is measured from carrier frequency. Values shown in the table are given for two different carrier frequencies. Adopted from \cite[si570-chip].
\endinsert
Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from the main local oscillator. This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose. FPGA may slightly affect the clock signal quality by adding a noise, but it has a negligible effect on the application where developed system will be used.
93,13 → 93,13
\label[signal-cables] \secc Signal cable connectors
Several widely used and commercially easily accessible differential connectors were considered to be used in our design.
Several widely used and commercially easily accessible differential connectors were considered to be used in our design:
\begitems
* HDMI % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
* SATA %{http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]
* DisplayPort %[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>
* SAS/miniSAS
* HDMI, % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
* SATA, %{http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]
* DisplayPort, or %[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>
* SAS/miniSAS.
\enditems
Finally, MiniSAS connector was chosen as the best option to be used in connecting multiple ADC modules together. A transition between SATA and miniSAS is achieved by SAS to SATA adapter cable, which is commonly used in servers to connect SAS controller to multiple SATA hard disc in RAID systems and thus is commercially easily available. It is compatible with existing SATA cabling systems and aggregates multiple SATA cables to a single connector. It also has SPI configuration lines which can be seen in Figure~\ref[img-miniSAS-cable] as the standard pinheader connector.
108,7 → 108,7
\midinsert
\clabel[img-miniSAS-cable]{Used miniSAS cable}
\picw=5cm \cinspic ./img/miniSAS_SATA_cable.jpg
\caption/f An example of miniSAS cable similar to used.
\caption/f An example of a miniSAS cable.
\endinsert
\secc Signal integrity requirements
115,31 → 115,22
\label[diff-signaling]
We use ADC devices that have DATA clock frequency eight times higher than sampling frequency in a single line output mode, implying a 40 MHz output bit rate. This implies a $ 1/4 \cdot 10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5~m light path in a free space. If the copper PCB with FR4 substrate layer or the coaxial/twinax cable is used, we could obtain the velocity factor of 0.66 in the worst case. Consequently, the light path for the same bit rate $t_s$ will be 4.95~m. Although we do not have any cables in the system with comparable lengths, the worst data bit skew described by data sheets of the used components is $0.3 \cdot t_s$, which is 1.485~m. Therefore the length matching is not critical in our current design operating on the lowest sampling speed. The length matching may become critical in future versions with higher sampling rates, where the cable length must be matched. However SATA cabling technology is already prepared for that case and matched SATA cables are a standard merchandise.
We use ADC devices that have DATA clock frequency eight times higher than sampling frequency in a single line output mode, implying a 40 MHz output bit rate. This implies a $t_s=25$~ns time length of data bit, which is equivalent to 7.5~m light path in a free space. If the copper PCB with FR4 substrate layer or the coaxial/twinax cable is used, we could obtain the velocity factor of 0.66 in the worst case. Consequently, the light path for the same bit rate $t_s$ will be 4.95~m. Although we do not have any cables in the system with comparable lengths, the worst data bit skew described by data sheets of the used components is $0.3 \cdot t_s$, which is 1.485~m. Therefore the length matching is not critical in our current design operating on the used sampling speed. The length matching may become critical in future versions with higher sampling rates, where the cable length must be matched. However SATA cabling technology is already prepared for that case and matched SATA cables are a standard merchandise.
\secc ADC modules design
\midinsert
\clabel[adcdual-preview]{Preview of designed ADCdual PCB}
\picw=10cm \cinspic ./img/ADCdual01A_Top_Big.JPG
\picw=10cm \cinspic ./img/ADCdual01A_Bottom_Big.JPG
\caption/f Realised PCB of ADCdual01A modules. Differential pairs routings are clearly visible.
\endinsert
There exist several standard ADC signalling formats currently used in communication with FPGA:
\secc ADC selection
There exist several standard ADC signalling formats currently used in communication with FPGA.
\begitems
* DDR LVDS
* JEDEC 204B
* JESD204A
* Paralel LVDS
* Serdes
* serial LVDS
* DDR LVDS,
* JEDEC 204B,
* JESD204A,
* Paralel LVDS,
* Serdes,
* serial LVDS.
\enditems
As a result of our need to use the smallest number of cables possible, the choice fell on the serial LVDS format. A small number of differential pairs is an important parameter determining the construction complexity and reliability\cite[serial-lvds]. No many currently existing ADC devices have this kind of digital interface. An ultrasound AFE device chips seem to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though. It is incapable of handling the differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC) and has many single ended ADC channels. Consequently, the scaling is possible only by a factor of 4 receivers (making 8 analog single ended channels).
As a result of our need to use the smallest number of cables possible, the choice fell on the serial LVDS format. A small number of differential pairs is an important parameter determining the construction complexity and reliability~\cite[serial-lvds]. No many currently existing ADC devices have this kind of digital interface. An ultrasound AFE device chips seem to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though. It is incapable of handling the differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC) and has many single ended ADC channels. Consequently, the scaling is possible only by a factor of 4 receivers (making 8 analog single ended channels).
If we add a requirement of a separate output for every analog channel and a 16bit depth, we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these criteria. We have summarized those ADCs in Table~\ref[ADC-types].
159,26 → 150,24
\caption/t The summary of the currently available ADC types and theirs characteristics.
\endinsert
All parts in this category are compatible with one board layout. The main differences lay in the sampling frequency and in the signal to noise ratio, with the slowest having a maximum sampling frequency of 20 MHz. However, all of them have a minimal sampling frequency of 5 MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated, etc.). We have selected two slowest types for our evaluation design. Following that, a PCB for this part have been designed.
All parts in this category are compatible with one board layout. The main differences lay in the sampling frequency and in the signal to noise ratio, with the slowest having a maximum sampling frequency of 20~MSPS. However, all of them have a minimal sampling frequency of 5~MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated, etc.). For the first testing realisation, we have selected two slowest types for our evaluation design -- LTC2271 and LTC2190. Following that, a PCB for this part have been designed.
We have decided that ADCdual01A modules will have a standard MLAB construction layout with four mounting holes in corners aligned in defined raster of 400 mils.
Data serial data outputs of ADC modules should be connected directly by LVDS signalling levels conducted by SATA cables to FPGAs for the basic primary signal processing. The ADC chips used in the modules have a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel. This creates a signal concept enabling a selection of the proper bus bit-width according to the sampling rate (the higher bus bit-width downgrades signalling speed and vice versa.)
In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable should be used as described in Section~\ref[signal-cables].
In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable is used as described in Section~\ref[signal-cables].
KiCAD design suite had been chosen for PCB layout. However, the version, despite having integrated CERN Push \& Shove routing capability, is slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad, the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software.
KiCAD design suite had been chosen for PCB layout. As a part of work on the thesis, new PCB footprints for FMC, SATA, ADCs a and miniSAS connectors have been designed and were committed to official KiCAD GitHub library repository. Thus, they are now publicly available.
As a part of work on the thesis, new PCB footprints for FMC, SATA, ADCs a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub.
ADCdual01A module has several digital data output formats. Difference between these modes lays in the number of differential pairs used:
ADCdual01A module has several digital data output formats. Difference between these modes lays in the number of differential pairs used.
\begitems
* 1-lane mode
* 2-lane mode
* 4-lane mode
* 1-lane mode,
* 2-lane mode,
* 4-lane mode.
\enditems
All of the above-mentioned modes are supported by the module design. For the discussed data acquisition system, the 1-lane mode was selected. 1-lane mode allows a minimal number of differential pairs between ADCdual01A and FPGA. Digital signalling scheme used in 1-lane mode is shown in Figure~\ref[1-line-out].
All of the above-mentioned modes are supported by the module design. For the discussed data acquisition system, the 1-lane mode was selected. The 1-lane mode allows a minimal number of differential pairs between ADCdual01A and FPGA. Digital signalling scheme used in the 1-lane mode is shown in Figure~\ref[1-line-out].
\midinsert
\clabel[1-line-out]{Single line ADC output signals}
188,20 → 177,22
ADCdual01A parameters can be set either by jumper setup (referred to as a parallel programming in the device's data sheet) or by SPI interface. SPI interface has been chosen for our system, because of the parallel programming's lack of options (test pattern output setup for example).
Complete schematic diagram of ADCdual01A module board is included in the appendix.
Figure~\ref[adcdual-preview] shows realized ADCdual01A module. Complete schematic diagram of ADCdual01A module board is included in Appendix~\ref[adc-scheme].
\midinsert
\clabel[adcdual-preview]{Preview of designed ADCdual PCB}
\picw=10cm \cinspic ./img/ADCdual01A_Top_Big.JPG
\picw=10cm \cinspic ./img/ADCdual01A_Bottom_Big.JPG
\caption/f Realised PCB of ADCdual01A module. Differential pairs routings are clearly visible.
\endinsert
\secc ADC modules interface
\midinsert
\picw=10cm \cinspic ./img/FMC2DIFF_Top_Big.JPG
\picw=10cm \cinspic ./img/FMC2DIFF_Bottom_Big.JPG
\caption/f Realised PCB of FMC2DIFF01A module.
\endinsert
Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter expects the presence of FMC LPC connector on host side. It is designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in Figure~\ref[VITA57-regions].
This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in Appendix~\ref[fmc-scheme].
Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter expects the presence of FMC LPC connector on host side and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in Figrue~\ref[VITA57-regions].
This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the Appendix.
The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case with ML605 development board. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques).
Differential signalling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
214,11 → 205,6
Inputs of both used chips are terminated accordingly to the used logic. The LVDS input is terminated differentially by 100~$\Omega$ resistor between the positive and the negative inputs. PECL input is terminated by Thevenin resistor network. Thevenin termination method was selected as optimal one, due to the absence of a proper power voltage (1.3 V) for direct termination by 50~$\Omega$ resistors. Termination on FPGA side is realized directly by settings the proper digital logic type on input pins.
\midinsert
\clabel[ML605-development-board]{ML605 development board}
\picw=10cm \cinspic ./img/ML605-board.jpg
\caption/f FPGA ML605 development board.
\endinsert
\midinsert
\clabel[VITA57-regions]{VITA57 board geometry}
268,6 → 254,7
SPI interface is used in an unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back is not possible, thus the configuration written to registers in ADC module cannot be validated. We have not observed any problems with this system, but it may be a possible source of failures.
Realized FMC2DIFF01A module is shown in Figure~\ref[FMC-realized].
\midinsert \clabel[clock-interconnections]{System clock interconnections}
\ctable {lccc}
281,10 → 268,27
\caption/t Clock system interconnections.
\endinsert
\secc FPGA function
\midinsert
\clabel[FMC-realized]{Realized FMC2DIFF01A module}
\picw=10cm \cinspic ./img/FMC2DIFF_Top_Big.JPG
\picw=10cm \cinspic ./img/FMC2DIFF_Bottom_Big.JPG
\caption/f Realised PCB of FMC2DIFF01A module.
\endinsert
Several tasks in the separate FPGA blocks are performed by FPGA. In the first block, the FPGA prepares a sampling clock for ADCdual01A modules by dividing the signal from the main local oscillator. This task represents a separate block in FPGA and runs asynchronously to other logical circuits. The second block is a SPI configuration module, which sends configuration words to ADC modules and it is activated by opening of Xillybus interface file. The third block represents the main module, which resolves ADC - PC communication itself and it communicates via PCIe, collect data from ADC hardware and creates data packet, Table~\ref[xillybus-interface]. The last block is activated after the ADC is configurated via SPI.
\secc FPGA data concentrator
This section describes a specification of data concentrator built using FPGA board. The HDL implementation was created by my colleague Ond{\v r}ej Sychrovsk{\'y}. Detailed description of the currently implemented FPGA functions can be found in a separate paper~\cite[fpga-middleware].
\midinsert
\clabel[ML605-development-board]{ML605 development board}
\picw=10cm \cinspic ./img/ML605-board.jpg
\caption/f FPGA ML605 development board.
\endinsert
Several tasks in the separate IP blocks are performed by FPGA. In the first block, the FPGA prepares a sampling clock for ADCdual01A modules by dividing the signal from the main local oscillator. This task represents a separate block in FPGA and runs asynchronously to other logical circuits. The second block is a SPI configuration module, which sends configuration words to ADC modules and it is activated by opening of Xillybus interface file. The third block represents the main module, which resolves ADC -- PC communication itself and it communicates via PCIe, collect data from ADC hardware and creates data packet, Table~\ref[xillybus-interface]. The last block is activated after the ADC is configurated via SPI.
The communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in a system device file named "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are shown in Table~\ref[xillybus-interface].
\midinsert
303,12 → 307,11
FRAME word at the beginning of data packet, now filled with incrementing and overflowing saw signal, is used to ensure that no data samples ale lost during the data transfers from FPGA. FRAME signal may be used in the future for pairing the ADC samples data packet with another data packet. This new additional data packet should carry meta-data information about the sample time jitter, current accuracy of the local oscillator frequency etc.
Detailed description of the currently implemented FPGA functions can be found in a separate paper~\cite[fpga-middleware]. HDL source codes for FPGA at a state in which it was used are included on the enclosed CD. More recent development versions are publicly available from MLAB sources repository.
Detailed description of currently implemented FPGA functions can be found in separate paper~\cite[fpga-middleware]. HDL\glos{HDL}{Hardware description language} source codes for FPGA at state which was used are included on enclosed CD. Future development versions are publicly available from MLAB sources repository~\cite[mlab-sdrx].
HDL source codes for FPGA at a state in which it was used are included on the enclosed CD. Future development versions will be publicly available from MLAB sources repository~\cite[mlab-sdrx].
\secc Data reading and recording
In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool has been used to create a basic RAW data grabber to record and interactively view waterfall plots using the data streams output from ADC modules.
In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool has been used to create a basic RAW data grabber to record and interactively view waterfall plots using the data streams output from ADC modules. The ADC recorder flow graph is shown in Figure~\ref[grabber-flow-graph].
\midinsert
\clabel[grabber-flow-graph]{Gnuradio flow graph for signal grabbing}
319,11 → 322,12
\endinsert
\midinsert
\clabel[grabber-data]{User interface window of a running ADC grabber}
\picw=15cm \cinspic ./img/screenshots/Grabber_running.png
\caption/f User interface window of a running ADC grabber.
\endinsert
The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. The signal is grabbed to the file with the exactly same format as described in Table \ref[xillybus-interface].
The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. The signal is grabbed to the file with the exactly same format as described in Table \ref[xillybus-interface]. An example of interactive grabber-viewer showing a part of the grabbed signal is in Figure~\ref[grabber-data].

/dokumenty/skolni/diplomka/diplomka.pdf
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/dokumenty/skolni/diplomka/img/screenshots/observed_meteor.png
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/dokumenty/skolni/diplomka/mybase.bbl
13,7 → 13,8
\bibitem{33220A-generator}
Inc. Agilent~Technologies.
\newblock {\em 33220A Function / Arbitrary Waveform Generator, 20 MHz}, 2011.
\newblock {\em 33220A Function / Arbitrary Waveform Generator, 20 MHz},
December 2011.
\newblock
\url{http://www.home.agilent.com/agilent/redirector.jspx?action=obs&nid=536883183.3.00&lc=eng&cc=CZ&ckey=187648&pubno=5988-8544EN&ltype=LitStation&ctype=AGILENT_EDITORIAL&ml=eng}.
38,6 → 39,16
\newblock Simple interferometer, May 2004.
\newblock \url{http://fringes.org/}.
\bibitem{USRP-sdr}
A~National Instruments~Company Ettus~Research.
\newblock Ursp series products, 2013.
\newblock \url{https://www.ettus.com/product/category/USRP-X-Series}.
\bibitem{alfa}
Chris~Salter Fernando~Camilo, Robert~Minchin.
\newblock {\em ALFA: Arecibo L-Band Feed Array}, May 2012.
\newblock \url{http://www.naic.edu/alfa/}.
\bibitem{MLAB-GPSDO}
M.~Kakona J.~Kakona.
\newblock Software defined gps disciplined oscillator - gpsdo01a, January 2014.
47,6 → 58,8
Kortánek Jiří.
\newblock Radioteleskop jove, přijímač ruchů z jupiterových radiových
bouří, bakalářská práce 000672041, September 2007.
\newblock
\url{https://aleph.cvut.cz:443/F?func=direct&doc_number=000672041&local_base=DUPL&format=999}.
\bibitem{fpga-pcie}
Opal Kelly.
66,50 → 79,18
\newblock \url{http://www.ti.com/lit/wp/snaa110/snaa110.pdf}.
\bibitem{lofar}
A.~W. Gunst G. Heald J. P. McKean J. W. T. Hessels A. G. de Bruyn R. Nijboer J.
Swinbank R. Fallows M. Brentjens A. Nelles R. Beck H. Falcke R. Fender J.
Hörandel L. V. E. Koopmans G. Mann G. Miley H. Röttgering B. W. Stappers R.
A. M. J. Wijers S. Zaroubi M. van den Akker A. Alexov J. Anderson K. Anderson
A. van Ardenne M. Arts A. Asgekar I. M. Avruch F. Batejat L. Bähren M. E.
Bell M. R. Bell I. van Bemmel P. Bennema M. J. Bentum G. Bernardi P. Best L.
Bîrzan A. Bonafede A.-J. Boonstra R. Braun J. Bregman F. Breitling R. H. van
de Brink J. Broderick P. C. Broekema W. N. Brouw M. Brüggen H. R. Butcher W.
van Cappellen B. Ciardi T. Coenen J. Conway A. Coolen A. Corstanje S. Damstra
O. Davies A. T. Deller R.-J. Dettmar G. van Diepen K. Dijkstra P. Donker A.
Doorduin J. Dromer M. Drost A. van Duin J. Eislöffel J. van Enst C. Ferrari
W. Frieswijk H. Gankema M. A. Garrett F. de Gasperin M. Gerbers E. de Geus
J.-M. Grießmeier T. Grit P. Gruppen J. P. Hamaker T. Hassall M. Hoeft H.
Holties A. Horneffer A. van der Horst A. van Houwelingen A. Huijgen M.
Iacobelli H. Intema N. Jackson V. Jelic A. de Jong E. Juette D. Kant A.
Karastergiou A. Koers H. Kollen V. I. Kondratiev E. Kooistra Y. Koopman A.
Koster M. Kuniyoshi M. Kramer G. Kuper P. Lambropoulos C. Law J. van Leeuwen
J. Lemaitre M. Loose P. Maat G. Macario S. Markoff J. Masters D.
McKay-Bukowski H. Meijering H. Meulman M. Mevius E. Middelberg R. Millenaar
J. C. A. Miller-Jones R. N. Mohan J. D. Mol J. Morawietz R. Morganti D. D.
Mulcahy E. Mulder H. Munk L. Nieuwenhuis R. van Nieuwpoort J. E. Noordam M.
Norden A. Noutsos A. R. Offringa H. Olofsson A. Omar E. Orrú R. Overeem H.
Paas M. Pandey-Pommier V. N. Pandey R. Pizzo A. Polatidis D. Rafferty S.
Rawlings W. Reich J.-P. de Reijer J. Reitsma A. Renting P. Riemers E. Rol J.
W. Romein J. Roosjen M. Ruiter A. Scaife K. van der Schaaf B. Scheers P.
Schellart A. Schoenmakers G. Schoonderbeek M. Serylak A. Shulevski J. Sluman
O. Smirnov C. Sobey H. Spreeuw M. Steinmetz C. G. M. Sterks H.-J. Stiepel K.
Stuurwold M. Tagger Y. Tang C. Tasse I. Thomas S. Thoudam M. C. Toribio B.
van der Tol O. Usov M. van Veelen A.-J. van der Veen S. ter Veen J. P. W.
Verbiest R. Vermeulen N. Vermaas C. Vocks C. Vogt M. de Vos E. van der Wal R.
van Weeren H. Weggemans P. Weltevrede S. White S. J. Wijnholds T. Wilhelmsson
O. Wucknitz S. Yatawatta P. Zarka A. Zensus J. van~Zwieten M.~P.~van Haarlem,
M. W.~Wise.
et.~al. M.~P.~van Haarlem.
\newblock {\em LOFAR: The LOw-Frequency ARray}, May 2013.
\newblock \url{http://arxiv.org/abs/1305.3550}.
\bibitem{SY55855V-chip}
Inc Micrel.
\newblock {\em SY55855V datasheet}, 2005.
\newblock {\em SY55855V datasheet}, November 2005.
\newblock \url{http://www.micrel.com/_PDF/HBW/sy55855v.pdf}.
\bibitem{SY55857L-chip}
Inc Micrel.
\newblock {\em SY55857L datasheet}, 2006.
\newblock {\em SY55857L datasheet}, August 2006.
\newblock \url{http://www.micrel.com/_PDF/HBW/sy55857l.pdf}.
\bibitem{spectrum-observatory}
134,7 → 115,8
\bibitem{mlab-aras}
Jakub~Kákona MLAB.
\newblock Pokročilá radioastronomická stanice aras01a, September 2013.
\newblock Pokročilá radioastronomická stanice aras01a, Sep 2013.
\newblock \url{http://wiki.mlab.cz/doku.php?id=cs:aras}.
\bibitem{thunderbolt-chips}
Intel Mouser.
158,6 → 140,11
\newblock A new approach to radioastronomy signal processing, May 2014.
\newblock \url{https://casper.berkeley.edu/papers/200509URSI.pdf}.
\bibitem{hackrf-sdr}
Michael Ossmann.
\newblock Hackrf one an open source sdr platform, 2013.
\newblock \url{http://greatscottgadgets.com/hackrf/}.
\bibitem{fmc-sata}
Dan Strother.
\newblock Fmc-lpc to sata adapter board, April 2010.
168,6 → 155,8
Ondřej Sychrovský.
\newblock Connecting an fmc with attached a/d converters -- middleware for an
fpga board, ctu-cmp-2014-5, May 2014.
\newblock
\url{ftp://cmp.felk.cvut.cz/pub/cmp/articles/sychrovsky/Sychrovsky-TR-2014-05.pdf}.
\bibitem{CVUT-FEL:zaverecne-prace}
Ludmila Tichá, Zdeňka Civínová, Michaela Morysková, Ilona Trtíková, and

/dokumenty/skolni/diplomka/mybase.bib
104,7 → 104,6
AUTHOR = {Ettus Research, A National Instruments Company},
TITLE = {URSP Series products},
YEAR = {2013},
MONTH = ,
NOTE = {\url{https://www.ettus.com/product/category/USRP-X-Series}},
URLDATE= {2014-5-3},
}
113,7 → 112,6
AUTHOR = {Michael Ossmann},
TITLE = {HackRF One an open source SDR platform},
YEAR = {2013},
MONTH = ,
NOTE = {\url{http://greatscottgadgets.com/hackrf/}},
URLDATE= {2014-5-11},
}
192,7 → 190,8
AUTHOR = {Ondřej Sychrovský},
TITLE = {Connecting an FMC with attached A/D Converters -- Middleware for an FPGA board, CTU-CMP-2014-5},
YEAR = {2014},
MONTH = May 5,
MONTH = May,
DAY = {5},
NOTE = {\url{ftp://cmp.felk.cvut.cz/pub/cmp/articles/sychrovsky/Sychrovsky-TR-2014-05.pdf}},
}
201,7 → 200,8
AUTHOR = {Kortánek Jiří},
TITLE = {Radioteleskop JOVE, přijímač ruchů z Jupiterových radiových bouří, bakalářská práce 000672041},
YEAR = {2007},
MONTH = Sep 17,
MONTH = Sep,
DAY = {17},
NOTE = {\url{https://aleph.cvut.cz:443/F?func=direct&doc_number=000672041&local_base=DUPL&format=999}},
}
209,7 → 209,7
AUTHOR = {Micrel, Inc},
TITLE = {SY55855V datasheet},
YEAR = {2005},
MONTH = November ,
MONTH = Nov,
NOTE = {\url{http://www.micrel.com/_PDF/HBW/sy55855v.pdf}},
URLDATE= {2014-5-4},
}
219,7 → 219,7
AUTHOR = {Micrel, Inc},
TITLE = {SY55857L datasheet},
YEAR = {2006},
MONTH = August,
MONTH = Aug,
NOTE = {\url{http://www.micrel.com/_PDF/HBW/sy55857l.pdf}},
URLDATE= {2014-5-4},
}
230,7 → 230,7
AUTHOR = {Agilent Technologies, Inc.},
TITLE = {33220A Function / Arbitrary Waveform Generator, 20 MHz},
YEAR = {2011},
MONTH = December,
MONTH = Dec,
NOTE = {\url{http://www.home.agilent.com/agilent/redirector.jspx?action=obs&nid=536883183.3.00&lc=eng&cc=CZ&ckey=187648&pubno=5988-8544EN&ltype=LitStation&ctype=AGILENT_EDITORIAL&ml=eng}},
URLDATE= {2014-5-4},
}
239,7 → 239,8
AUTHOR = {MLAB, Jakub Kákona},
TITLE = {Pokročilá radioastronomická stanice ARAS01A},
YEAR = {2013},
MONTH = Sep 11,
MONTH = {Sep},
DAY = {11},
NOTE = {\url{http://wiki.mlab.cz/doku.php?id=cs:aras}},
URLDATE= {2014-5-4},
}

/dokumenty/skolni/diplomka/testing.tex
8,7 → 8,7
\label[ADC1-gain]
$$
A = {806 R_1 \over R_1 + R_2} \eqmark\,,
A = {806 R_1 \over R_1 + R_2}\,, \eqmark
$$
%
where
19,13 → 19,12
\enditems
We have $R_2 = 1000\, \Omega$ and $R_1 = 50\, \Omega$ which imply that $A = 0.815$. This value of A was further confirmed by the measurement.
In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator. Circuit diagram of the used transformer circuit is shown in Figure~\ref[balun-circuit] and circuit realization in Figure~\ref[SMA2SATA-nest].
In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator, see Figure~\ref[balun-circuit].
\midinsert
\clabel[balun-circuit]{Balun transformer circuit}
\picw=7cm \cinspic ./img/SMA2SATA.pdf
\picw=8cm \cinspic ./img/SMA2SATA_nest1.JPG
\caption/f Simplified balun transformer circuit diagram.
\picw=7cm \hbox{\inspic ./img/SMA2SATA.pdf \picw=8cm \inspic ./img/SMA2SATA_nest1.JPG }
\caption/f Simplified balun transformer circuit diagram (left) and balun transformer constructed from H1012 transformer salvaged from an old Ethernet card (right).
\endinsert
The signal generator Agilent 33220A which we used, does not have optimal parameters for this type of dynamic range measurement. Signal distortion and spurious levels are only -70 dBc according to Agilent datasheet \cite[33220A-generator]. We have managed to measure an ADC saturation voltage of 706 mV (generator output) with this setup. The main result of our measurement, seen as a FFT plot shown in Figure~\ref[ADC1-FFT], confirms $>$80 dB dynamic range at ADC module input.
32,7 → 31,7
\midinsert
\clabel[ADC1-FFT]{ADC1 sine test FFT}
\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
\picw=15cm \cinspic ./img/screenshots/ADC1_CH1_FFT.png
\caption/f Sine signal sampled by ADC1 module with LTC2190 and LT6600-5 devices.
\endinsert
41,7 → 40,7
\label[ADC2-gain]
$$
A = {1580 R_1 \over R_1 + R_2} \eqmark\,.
A = {1580 R_1 \over R_1 + R_2}\,. \eqmark
$$
%
The ADC2 module has LT6600-2.5 amplifiers populated on it with a gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well within the parameter tolerances of the used setup. Again, FFT plot shown in Figure~\ref[ADC2-FFT] confirms $>$ 80 dB dynamic range.
53,13 → 52,6
\caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices.
\endinsert
\midinsert
\clabel[SMA2SATA-nest]{Used balun transformer}
\picw=15cm \cinspic ./img/SMA2SATA_nest1.JPG
\caption/f Balun transformer circuit used for ADC parameters measurement. It is constructed from H1012 transformer salvaged from an old Ethernet card.
\endinsert
\sec Example of usage
At current state the constructed radioastronomy digitization unit paired with SDRX01B receiver module could be used in several experiments. We describe overall ideas of these experiments and show preliminary results in cases where we obtain the data.
66,11 → 58,11
\secc Simple polarimeter station
If we use two antennas with different linear polarization (Crossed Yagi antennas for example), we should determine polarization state of received signal. Such kind of measurement is useful if we need an additional information about reflection to distinguish between targets. This configuration needs more complicated antenna configuration and we had no experience with this type of observation, so we have not implemented this experiment.
If we use two antennas with different linear polarization (Crossed Yagi antennas for example), we should determine polarization state of received signal. Such kind of measurement is useful if we need an additional information about reflection to distinguish between targets. This configuration needs more complicated antenna configuration and we had no experience with this type of observation, so we have not implemented this experiment. However, this is exactly the scenario the system is designed for.
\secc Basic interferometric station
Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in the image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N, 14$^\circ$ 25' 4.170'' E.
Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in the Figure~\ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N, 14$^\circ$ 25' 4.170'' E.
Antennae were equipped with LNA01A amplifiers. All coaxial cables had the same length of 5 meters. Antennae were isolated by common mode ferrite bead mounted on cable to minimise the signal coupling between antennas. Evaluation system consisted of SDGPSDO local oscillator subsystem used to tune the local oscillator frequency.
\midinsert
83,12 → 75,12
Despite of the schematic diagram proposed at beginning of system description \ref[expected-block-schematic].
We have used two separate oscillators -- one oscillator drives ENC signal to ADCs still through FPGA based divider and the other one drives it to SDRX01B mixer.
The reason for this modification was an attempt to simplify the frequency tuning during the experiment. A single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA schema. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA scheme is changed. Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver.
The reason for this modification was an attempt to simplify the frequency tuning during the experiment. A single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA design. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA design is changed. Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver.
We have used ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators.
\midinsert
\clabel[phase-difference]{Phase difference}
\picw=10cm \cinspic ./img/screenshots/phase_difference.png
\picw=15cm \cinspic ./img/screenshots/phase_difference.png
\caption/f Demonstration of phase difference between antennae.
\endinsert
104,7 → 96,7
\midinsert
\clabel[meteor-reflection]{Meteor reflection}
\picw=10cm \cinspic ./img/screenshots/observed_meteor.png
\picw=13cm \cinspic ./img/screenshots/observed_meteor.png
\caption/f Meteor reflection (the red spot in centre of image) received by an evaluation design.
\endinsert
111,7 → 103,7
\chap Proposition of the final system
The construction of the final system, that is supposed to be employed for real radioastronomy observations will be described in this chapter. It is mainly a theoretical analysis of the data handling systems. Realization of the described ideas might be possible as a part of our future development after we fully evaluate and test the current trial design.
The construction of the final system, that is supposed to be employed for real radioastronomy observations is described in this chapter. It is mainly a theoretical analysis of the data handling systems. Realization of the described ideas might be possible as a part of our future development after we fully evaluate and test the current trial design.
The system requires proper handling of huge amounts of data and either huge and fast storage capacity is needed to store the captured signal data, or enormous computational power is required for online data processing and filtering. Several hardware approaches currently exist and are in use for data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially constructed ASICs are used for this task.
120,7 → 112,7
In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than the trial design. It should be compatible with MLAB internal standards which are further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface.
Thunderbolt technology standard was expected to be used in this PC to PCIe module communication which further communicates with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as they are only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need to preserve standard PC as a main computational platform.
However, these PCI express external systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing the thesis. Therefore, a better solution probably needs to be found.
However, these PCI express external systems and cables are still very expensive. The Opal Kelly XEM6110 \cite[fpga-pcie] is an example, with its price tag reaching 995 USD at time of writing the thesis. Therefore, a better solution probably needs to be found.
An interface problem will by probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to an increased demand of embedded technologies, which require high computation capacity, low power consumption and small size -- especially smartphones. Many of those ARM based systems have interesting parameters of signal processing. These facts make Intel's ix86 architecture unattractive for future projects.