48,6 → 48,8 |
mSCL_LOW(); // Clear SCL line |
// enable_interrupts(GLOBAL); |
delay_us( TBUF ); // Wait a few microseconds |
|
toggle_dome(); |
} |
//********************************************************************************************* |
// STOP CONDITION ON SMBus |
71,6 → 73,8 |
delay_us( TBUF ); // Stop condition setup time(Tsu:sto=4.0us min) |
mSDA_HIGH(); // Set SDA line |
// enable_interrupts(GLOBAL); |
|
toggle_dome(); |
} |
|
|
83,9 → 87,6 |
mSCL_HIGH(); // Set SCL line |
delay_us( HIGHLEV ); // High Level of Clock Pulse |
mSCL_LOW(); // Clear SCL line |
|
toggle_dome(); |
|
delay_us( LOWLEV ); // Low Level of Clock Pulse |
// mSDA_HIGH(); // Master release SDA line , |
// enable_interrupts(GLOBAL); |
105,9 → 106,6 |
if(input(SDA)) Ack_bit=1; // \ Read acknowledgment bit, save it in Ack_bit |
else Ack_bit=0; // / |
mSCL_LOW(); // Clear SCL line |
|
toggle_dome(); |
|
delay_us( LOWLEV ); // Low Level of Clock Pulse |
// enable_interrupts(GLOBAL); |
|
214,7 → 212,6 |
j=0x00; |
i--; |
} |
toggle_dome(); |
} |
|
shift=BitPosition-8; /*Get shift value for crc value*/ |
237,7 → 234,6 |
crc[i]+=temp; |
} |
shift--; |
toggle_dome(); |
} |
|
//Exclusive OR between pec and crc |
245,7 → 241,7 |
{ |
pec[i] ^=crc[i]; |
} |
} while(BitPosition>8); |
} while(BitPosition>8);/*End of do-while*/ |
|
return pec[0]; |
} |