| /Modules/PICPGR3/PICPGR301A/GAL/OLD_GAL/!____!.txt |
|---|
| 0,0 → 1,0 |
| Stare verze GAL (1 az 3) nejdou pouzit s touto verzi schematu. |
| /Modules/PICPGR3/PICPGR301A/GAL/OLD_GAL/GAL1.EQN |
|---|
| 0,0 → 1,36 |
| CHIP GAL1 PAL16V8 |
| D0=2 |
| D1=3 |
| D2=4 |
| D3=5 |
| D4=6 |
| D5=7 |
| D6=8 |
| D7=9 |
| GND=10 |
| CLOCK=12 |
| DATA=13 |
| RES=14 |
| VPPON=15 |
| VCCON=16 |
| DQ=17 |
| VCC=20 |
| @UES PICPRG |
| EQUATIONS |
| DATA = D0 |
| DATA.OE = D1 * /D7 |
| CLOCK = D2 |
| CLOCK.OE = D3 * /D7 |
| VCCON = D4 * /D7 |
| VPPON = D5 * /D7 |
| RES = D6 * /D7 |
| DQ = DATA |
| /Modules/PICPGR3/PICPGR301A/GAL/OLD_GAL/GAL1.JED |
|---|
| 0,0 → 1,51 |
| GAL16V8 |
| EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) |
| Copyright (R) National Semiconductor Corporation 1990,1991 |
| Assembled from "gal1.eqn". Date: 8-20-95 |
| * |
| N@ D0 @2 |
| N@ D1 @3 |
| N@ D2 @4 |
| N@ D3 @5 |
| N@ D4 @6 |
| N@ D5 @7 |
| N@ D6 @8 |
| N@ D7 @9 |
| N@ CLOCK @12 |
| N@ DATA @13 |
| N@ RES @14 |
| N@ VPPON @15 |
| N@ VCCON @16 |
| N@ DQ @17 |
| QF2194*QP20*F0* |
| L0512 |
| 11111111111111111111111111111111 |
| 11111111111111111111111111011111* |
| L0768 |
| 11111111111111111111111111111111 |
| 11111111111111110111111111111011* |
| L1024 |
| 11111111111111111111111111111111 |
| 11111111111111111111011111111011* |
| L1280 |
| 11111111111111111111111111111111 |
| 11111111111111111111111101111011* |
| L1536 |
| 11110111111111111111111111111011 |
| 01111111111111111111111111111111* |
| L1792 |
| 11111111111101111111111111111011 |
| 11111111011111111111111111111111* |
| L2048 |
| 00111111* |
| L2056 |
| 0101000001001001010000110101000001010010010001110000000000000000* |
| L2120 |
| 11111111* |
| L2128 |
| 0000000000000000110000001100000011000000110000001100000011000000* |
| L2192 |
| 11* |
| C339C* |
| 0000 |
| /Modules/PICPGR3/PICPGR301A/GAL/OLD_GAL/GAL1.LOG |
|---|
| 0,0 → 1,70 |
| EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) |
| Copyright (R) National Semiconductor Corporation 1990,1991 |
| Document file for gal1.eqn |
| Device: 16V8 |
| $LABELS 20 nc D0 D1 D2 D3 D4 D5 D6 D7 GND nc CLOCK DATA RES VPPON VCCON DQ |
| nc nc VCC |
| Pin Label Type |
| --- ----- ---- |
| 2 D0 com input |
| 3 D1 com input |
| 4 D2 com input |
| 5 D3 com input |
| 6 D4 com input |
| 7 D5 com input |
| 8 D6 com input |
| 9 D7 com input |
| 10 GND ground pin |
| 12 CLOCK pos,trst,com output |
| 13 DATA pos,trst,com feedback |
| 14 RES pos,trst,com output |
| 15 VPPON pos,trst,com output |
| 16 VCCON pos,trst,com output |
| 17 DQ pos,trst,com output |
| 20 VCC power pin |
| EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) |
| Copyright (R) National Semiconductor Corporation 1990,1991 |
| Device Utilization: |
| No of dedicated inputs used : 8/10 (80.0%) |
| No of dedicated outputs used : 2/2 (100.0%) |
| No of feedbacks used as dedicated outputs : 3/6 (50.0%) |
| No of feedbacks used : 1/6 (16.7%) |
| ------------------------------------------ |
| Pin Label Terms Usage |
| ------------------------------------------ |
| 17 DQ 2/8 (25.0%) |
| 16 VCCON 2/8 (25.0%) |
| 15 VPPON 2/8 (25.0%) |
| 14 RES 2/8 (25.0%) |
| 13 DATA 3/8 (37.5%) |
| 12 CLOCK 3/8 (37.5%) |
| ------------------------------------------ |
| Total 12/64 (18.8%) |
| ------------------------------------------ |
| EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) |
| Copyright (R) National Semiconductor Corporation 1990,1991 |
| Chip diagram (DIP) |
| ._____ _____. |
| | \__/ | |
| | 1 20 | VCC |
| D0 | 2 19 | |
| D1 | 3 18 | |
| D2 | 4 17 | DQ |
| D3 | 5 16 | VCCON |
| D4 | 6 15 | VPPON |
| D5 | 7 14 | RES |
| D6 | 8 13 | DATA |
| D7 | 9 12 | CLOCK |
| GND | 10 11 | |
| |______________| |
| /Modules/PICPGR3/PICPGR301A/GAL/OLD_GAL/GAL2.EQN |
|---|
| 0,0 → 1,39 |
| CHIP GAL1 PAL16V8 |
| ; Pro druhou verzi PCB |
| ; bez ochran proti chyne manipulaci |
| ; --- UZ NEPOUZIVAT --- |
| D0=9 |
| D1=8 |
| D2=7 |
| D3=6 |
| D4=5 |
| D5=4 |
| D6=3 |
| D7=2 |
| GND=10 |
| CLOCK=12 |
| DATA=13 |
| RES=15 |
| VPPON=18 |
| VCCON=17 |
| DQ=19 |
| VCC=20 |
| @UES PICPRG |
| EQUATIONS |
| DATA = D0 |
| DATA.OE = D1 * /D7 |
| CLOCK = D2 |
| CLOCK.OE = D3 * /D7 |
| VCCON = D4 * /D7 |
| VPPON = D5 * /D7 |
| RES = D6 * /D7 |
| DQ = DATA |
| /Modules/PICPGR3/PICPGR301A/GAL/OLD_GAL/GAL2.JED |
|---|
| 0,0 → 1,51 |
| GAL16V8 |
| EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) |
| Copyright (R) National Semiconductor Corporation 1990,1991 |
| Assembled from "gal2.eqn". Date: 1-20-96 |
| * |
| N@ D7 @2 |
| N@ D6 @3 |
| N@ D5 @4 |
| N@ D4 @5 |
| N@ D3 @6 |
| N@ D2 @7 |
| N@ D1 @8 |
| N@ D0 @9 |
| N@ CLOCK @12 |
| N@ DATA @13 |
| N@ RES @15 |
| N@ VCCON @17 |
| N@ VPPON @18 |
| N@ DQ @19 |
| QF2194*QP20*F0* |
| L0000 |
| 11111111111111111111111111111111 |
| 11111111111111111111111111011111* |
| L0256 |
| 11111111111111111111111111111111 |
| 10111111011111111111111111111111* |
| L0512 |
| 11111111111111111111111111111111 |
| 10111111111101111111111111111111* |
| L1024 |
| 11111111111111111111111111111111 |
| 10110111111111111111111111111111* |
| L1536 |
| 10111111111111111111111101111111 |
| 11111111111111111111111111110111* |
| L1792 |
| 10111111111111110111111111111111 |
| 11111111111111111111011111111111* |
| L2048 |
| 11101011* |
| L2056 |
| 0101000001001001010000110101000001010010010001110000000000000000* |
| L2120 |
| 11111111* |
| L2128 |
| 1100000011000000110000000000000011000000000000001100000011000000* |
| L2192 |
| 11* |
| C33FE* |
| 0000 |
| /Modules/PICPGR3/PICPGR301A/GAL/OLD_GAL/GAL2.LOG |
|---|
| 0,0 → 1,70 |
| EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) |
| Copyright (R) National Semiconductor Corporation 1990,1991 |
| Document file for gal2.eqn |
| Device: 16V8 |
| $LABELS 20 nc D7 D6 D5 D4 D3 D2 D1 D0 GND nc CLOCK DATA nc RES nc VCCON VPPON |
| DQ VCC |
| Pin Label Type |
| --- ----- ---- |
| 2 D7 com input |
| 3 D6 com input |
| 4 D5 com input |
| 5 D4 com input |
| 6 D3 com input |
| 7 D2 com input |
| 8 D1 com input |
| 9 D0 com input |
| 10 GND ground pin |
| 12 CLOCK pos,trst,com output |
| 13 DATA pos,trst,com feedback |
| 15 RES pos,trst,com output |
| 17 VCCON pos,trst,com output |
| 18 VPPON pos,trst,com output |
| 19 DQ pos,trst,com output |
| 20 VCC power pin |
| EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) |
| Copyright (R) National Semiconductor Corporation 1990,1991 |
| Device Utilization: |
| No of dedicated inputs used : 8/10 (80.0%) |
| No of dedicated outputs used : 2/2 (100.0%) |
| No of feedbacks used as dedicated outputs : 3/6 (50.0%) |
| No of feedbacks used : 1/6 (16.7%) |
| ------------------------------------------ |
| Pin Label Terms Usage |
| ------------------------------------------ |
| 19 DQ 2/8 (25.0%) |
| 18 VPPON 2/8 (25.0%) |
| 17 VCCON 2/8 (25.0%) |
| 15 RES 2/8 (25.0%) |
| 13 DATA 3/8 (37.5%) |
| 12 CLOCK 3/8 (37.5%) |
| ------------------------------------------ |
| Total 12/64 (18.8%) |
| ------------------------------------------ |
| EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) |
| Copyright (R) National Semiconductor Corporation 1990,1991 |
| Chip diagram (DIP) |
| ._____ _____. |
| | \__/ | |
| | 1 20 | VCC |
| D7 | 2 19 | DQ |
| D6 | 3 18 | VPPON |
| D5 | 4 17 | VCCON |
| D4 | 5 16 | |
| D3 | 6 15 | RES |
| D2 | 7 14 | |
| D1 | 8 13 | DATA |
| D0 | 9 12 | CLOCK |
| GND | 10 11 | |
| |______________| |
| /Modules/PICPGR3/PICPGR301A/GAL/OLD_GAL/GAL3.EQN |
|---|
| 0,0 → 1,40 |
| CHIP GAL1 PAL16V8 |
| ; Pro druhou verzi PCB |
| ; s ochranami proti chyne manipulaci |
| ; WORK VERZE |
| D0=9 |
| D1=8 |
| D2=7 |
| D3=6 |
| D4=5 |
| D5=4 |
| D6=3 |
| D7=2 |
| GND=10 |
| CLOCK=12 |
| DATA=13 |
| RES=15 |
| VPPON=18 |
| VCCON=17 |
| DQ=19 |
| VCC=20 |
| @UES PICPRG |
| EQUATIONS |
| DATA = D0 |
| DATA.OE = D1 * /D7 |
| CLOCK = D2 |
| CLOCK.OE = D3 * /D7 |
| VCCON = D4 * /D7 |
| VPPON = D5 * /D7 * D4 |
| RES = D6 * /D7 * /D5 |
| DQ = DATA |
| /Modules/PICPGR3/PICPGR301A/GAL/OLD_GAL/GAL3.JED |
|---|
| 0,0 → 1,51 |
| GAL16V8 |
| EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) |
| Copyright (R) National Semiconductor Corporation 1990,1991 |
| Assembled from "gal3.eqn". Date: 1-22-96 |
| * |
| N@ D7 @2 |
| N@ D6 @3 |
| N@ D5 @4 |
| N@ D4 @5 |
| N@ D3 @6 |
| N@ D2 @7 |
| N@ D1 @8 |
| N@ D0 @9 |
| N@ CLOCK @12 |
| N@ DATA @13 |
| N@ RES @15 |
| N@ VCCON @17 |
| N@ VPPON @18 |
| N@ DQ @19 |
| QF2194*QP20*F0* |
| L0000 |
| 11111111111111111111111111111111 |
| 11111111111111111111111111011111* |
| L0256 |
| 11111111111111111111111111111111 |
| 10111111011101111111111111111111* |
| L0512 |
| 11111111111111111111111111111111 |
| 10111111111101111111111111111111* |
| L1024 |
| 11111111111111111111111111111111 |
| 10110111101111111111111111111111* |
| L1536 |
| 10111111111111111111111101111111 |
| 11111111111111111111111111110111* |
| L1792 |
| 10111111111111110111111111111111 |
| 11111111111111111111011111111111* |
| L2048 |
| 11101011* |
| L2056 |
| 0101000001001001010000110101000001010010010001110000000000000000* |
| L2120 |
| 11111111* |
| L2128 |
| 1100000011000000110000000000000011000000000000001100000011000000* |
| L2192 |
| 11* |
| C33EC* |
| 0000 |
| /Modules/PICPGR3/PICPGR301A/GAL/OLD_GAL/GAL3.LOG |
|---|
| 0,0 → 1,70 |
| EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) |
| Copyright (R) National Semiconductor Corporation 1990,1991 |
| Document file for gal3.eqn |
| Device: 16V8 |
| $LABELS 20 nc D7 D6 D5 D4 D3 D2 D1 D0 GND nc CLOCK DATA nc RES nc VCCON VPPON |
| DQ VCC |
| Pin Label Type |
| --- ----- ---- |
| 2 D7 com input |
| 3 D6 com input |
| 4 D5 com input |
| 5 D4 com input |
| 6 D3 com input |
| 7 D2 com input |
| 8 D1 com input |
| 9 D0 com input |
| 10 GND ground pin |
| 12 CLOCK pos,trst,com output |
| 13 DATA pos,trst,com feedback |
| 15 RES pos,trst,com output |
| 17 VCCON pos,trst,com output |
| 18 VPPON pos,trst,com output |
| 19 DQ pos,trst,com output |
| 20 VCC power pin |
| EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) |
| Copyright (R) National Semiconductor Corporation 1990,1991 |
| Device Utilization: |
| No of dedicated inputs used : 8/10 (80.0%) |
| No of dedicated outputs used : 2/2 (100.0%) |
| No of feedbacks used as dedicated outputs : 3/6 (50.0%) |
| No of feedbacks used : 1/6 (16.7%) |
| ------------------------------------------ |
| Pin Label Terms Usage |
| ------------------------------------------ |
| 19 DQ 2/8 (25.0%) |
| 18 VPPON 2/8 (25.0%) |
| 17 VCCON 2/8 (25.0%) |
| 15 RES 2/8 (25.0%) |
| 13 DATA 3/8 (37.5%) |
| 12 CLOCK 3/8 (37.5%) |
| ------------------------------------------ |
| Total 12/64 (18.8%) |
| ------------------------------------------ |
| EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) |
| Copyright (R) National Semiconductor Corporation 1990,1991 |
| Chip diagram (DIP) |
| ._____ _____. |
| | \__/ | |
| | 1 20 | VCC |
| D7 | 2 19 | DQ |
| D6 | 3 18 | VPPON |
| D5 | 4 17 | VCCON |
| D4 | 5 16 | |
| D3 | 6 15 | RES |
| D2 | 7 14 | |
| D1 | 8 13 | DATA |
| D0 | 9 12 | CLOCK |
| GND | 10 11 | |
| |______________| |