MLABlibrarysvnkaklikMLAB_E8magsvn

Català-Valencià – Catalan中文 – Chinese (Simplified)中文 – Chinese (Traditional)Česky – CzechDansk – DanishNederlands – DutchEnglish – EnglishSuomi – FinnishFrançais – FrenchDeutsch – Germanעברית – Hebrewहिंदी – HindiMagyar – HungarianBahasa Indonesia – IndonesianItaliano – Italian日本語 – Japanese한국어 – KoreanМакедонски – Macedonianमराठी – MarathiNorsk – NorwegianPolski – PolishPortuguês – PortuguesePortuguês – Portuguese (Brazil)Русский – RussianSlovenčina – SlovakSlovenščina – SlovenianEspañol – SpanishSvenska – SwedishTürkçe – TurkishУкраїнська – UkrainianOëzbekcha – Uzbek

Compare Revisions

• This comparison shows the changes necessary to convert path

  → /dokumenty/ @ 1144

  → /dokumenty/ @ 1145

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 1144 → Rev 1145

/dokumenty/skolni/diplomka/description.tex
90,10 → 90,10
Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from the main local oscillator. This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose. FPGA may slightly affect the clock signal quality by adding a noise, but it has a negligible effect on the application where developed system will be used.
\secc Signal cable connectors
\label[signal-cables] \secc Signal cable connectors
\label[signal-cables]
Several widely used and commercially easily accessible differential connectors were considered to be use in our design.
\begitems

/dokumenty/skolni/diplomka/diplomka.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/dokumenty/skolni/diplomka/testing.tex
85,7 → 85,7
% doplnit schema skutecne pouziteho systemu
Despite of the schematic diagram proposed at beginning of system description....
Despite of the schematic diagram proposed at beginning of system description \ref[expected-block-schematic].
We have used two separate oscillators -- one oscillator drives encoded signal to ADCs still through FPGA based divider and the other one drives it to SDRX01B mixer.
The reason for this modification was an attempt to simplify the frequency tuning during the experiment. A single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA schema. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA scheme is changed. Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver.
We have used ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators.