| 1,10 → 1,10 |
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| \chap Testing construction |
| \chap Trial design |
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| Whole design of radioastronomy receiver digitalization unit is constructed for use in wide range of applications and tasks related to signal digitalisation from radioastronomy receivers. Illustrating problem for its use is signal digitalisation from multiple antenna arrays. And this design will become a part of MLAB Advanced Radio Astronomy System. |
| The whole design of radioastronomy receiver digitalization unit is constructed to be used in a wide range of applications and tasks related to digitalisation of signal from radioastronomy receivers. A good illustrating problem for its use is a signal digitalisation from multiple antenna arrays. This design will eventually become a part of MLAB Advanced Radio Astronomy System. |
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| \sec Required parameters |
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| Wide dynamical range and high 3 intercept point are desired. The receiver must accept wide dynamic signals because classic radioastronomy signal in typically weak signal covered by strong man made noise signal. |
| Wide dynamical range and high 3 intercept points are desired. The receiver must accept wide dynamic signals because a typical radioastronomy signal has a form of a weak signal covered by a strong man-made noise signal. |
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| \begitems |
| * Dynamical range better than 80 dB |
| 17,25 → 17,25 |
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| \sec Sampling frequency |
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| Sampling frequency is limited by technical constrains in testing construction design. This parameter is especially limited by sampling frequencies of analog to digital conversion chips accessible on market. Combination of required parameters -- dynamic range which needs 16bit at least and minimum sampling frequency of 1 MSPS, leads to high end ADC chips. Which does not support such low sampling frequencies at all. Its minimum sampling frequency is 5 MSPS. |
| Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market. Combination of the required parameters -- dynamic range which needs at least 16bit and a minimum sampling frequency of 1 MSPS, leads to high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5 MSPS. |
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| \sec System scalability |
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| For analog channels scalability special parameters of ADC modules were needed. ADC module ideally needs separate output for each I/Q channel. ADC module must have separate inputs for sampling and for data output clocks. This parameters allows conduction of relatively low digital data rates. And digital signal can be conducted on long wires. |
| For analog channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each I/Q channel in ACD module. ADC module must also have separate inputs for sampling and data output clocks. These parameters allow for conduction at relatively low digital data rates. Then the digital signal can be conducted even through long wires. |
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| Clock signal will be handled specially in this scalable design. Selected ADC chip guaranteed defined clock skew between sampling and data output clock. This allows taking data and frame clocks from first ADC module only. Other data and frame clocks from other ADC modules can be measured for diagnostic purposes. (Failure detection, jitter measurement etc.) |
| Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes. (Failure detection, jitter measurement etc.) |
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| This system concept allows scalability technically limited by number of differential signals on host side, and its computational power. There is another advantage of scalable data acquisition system -- economic reasons. Observatories or end user can pick choice how much money they are able to spent in radioastronomy receiver system. This option is especially useful for science sites without previous experience with radioastronomy observations. |
| This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power. There is another advantage of scalable data acquisition system -- economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations. |
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| \secc Differential signalling |
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| This concept of scalable design requires relatively long traces between ADC and digital unit which captures the data and performs computations. Distance of digital processing unit and analog to digital conversion unit has advantage in noise retention typically produced by digital circuits. Those digital circuits such as FPGA or other flip-flops block and traces usually works on high frequencies and emits wideband noise with relatively low power. In such case any distance increase between noise source and analog signal source increase S/N significantly. But this distance also brings problems with digital signal transmission between ADC and computational unit. But this obstruction should be resolved easier in free space than on board routing. The high quality differential signalling shielded cables should be used. This technology have two advantages on PCB signal routing. It can use two wire twisting for leak inductance suppression of signal path. And this twisted pair may be additionally shielded by uninterrupted metal foil. |
| The concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA or other flip-flops block and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such case any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time a long distance brings problems with the digital signal transmission between ADC and computational unit. This obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used. This technology have two advantages over PCB signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path. Moreover, the twisted pair may additionally be shielded by uninterrupted metal foil. |
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| \secc Phase matching |
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| For multiple antenna radioastronomy project, system phase stability is mandatory. It allows precise high resolution imaging of object. |
| For multiple antenna radioastronomy projects, system phase stability is mandatory. It allows precise high resolution imaging of objects. |
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| High phase stability in this scalable design is achieved by centralised frequency generation and distribution with multi-output LVPECL hubs. These hubs have equiphased outputs for multiple devices. |
| High phase stability in our scalable design is achieved by centralised frequency generation and distribution with multi-output LVPECL hubs, that have equiphased outputs for multiple devices. |
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| This design ensures that all devices have access to defined phase and known frequency. |
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| 46,10 → 46,10 |
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| \secc Frequency synthesis |
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| Centralised topology was used for frequency synthesis. One precise high frequency and low jitter digital oscillator was used and other working frequencies are delivered by division from it. This central oscillator has software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design was developed in parallel to this diploma thesis construction as related project, but it is not explicitly required by specification.} |
| This method was used in order to meet modern requirements on radioastronomy equipment, which needs precise frequency and phase stability on wide area for effective radioastronomy imaging. |
| We have used centralised topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used while other working frequencies have been derived by its division. This central oscillator has a software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by specification.} |
| This method has been used in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability on wide area for effective radioastronomy imaging. |
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| Every ADC module will be directly connected to CLKHUB02A module. This module takes sampling clock delevered by FPGA from main local oscillator. This signal should use high quality differential signaling cable -- SATA cable should be used for this purpose. |
| Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock delivered by FPGA from main local oscillator. This signal should use high quality differential signaling cable -- SATA cable should be used for this purpose. |
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| \secc Signal cable connectors |
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| 62,7 → 62,7 |
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| * SAS/miniSAS |
| \enditems |
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| MiniSAS connector was chosen as the best for use in connection multiple ADC modules. This miniSAS connector is compatible with existing SATA cabling system and aggregates multiple SATA cables to single connector this cable type is shown on image \ref[img-miniSAS-cable]. Translation between SATA and miniSAS is achieved by SAS to SATA adapter cable. This cable is used in servers to connecting SAS controller to multiple SATA hard disc in RAID systems thus is commercially available. |
| MiniSAS connector was chosen as the best to be used in connecting multiple ADC modules. The miniSAS connector is compatible with existing SATA cabling system and aggregates multiple SATA cables to a single connector this cable type is shown on image \ref[img-miniSAS-cable]. Translation between SATA and miniSAS is achieved by SAS to SATA adapter cable which is used in servers to connecting SAS controller to multiple SATA hard disc in RAID systems thus is commercially available. |
| One drawback is that miniSAS PCB connectors are manufactured in SMT versions only. But outer metal housing of connector is standard trough hole type. This mechanical design should degrade durability of this connector type. |
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| 245,4 → 245,4 |
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| \sec Possible future improvements |
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| Several ADC module imperfections such as useless separation of FRAME and DCO signal to two connectors should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest. |
| Several ADC module imperfections, such as useless separation of FRAME and DCO signal to two connectors, should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest. |