| 2,10 → 2,22 |
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| Special design of scalable data-aquisition system was proposed. This system has parameters |
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| \sec Possible future improvements |
| \sec Possible hardware improvements |
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| PCB design of used modules might need more precise high speed optimization of differential pairs. Improvement in high-speed routing allows possible use of fastest ADC from Linear Technology devices family. Use of faster ADCs even improve range of possible usage. |
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| \secc ADC modules weakness |
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| Several ADC module imperfections, such as useless separation of FRAME and DCO signal to two connectors, should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest. |
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| \sec Possible software improvements |
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| In future versions Xilibus interface should be swapped with an open-source alternative PCIe interfacing module or PCIe may be completely avoided. |
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| SPI configuration data read back should be implemented. |
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| \bibchap |
| \usebbl/c mybase |
| |