| 50,7 → 50,7 |
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| \secc Frequency synthesis |
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| We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used, while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilization.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis.} |
| We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO], while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis.} |
| We have used methods of frequency monitoring compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide scale for effective radioastronomy imaging. |
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| Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from main local oscillator. This signal should use high quality differential signaling cable -- we should use SATA cable for this purpose. |
| 103,7 → 103,7 |
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| * serial LVDS |
| \enditems |
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| Because it uses the smallest number of differential pairs, the choice fell on the serial LVDS format. Small number of differential pairs is an important parameter determining the construction complexity and reliability. \url{http://www.ti.com/lit/pdf/snaa110} |
| Because it uses the smallest number of differential pairs, the choice fell on the serial LVDS format. Small number of differential pairs is an important parameter determining the construction complexity and reliability\cite[serial-lvds]. |
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| An ultrasound AFE chip seems to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though - it is incapable of handling differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC). Because this IO has many ADC channels the scaling is possible only by a factor of 4 receivers (making 8 analogue channels). |
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| 270,7 → 270,7 |
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| \sec Basic interferometer station |
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| Interferometry station was selected as most basic setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematic of used setup is shown in image \ref[block-schematic]. Two ground-plane antennas were used and mounted outside of balcony at CTU building at location 50°4'36.102"N, 14°25'4.170"E. Antennas were equipped by LNA01A amplifiers. Coaxial cable length are matched for 5 meters. And antennas were isolated by common mode ferrite bead mounted on cable for minimize signal coupling between antennas. Evaluation system consists SDGPSDO local oscillator subsystem used for tunning local oscillator frequency. |
| Interferometry station was selected as most basic setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematic of used setup is shown in image \ref[block-schematic]. Two ground-plane antennas were used and mounted outside of balcony at CTU building at location 50$^\circ$4'36.102"N, 14 $^\circ$ 25'4.170" E. Antennas were equipped by LNA01A amplifiers. Coaxial cable length are matched for 5 meters. And antennas were isolated by common mode ferrite bead mounted on cable for minimize signal coupling between antennas. Evaluation system consists SDGPSDO local oscillator subsystem used for tuning local oscillator frequency. |
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| \midinsert |
| \clabel[block-schematic]{Receiver block schematic} |
| 309,7 → 309,7 |
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| In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than trial design. It should be compatible with MLAB which is further backward compatible with the existing or improved design of ADC modules. For a connection of this board to another adapter board with PCIe we expect a use of a host interface. |
| Thunderbolt technology standard was expected to be used in this PC to PCIe -> FPGA module. Thunderbolt chips are currently available on the market for reasonable prices. However, a problem lies in the accessibility to their specifications, as they are only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution. |
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| However, these systems and cables are still very expensive. Take (http://www.opalkelly.com/products/xem6110/) as an example, with its price tag reaching 995 USD at time of writing of thesis. |
| However, these systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing of thesis. |
| Therefore, a better solution probably needs to be found. |
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| \sec Parralella board computer |