MLABlibrarysvnkaklikMLAB_E8magsvn

Català-Valencià – Catalan中文 – Chinese (Simplified)中文 – Chinese (Traditional)Česky – CzechDansk – DanishNederlands – DutchEnglish – EnglishSuomi – FinnishFrançais – FrenchDeutsch – Germanעברית – Hebrewहिंदी – HindiMagyar – HungarianBahasa Indonesia – IndonesianItaliano – Italian日本語 – Japanese한국어 – KoreanМакедонски – Macedonianमराठी – MarathiNorsk – NorwegianPolski – PolishPortuguês – PortuguesePortuguês – Portuguese (Brazil)Русский – RussianSlovenčina – SlovakSlovenščina – SlovenianEspañol – SpanishSvenska – SwedishTürkçe – TurkishУкраїнська – UkrainianOëzbekcha – Uzbek

Compare Revisions

• This comparison shows the changes necessary to convert path

  → /dokumenty/skolni/diplomka/description.tex @ 1116

  → /dokumenty/skolni/diplomka/description.tex @ 1117

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 1116 → Rev 1117

/dokumenty/skolni/diplomka/description.tex
357,6 → 357,8
Parallella is new product from Adapteva, Inc. \cite[parallella-board], this small supercomputer have been in development almost two years and only testing series of boards have been produced until now (first single-board computers with 16-core Epiphany chip were shipped December 2013) \cite[parallella-board]. This board have near ideal parameters for signal processing (provides around 50 GFLOPS of computational power). The board is equipped by Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and 866 MHz operating frequency, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. Completely this board provides In addition of that this board consume only 3 Watts of power if both Zynq and Epiphany cores are running.
Main disadvantage of Parralella board is is unknown lead time and absence of SATA interface or other interface for data storage connection. Fast data storage interface would be useful and allows bulk processing of captured data. Then a result from data processing will be sent over the Ethernet interface to data storage server.
\midinsert
\clabel[img-parallella-board]{Parallella board overview}
\picw=15cm \cinspic ./img/ParallellaTopView31.png
363,11 → 365,8
\caption/f Top view on Parallella-16 board \cite[parallella16-board].
\endinsert
If Parallella board will be used a new ADC interface board should be designed. Interfacing module will use four PEC connectors mounted on bottom of Parallella board. This doughter module should have MLAB compatible design preferably constructed as separable module for every Parallella's PEC connectors.
If Parallella board will be used as radioastronomy data interface a new ADC interface module should be designed. Interfacing module will use four PEC connectors mounted on bottom of Parallella board. This doughter module should have MLAB compatible design and preferably constructed as separable modules for every Parallella's PEC connectors.
Main imperfections of Parallella board is unknown lead time and absence of onboard data
\sec GPU based computational system
A new GPU development board NVIDIA K1, shown in the following picture \ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have ideal parameters for signal processing for a relatively low price of 192 USD. Unfortunately, they are currently only in pre-order release stage (in April 2014).