| 17,7 → 17,7 |
|---|
| * Support for any number of receivers in range 1 to 8 |
| \enditems |
| |
| Now we analyzes several parameters more precisely. |
| Now we analyze several of the parameters in detail. |
| |
| \sec Sampling frequency |
| |
| 346,7 → 346,7 |
|---|
| |
| % doplnit schema zapojeni transformatoru. |
| |
| Used signal generator Agilent 33220A has not optimal parameters for this type of dynamic range measurement. Signal distortion and spurious levels are only -70 dBc according to Agilent datasheet \cite[33220A-generator]. Although, we measured ADC saturation voltage of 705.7 mV (generator output) in this setup due to impedance mismatch and uncalibrated measurement setup and 1V ADC range selected by sense pin. This is relatively high error, but main result from this measurement is FFT plot shown in image \ref[ADC1-FFT], which confirms $>$80 dB dynamic range at ADC module input. |
| The signal generator Agilent 33220A which we used does not have optimal parameters for this type of dynamic range measurement. Signal distortion and spurious levels are only -70 dBc according to Agilent datasheet \cite[33220A-generator]. We have managed to measure an ADC saturation voltage of 705.7 mV (generator output) with this setup, mostly due to an impedance mismatch and uncalibrated measurement setup, with 1V ADC range selected by sense pin. This is a relatively large error, but the main result of our measurement, seen as a FFT plot shown in image \ref[ADC1-FFT], confirms $>$80 dB dynamic range at ADC module input. |
| |
| \midinsert |
| \clabel[ADC1-FFT]{ADC1 sine test FFT} |
| 355,7 → 355,7 |
|---|
| \endinsert |
| |
| |
| Similar test we performed at ADC2 module. For ADC2 we have to use formula with a different constant \ref[ADC1-gain]. The ADC2 module has LT6600-2.5 amplifiers populated on it with gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances of used setup. |
| Similar test was performed at ADC2 module. For ADC2 we have to use formula with a different constant \ref[ADC1-gain]. The ADC2 module has LT6600-2.5 amplifiers populated on it with gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances of used setup. |
| |
| \label[ADC2-gain] |
| $$ |
| 404,9 → 404,9 |
|---|
| |
| % doplnit schema skutecne pouziteho systemu |
| |
| Despite of schematic diagram proposed on beginning of system description.... |
| Despite of the schematic diagram proposed at beginning of system description.... |
| We used two separate oscillators -- one oscillator drives encode signal to ADCs still through FPGA based divider and other one drives SDRX01B mixer. |
| Reason for this modification is simplification of frequency tuning during experiment. It is because single oscillator may be used only with proper setting of FPGA divider, this divider may be modified only by recompilation of FPGA code and loading/flashing new FPGA schema. Due to fact that FPGA was connected to PCI express and kernel drivers and hardware must be reinitialized, reboot of PC is required. Instead of this procedure, we set the FPGA divider to constant division of factor 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver. |
| The reason for this modification is a simplification of frequency tuning during the experiment. It is because a single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA schema. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA scheme is changed. Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver. |
| We use ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators. |
| |
| \midinsert |
| 418,10 → 418,10 |
|---|
| \midinsert |
| \clabel[phase-difference]{Phase difference} |
| \picw=10cm \cinspic ./img/screenshots/phase_difference.png |
| \caption/f Demonstration of phase difference between antennas. |
| \caption/f Demonstration of phase difference between antennae. |
| \endinsert |
| |
| For simplest demonstration of phase difference between antennas, we analyse part of signal by complex conjugate multiplication between channels. Result of this analysis can be seen on picture \ref[phase-difference]. Points of selected part of signal creates clear vector, which illustrates the presence of phase difference. |
| For the simplest demonstration of phase difference between antennae, we have analysed part of the signal by complex conjugate multiplication between channels. Results of this analysis can be seen in the following picture \ref[phase-difference]. Points of the selected part of signal create a clear vector, which illustrates the presence of the phase difference. |
| |
| |
| %\sec Simple passive Doppler radar |
| 428,27 → 428,27 |
|---|
| |
| %\sec Simple polarimeter station |
| |
| \chap Proposed final system |
| \chap Proposition of the final system |
| |
| Construction of a final system which is supposed to be employed for real radioastronomy observations will be described. This chapter is mainly a theoretical analysis of data handling systems. Realization of these ideas might be possible as a part of our future development after we fully evaluate and test the current trial design. |
| The construction of a final system, that is supposed to be employed for real radioastronomy observations will be described in this chapter. It is mainly a theoretical analysis of the data handling systems. Realization of the described ideas might be possible as a part of our future development after we fully evaluate and test the current trial design. |
| |
| The system requires proper handling of huge amounts of data and either huge and fast storage capacity is needed for store captured signal data, or enormous computational power is required for online data processing and filtering. Several hardware approach currently exist and are in use for data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially constructed ASICs are used for this task. |
| |
| \sec Custom design of FPGA board |
| |
| In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than trial design. It should be compatible with MLAB internal standards which is further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface. |
| In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than the trial design. It should be compatible with MLAB internal standards which is further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface. |
| Thunderbolt technology standard was expected to be used in this PC to PCIe module which further communicate with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as specification is only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need preserve standard PC as main computational platform. |
| |
| However, these PCI express external systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing of thesis. |
| Therefore, a better solution probably needs to be found. |
| |
| An interfacing problem will by probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to increased demand of embedded technologies, which requires high computation capacity, low power consumption and small size -- especially smart phones. Many of those ARM based systems has interesting parameters for signal processing. This facts makes Intel's ix86 architecture unattractive for future project. |
| An interface problem will by probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to an increased demand of embedded technologies, which require high computation capacity, low power consumption and small size -- especially smartphones. Many of those ARM based systems have interesting parameters of signal processing. These facts make Intel's ix86 architecture unattractive for future projects. |
| |
| \sec Parralella board computer |
| |
| Parallella is new product from Adapteva, Inc. \cite[parallella-board], this small supercomputer have been in development almost two years and only testing series of boards have been produced until now (first single-board computers with 16-core Epiphany chip were shipped December 2013) \cite[parallella-board]. This board have near ideal parameters for signal processing (provides around 50 GFLOPS of computational power). The board is equipped by Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and 866 MHz operating frequency, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition of that this board consume only 3 Watts of power if both Zynq and Epiphany cores are running. |
| Parallella is a new product created by Adapteva, Inc. \cite[parallella-board]. It represents a small supercomputer, that has been in development for almost two years with only testing series of boards produced until now (first single-board computers with 16-core Epiphany chip were shipped in December 2013) \cite[parallella-board]. The board has nearly ideal parameters for signal processing (as it provides around 50 GFLOPS of computational power). It is is equipped with Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and operating frequency of 866 MHz, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition to this, the board consumes only 3 Watts of power if both Zynq and Epiphany cores are running simultaniously. |
| |
| Main disadvantage of Parralella board is is unknown lead time and absence of SATA interface or other interface for data storage connection. Fast data storage interface would be useful and allows bulk processing of captured data. Then a result from data processing will be sent over the Ethernet interface to data storage server. |
| The main disadvantage of Parralella board is its unknown lead time and an absence of SATA interface or other interface suitable for data storage connection. Fast data storage interface would be useful and would allow bulk processing of captured data. Following that, the results of data processing may be sent over the Ethernet interface to data storage server. |
| |
| \midinsert |
| \clabel[img-parallella-board]{Parallella board overview} |
| 456,7 → 456,7 |
|---|
| \caption/f Top view on Parallella-16 board \cite[parallella16-board]. |
| \endinsert |
| |
| If Parallella board will be used as radioastronomy data interface a new ADC interface module should be designed. Interfacing module will use four PEC connectors mounted on bottom of Parallella board. This doughter module should have MLAB compatible design and preferably constructed as separable modules for every Parallella's PEC connectors. |
| If Parallella board will be used as a radioastronomy data interface, there would be a demand for new ADC interface module. The interface module will use four PEC connectors mounted on the bottom of the Parallella board. This daughter module should have MLAB compatible design and should preferably be constructed as separable modules for every Parallella's PEC connectors. |
| |
| \sec GPU based computational system |
| |
| 468,15 → 468,15 |
|---|
| \caption/f The NVIDIA Jetson TK1 Development Kit \url{https://developer.nvidia.com/jetson-tk1}. |
| \endinsert |
| |
| NVIDIA board is discrict by presence of PCI Experess connector. This connector should be used for FPGA connection, if we decide to use this development board in our radio astronomy digitalisation system. A new FPGA board with PCI Express direct PCB connector |
| NVIDIA board differs from other boards in its category by a presence of PCI Experess connector. If we decide to use this development board in our radio astronomy digitalisation system, the PCI express should be used for FPGA connection. A new FPGA board with PCI Express direct PCB connector |
| |
| % doplnit popis pripojeni FPGA desky s HDMI Kabelem. |
| |
| \sec Other ARM based computation systems |
| |
| Other embeded ARM based computers for example ODROID-XU, lack of suitable high speed interface. Theirs highest speed interface is USB 3.0 which has currently unsettled development support and needs commercial software tools for evaluation and testing. |
| Other embedded ARM based computers, for example ODROID-XU, lack a suitable high speed interface. Their highest speed interface is USB 3.0 which has currently unsettled development support and needs commercial software tools for evaluation and testing. |
| |
| |
| From summary analysis mentioned above the Parrallella board should be the best candidate for computational board in radioastronomy data aquisition system. Parralella board is optimised for high data flow processing. Parallella has not much memory to cache processing data but instead of this it has wide bandwidth data channels. Other boards provides much more computational power -- 300 GFLOPS in case of NVIDIA K1, but these boards are optimised for computational heavy tasks on limited amount of data. This is typical problem in computer graphics. But in our application we do not need such extreme computation power at data aquisition system level. |
| As result we should wait until Parallella becomes widely available. Then new ADCdual interfacing board should be designed ad prepared for use in new scalable radio astronomy data aquisition system. In meen time before suitable computing hardware become accessible. Required applications and algorithms should be optimised on proposed trial design with FPGA development board on standard PC host computer with PCI Express interface to development board. |
| From the summary analysis mentioned above, the Parrallella board should be a best candidate for computational board in radioastronomy data acquisition system, as it is optimised for high data flow processing. On one hand, Parrallella does not have much memory to cache the processing data but on the other hand it has wide bandwidth data channels instead. Other boards might provide much more computational power -- 300 GFLOPS in case of NVIDIA K1, but they are optimised for heavy computational tasks on limited amount of data which represents a typical problem in computer graphics. However, in our application we do not need such extreme computation power at data acquisition system level. |
| As a result we should presumably wait until Parallella becomes widely available. Following that, a new ADCdual interface board should be designed and prepared to be used in new scalable radio astronomy data acquisition system. In the meantime, before suitable computing hardware become accessible, the required applications and algorithms should be optimised using the proposed trial design. with FPGA development board on standard PC host computer with PCI Express interface to development board. |
| |