| 1,7 → 1,16 |
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| \chap Trial design |
| \chap Trial design implementation |
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| The whole design of radioastronomy receiver digitalization unit is constructed to be used in a wide range of applications and tasks related to digitalization of signal from radioastronomy receivers. A good illustrating problem for its use is a signal digitalisation from multiple antenna arrays. |
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| \midinsert |
| \clabel[expected-block-schematic]{Expected system block schematic} |
| \picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png } |
| \par\nobreak \vskip\wd0 \vskip-\ht0 |
| \centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore} |
| \caption/f Expected realisation of signal digitalisation unit. |
| \endinsert |
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| \sec Required parameters |
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| We require following technical parameter, to supersede existing digitalization units solutions. |
| 113,9 → 122,9 |
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| \midinsert |
| \clabel[adcdual-preview]{Preview of designed ADCdual PCB} |
| \picw=10cm \cinspic ./img/ADCdual_Top.png |
| \picw=10cm \cinspic ./img/ADCdual_Bottom.png |
| \caption/f Modelled previews of designed and realised PCB of ADCdual01A modules. Differential pairs routing are clearly visible. |
| \picw=10cm \cinspic ./img/ADCdual01A_Top_Big.JPG |
| \picw=10cm \cinspic ./img/ADCdual01A_Bottom_Big.JPG |
| \caption/f Realised PCB of ADCdual01A modules. Differential pairs routing are clearly visible. |
| \endinsert |
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| \secc ADC selection |
| 185,9 → 194,9 |
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| \secc ADC modules interface |
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| \midinsert |
| \picw=10cm \cinspic ./img/FMC2DIFF_top.png |
| \picw=10cm \cinspic ./img/FMC2DIFF_Bottom.png |
| \caption/f Modelled prewievs of designed and realised PCB of FMC2DIFF01A module. |
| \picw=10cm \cinspic ./img/FMC2DIFF_Top_Big.JPG |
| \picw=10cm \cinspic ./img/FMC2DIFF_Bottom_Big.JPG |
| \caption/f Realised PCB of FMC2DIFF01A module. |
| \endinsert |
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| Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter expects the presence of FMC LPC connector on host side and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions]. |
| 321,11 → 330,11 |
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| The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. Signal is grabbed to file with exactly the same format, as it is described in table \ref[xillybus-interface]. |
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| \sec Achieved parameters |
| \chap Achieved parameters |
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| Trial design construction was tested for proper handling of sampling rates in range of 5 MSPS to 15 MSPS it should work above this limit. System works on i7 8 cores computer with Ubuntu 12.04 LTS operating system. Data recording of input signal is impossible above sampling rates around 7 MSPS due to bottleneck at HDD speed limits, it should be resolved by use of SSD disk drive. But it is not tested in our setup. |
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| \secc ADC module parameters |
| \sec Measured parameters |
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| Two prototypes of ADC modules were assembled and tested. The first prototype, labeled ADC1, has LTC2190 ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which give it an ability of an internal attenuation of the input signal. The value of this attenuation $A$ is described by the following formula \ref[ADC1-gain] |
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| 342,9 → 351,13 |
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| \enditems |
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| We have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply that $A = 0.815$. That value of A is further confirmed by the measurement. |
| In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator. Circuit diagram of used transformer circuit is shown in picture and circuit realization in photograph \ref[SMA2SATA-nest]. |
| In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator. Circuit diagram of used transformer circuit is shown in picture \ref[balun-circuit] and circuit realization in photograph \ref[SMA2SATA-nest]. |
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| % doplnit schema zapojeni transformatoru. |
| \midinsert |
| \clabel[balun-circuit]{Balun transformer circuit} |
| \picw=10cm \cinspic ./img/SMA2SATA.pdf |
| \caption/f Simplified balun transformer circuit diagram. |
| \endinsert |
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| The signal generator Agilent 33220A which we used does not have optimal parameters for this type of dynamic range measurement. Signal distortion and spurious levels are only -70 dBc according to Agilent datasheet \cite[33220A-generator]. We have managed to measure an ADC saturation voltage of 705.7 mV (generator output) with this setup, mostly due to an impedance mismatch and uncalibrated measurement setup, with 1V ADC range selected by sense pin. This is a relatively large error, but the main result of our measurement, seen as a FFT plot shown in image \ref[ADC1-FFT], confirms $>$80 dB dynamic range at ADC module input. |
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| 385,11 → 398,11 |
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| \chap Example of usage |
| \sec Example of usage |
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| For additional validation of system characteristics a receiver setup has been constructed. |
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| \sec Basic interferometric station |
| \secc Basic interferometric station |
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| Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N, 14$^\circ$ 25' 4.170'' E. |
| Antennae were equipped by LNA01A amplifiers. All coaxial cables have the same length of 5 meters. Antennae were isolated by common mode ferrite bead mounted on cable to minimise the signal coupling between antennas. Evaluation system consists of SDGPSDO local oscillator subsystem used to tune the local oscillator frequency. |
| 396,7 → 409,7 |
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| \midinsert |
| \clabel[block-schematic]{Receiver block schematic} |
| \picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png } |
| \picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Basic_interferometer.png } |
| \par\nobreak \vskip\wd0 \vskip-\ht0 |
| \centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore} |
| \caption/f Complete receiver block schematic of dual antenna interferometric station. |
| 424,10 → 437,15 |
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| For the simplest demonstration of phase difference between antennae, we have analysed part of the signal by complex conjugate multiplication between channels. Results of this analysis can be seen in the following picture \ref[phase-difference]. Points of the selected part of signal create a clear vector, which illustrates the presence of the phase difference. |
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| %\sec Simple passive Doppler radar |
| \secc Simple passive Doppler radar |
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| %\sec Simple polarimeter station |
| % doplnit popis |
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| \secc Simple polarimeter station |
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| % doplnit popis |
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| \chap Proposition of the final system |
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| The construction of a final system, that is supposed to be employed for real radioastronomy observations will be described in this chapter. It is mainly a theoretical analysis of the data handling systems. Realization of the described ideas might be possible as a part of our future development after we fully evaluate and test the current trial design. |
| 465,7 → 483,7 |
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| \midinsert |
| \clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit} |
| \picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg |
| \caption/f The NVIDIA Jetson TK1 Development Kit \url{https://developer.nvidia.com/jetson-tk1}. |
| \caption/f The NVIDIA Jetson TK1 Development Kit \cite[nvidia-k1]. |
| \endinsert |
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| NVIDIA board differs from other boards in its category by a presence of PCI Experess connector. If we decide to use this development board in our radio astronomy digitalisation system, the PCI express should be used for FPGA connection. A new FPGA board with PCI Express direct PCB connector |