| 14,7 → 14,7 |
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| \sec Required parameters |
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| We require the following technical parameters, to supersede existing digitalization units solutions. |
| Primarily, we need wide a dynamical range and high IP3. The receiver must accept wide dynamic signals because a typical radioastronomical signal has a form of a weak signal covered by a strong man-made noise or other undesired noises as lighting, Sun emissions etc. |
| Primarily, we need wide a dynamical range and high IP3. \glos{IP3}{Third-order intercept point} The receiver must accept wide dynamic signals because a typical radioastronomical signal has a form of a weak signal covered by a strong man-made noise or other undesired noises as lighting, Sun emissions etc. |
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| Summary of other additional required parameters follows |
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| 30,28 → 30,28 |
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| \sec Sampling frequency |
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| Sampling frequency is not limited by the technical constrains in the trial version. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market and interface bandwidth. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1$\ $MSPS leads to the need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5$\ $MSPS. |
| Sampling frequency is not limited by the technical constrains in the trial version. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market and interface bandwidth. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1$\ $MSPS \glos{MSPS}{Mega-Samples Per Second} leads to the need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5$\ $MSPS. |
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| We calculated a minimum data bandwidth data rate for eight receivers, 2 bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/s. Such data rate is at the limit of the actual writing speed of classical HDD and it is almost double the real bandwidth of USB 2.0 interface. As a result of these facts we must use faster interface. Faster interface is especially needed in cases where we require faster sampling rates than ADC's minimal 5$\ $MSPS sample rate. |
| The most perspective interface for use in our type of application is USB 3.0 or PCI Express interface. However, USB 3.0 is a relatively new technology without good development tools currently available. We have used PCI Express interface as the simplest and the most reliable solution. |
| We calculated a minimum data bandwidth data rate for eight receivers, 2 bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/s. Such data rate is at the limit of the actual writing speed of classical HDD \glos{HDD}{Hard disk drive} and it is almost double the real bandwidth of USB 2.0 \glos{USB 2.0}{Universal Serial Bus version 2.0} interface. As a result of these facts we must use faster interface. Faster interface is especially needed in cases where we require faster sampling rates than ADC's minimal 5$\ $MSPS sample rate. |
| The most perspective interface for use in our type of application is USB 3.0 or PCI Express interface. However, USB 3.0 is a relatively new technology without good development tools currently available. We have used PCI Express \glos{PCI Express}{Peripheral Component Interconnect Express} interface as the simplest and the most reliable solution. |
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| \sec System scalability |
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| For analogue channels' scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each analogue channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow for conduction at relatively low digital data rates. As a result, the digital signal can be conducted even through long wires. Modular concept allows a separation from central logical unit which supports optimization of number analogue channels. |
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| Clock and data signals will be then handled distinctively in our modular scalable design. Selected ADC chips are guaranteed to have defined clock skew between the sampling and data output clocks. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.), but these redundant signals are not used for data sampling. If more robustness is required in the final application, DCO and FR signals may be collected from other modules and routed through an voting logic which will correct possible signal defects. |
| Clock and data signals will be then handled distinctively in our modular scalable design. Selected ADC chips are guaranteed to have defined clock skew between the sampling and data output clocks. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.), but these redundant signals are not used for data sampling. If more robustness is required in the final application, DCO \glos{DCO}{Data Clock Output} and FR signals may be collected from other modules and routed through an voting logic which will correct possible signal defects. |
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| This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power. There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations. |
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| \secc Differential signalling |
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| The above mentioned concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA, Ethernet or other flip-flops blocks and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such cases any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time, a long distance brings problems with the digital signal transmission between ADC and computational unit. But this obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used, such as massively produced and cheap SATA cables. This technology has two advantages over PCB signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path and second, the twisted pair may additionally be shielded by uninterrupted metal foil. |
| The above mentioned concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA \glos{FPGA}{Field-programmable gate array}, Ethernet or other flip-flops blocks and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such cases any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time, a long distance brings problems with the digital signal transmission between ADC and computational unit. But this obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used, such as massively produced and cheap SATA \glos{SATA}{Serial ATA} \glos{ATA}{AT Attachment} cables. This technology has two advantages over PCB \glos{PCB}{printed circuit board} signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path and second, the twisted pair may additionally be shielded by uninterrupted metal foil. |
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| \secc Phase matching |
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| For multiple antenna radioastronomy projects, system phase stability is a mandatory condition. It allows a precise, high resolution imaging of objects, increases signal to noise ratios in several observation methods and allows the use of advanced algorithms for signal processing. |
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| High phase stability in our scalable design is achieved through centralized frequency generation and distribution with multi-output LVPECL hubs (CLKHUB02A), that have equiphased outputs for multiple devices. LVPECL logic is used on every system critical clock signal distribution hub. LVPECL logic has an advantage over LVDS in signal integrity robustness. LVPECL uses higher logical levels and higher signalling currents. Power consumption of LVPECL logic is nearly constant over the operating frequency range due to the use of bipolar transistors. This minimizes voltage glitches which are typical for CMOS logic. One drawback of its parameters is a high power consumption of LVPECL logic which easily reaches tens of milliamperes per device. |
| High phase stability in our scalable design is achieved through centralized frequency generation and distribution with multi-output LVPECL \glos{LVPECL}{Low Voltage Emitter-coupled logic} hubs (CLKHUB02A), that have equiphased outputs for multiple devices. LVPECL logic is used on every system critical clock signal distribution hub. LVPECL logic has an advantage over LVDS \glos{LVDS}{Low-voltage differential signaling} in signal integrity robustness. LVPECL uses higher logical levels and higher signalling currents. Power consumption of LVPECL logic is nearly constant over the operating frequency range due to the use of bipolar transistors. This minimizes voltage glitches which are typical for CMOS \glos{CMOS}{Complementary metal–oxide–semiconductor } logic. One drawback of its parameters is a high power consumption of LVPECL logic which easily reaches tens of milliamperes per device. |
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| This design ensures that all system devices have access to the defined phase and known frequency. |
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| 61,10 → 61,10 |
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| \secc Frequency synthesis |
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| We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO], while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the thesis itself and thus it is described in a separate document} |
| We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO], while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS \glos{GPS}{Global Positioning System} disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the thesis itself and thus it is described in a separate document} |
| We have used new methods of software frequency monitoring and compensation in order to meet modern requirements on radioastronomy equipment which need precise frequency and phase stability over a wide baseline scales for effective radioastronomy imaging. |
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| The GPSDO device consists of Si570 chip with LVPECL output. Phase jitter of GPSDO is determined mainly by Si570 phase noise. Parameters of the Si570 are summarized in the following table \ref[LO-noise] (source \cite[si570-chip] ). |
| The GPSDO device consists of Si570 chip with LVPECL output. Phase jitter of GPSDO \glos{GPSDO}{GPS disciplined oscillator} is determined mainly by Si570 phase noise. Parameters of the Si570 are summarized in the following table \ref[LO-noise] (source \cite[si570-chip] ). |
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| The GPSDO design, that is included in data acquisition system, has special feature -- it generates time marks for a precise time-stamping of the received signal. Timestamps are created by disabling the local oscillator's outputs, connected to SDRX01B receivers, for 100 us. As result, a rectangular click in the ADC input signal is created which appears as a horizontal line in spectrogram. |
| Timestamps should be seen in image \ref[meteor-reflection] (above and below the meteor reflection). |
| 463,7 → 463,7 |
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| \sec Parralella board computer |
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| Parallella is a new product created by Adapteva, Inc. \cite[parallella-board]. It represents a small supercomputer, that has been in development for almost two years with only testing series of boards produced until now (first single-board computers with 16-core Epiphany chip were shipped in December 2013) \cite[parallella-board]. The board has nearly ideal parameters for signal processing (as it provides around 50 GFLOPS of computational power). It is is equipped with Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and operating frequency of 866 MHz, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition to this, the board consumes only 3 Watts of power if both Zynq and Epiphany cores are running simultaniously. |
| Parallella is a new product created by Adapteva, Inc. \cite[parallella-board]. It represents a small supercomputer, that has been in development for almost two years with only testing series of boards produced until now (first single-board computers with 16-core Epiphany chip were shipped in December 2013) \cite[parallella-board]. The board has nearly ideal parameters for signal processing (as it provides around 50 GFLOPS of computational power). It is is equipped with Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and operating frequency of 866 MHz, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition to this, the board consumes only 3 Watts of power if both Zynq and Epiphany cores are running simultaniously. |
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| The main disadvantage of Parralella board is its unknown lead time and an absence of SATA interface or other interface suitable for data storage connection. Fast data storage interface would be useful and would allow bulk processing of captured data. Following that, the results of data processing may be sent over the Ethernet interface to data storage server. |
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