MLABlibrarysvnkaklikMLAB_E8magsvn

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/dokumenty/skolni/diplomka/description.tex
90,10 → 90,10
Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from the main local oscillator. This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose. FPGA may slightly affect the clock signal quality by adding a noise, but it has a negligible effect on the application where developed system will be used.
\secc Signal cable connectors
\label[signal-cables] \secc Signal cable connectors
\label[signal-cables]
Several widely used and commercially easily accessible differential connectors were considered to be use in our design.
\begitems