MLABlibrarysvnkaklikMLAB_E8magsvn

Català-Valencià – Catalan中文 – Chinese (Simplified)中文 – Chinese (Traditional)Česky – CzechDansk – DanishNederlands – DutchEnglish – EnglishSuomi – FinnishFrançais – FrenchDeutsch – Germanעברית – Hebrewहिंदी – HindiMagyar – HungarianBahasa Indonesia – IndonesianItaliano – Italian日本語 – Japanese한국어 – KoreanМакедонски – Macedonianमराठी – MarathiNorsk – NorwegianPolski – PolishPortuguês – PortuguesePortuguês – Portuguese (Brazil)Русский – RussianSlovenčina – SlovakSlovenščina – SlovenianEspañol – SpanishSvenska – SwedishTürkçe – TurkishУкраїнська – UkrainianOëzbekcha – Uzbek

Compare Revisions

• This comparison shows the changes necessary to convert path

  → /dokumenty/skolni/diplomka/description.tex @ 1159

  → /dokumenty/skolni/diplomka/description.tex @ 1162

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 1159 → Rev 1162

/dokumenty/skolni/diplomka/description.tex
2,13 → 2,6
The whole design of the radioastronomic receiver digitization unit is meant to be used in a wide range of applications and tasks related to digitization of a signal. A good illustrating problem for its use is the signal digitization from multiple antenna arrays. Design and implementation of the system is presented in this chapter.
\midinsert
\clabel[expected-block-schematic]{Expected system block schematic}
\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png }
\par\nobreak \vskip\wd0 \vskip-\ht0
\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}
\caption/f Expected realization of signal digitalisation unit.
\endinsert
\sec Required parameters
58,8 → 51,19
\sec System description
This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board], available at the workplace. This FPGA parameters are more than sufficient of what we need for the fast data acquisition system being developed.
This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board], available at the workplace. This FPGA parameters are more than sufficient of what we need for the fast data acquisition system being developed. Expected system configuration is shown in Figure~\ref[expected-block-schematic]. The system consist antennas equipped by
%% dopsat celkovy popis systemu.
\midinsert
\clabel[expected-block-schematic]{Expected system block schematic}
\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png }
\par\nobreak \vskip\wd0 \vskip-\ht0
\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}
\caption/f Expected realization of signal digitalisation unit.
\endinsert
\secc Frequency synthesis
We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator (GPSDO\glos{GPSDO}{GPS disciplined oscillator}) has been used \cite[MLAB-GPSDO]. The other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS\glos{GPS}{Global Positioning System} disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma project as a related project, but it is not explicitly required by the thesis itself and thus it is described in a separate document.}