MLABlibrarysvnkaklikMLAB_E8magsvn

Català-Valencià – Catalan中文 – Chinese (Simplified)中文 – Chinese (Traditional)Česky – CzechDansk – DanishNederlands – DutchEnglish – EnglishSuomi – FinnishFrançais – FrenchDeutsch – Germanעברית – Hebrewहिंदी – HindiMagyar – HungarianBahasa Indonesia – IndonesianItaliano – Italian日本語 – Japanese한국어 – KoreanМакедонски – Macedonianमराठी – MarathiNorsk – NorwegianPolski – PolishPortuguês – PortuguesePortuguês – Portuguese (Brazil)Русский – RussianSlovenčina – SlovakSlovenščina – SlovenianEspañol – SpanishSvenska – SwedishTürkçe – TurkishУкраїнська – UkrainianOëzbekcha – Uzbek

Compare Revisions

• This comparison shows the changes necessary to convert path

  → /dokumenty/skolni/diplomka/description.tex @ 1162

  → /dokumenty/skolni/diplomka/description.tex @ 1166

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 1162 → Rev 1166

/dokumenty/skolni/diplomka/description.tex
12,7 → 12,7
The summary of other additional required parameters:
%
\begitems
* Dynamic range better than 80 dB, see section \ref[dynamic-range-theory] for the explanation.
* Dynamic range better than 80 dB, see Section \ref[dynamic-range-theory] for the explanation.
* Phase stability between channels.
* Low noise (all types).
* Sampling jitter better than 100 metres.
51,7 → 51,7
\sec System description
This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board], available at the workplace. This FPGA parameters are more than sufficient of what we need for the fast data acquisition system being developed. Expected system configuration is shown in Figure~\ref[expected-block-schematic]. The system consist antennas equipped by
This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board], available at the workplace. This FPGA parameters are more than sufficient of what we need for the fast data acquisition system being developed. Expected system configuration is shown in Figure~\ref[expected-block-schematic]. The system consist antennas equipped by
%% dopsat celkovy popis systemu.
139,8 → 139,7
If we add a requirement of a separate output for every analog channel and a 16bit depth, we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these criteria. We have summarized those ADCs in Table~\ref[ADC-types].
\midinsert
\typosize[9/11] \def\t
abiteml{ }\let\tabitemr=\tabiteml
\typosize[9/11] \def\tabiteml{ }\let\tabitemr=\tabiteml
\clabel[ADC-types]{Available ADC types}
\ctable{lccccccc}{
\hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr
207,7 → 206,7
The SY55857L is a fully differential, a high-speed dual translator optimized for accepting any logic standard from the single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is guaranteed for speeds up to 2.5Gbps (2.5GHz toggle frequency). The SY55857L does not internally terminate its inputs, as different interfacing standards have different termination requirements\cite[SY55857L-chip].
Inputs of both used chips are terminated accordingly to the used logic. The LVDS input is terminated differentially by 100~$\Omega$ resistor between the positive and the negative inputs. PECL input is terminated by Thevenin resistor network. Thevenin termination method was selected as optimal one, due to the absence of a proper power voltage (1.3 V) for direct termination by 50~$\Omega$ resistors. Termination on FPGA side is realized directly by settings the proper digital logic type on input pins.
Inputs of both used chips are terminated accordingly to the used logic. The LVDS input is terminated differentially by 100~$\Omega$ resistor between the positive and the negative inputs. PECL input is terminated by Thevenin resistor network. Thevenin termination method was selected as optimal one, due to the absence of a proper power voltage (1.3~V) for the direct termination by 50~$\Omega$ resistors. Termination on FPGA side is realized directly by settings the proper digital logic type on input pins.
\midinsert