| 1,9 → 1,20 |
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| \chap Testing construction |
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| Whole design of radioastronomy receiver digitalization unit shoud be constructed for the most universal application in signal digitalisation from radioastronomy receivers. Ilustrating problem for its use is signal digitalisation from multiple antenna arrays. This design will be used as part of MLAB Advanced Radio Astronomy System. |
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| \sec Required parameters |
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| Wide dynamical range and high 3 intercept point are desired. The receiver must accept wide dynamic signals because classic radioastronomy signal in typically weak signal covered by strong man made noise signal. |
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| \begitems |
| * Dynamical range better than 80 dB |
| * Phase stability between channels |
| * Noise (all types) |
| * Sampling jitter better than 100 metres |
| \enditems |
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| \sec Sampling frequency |
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| Sampling frequency is limited by technical constrains in testing construction design. This parameter is especially limited by sampling frequencies of analog to digital conversion chips accessible on market. Combination of required parameters -- dynamic range which needs 16bit at least and minimum sampling frequency of 1 MSPS, leads to high end ADC chips. Which does not support such low sampling frequencies at all. Its minimum sampling frequency is 5 MSPS. |
| 37,6 → 48,8 |
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| Centralised topology was used for frequency synthesis. One precise high frequency and low jitter digital oscillator was used and other working frequencies are delivered by division from it. This central oscillator has software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design was developed in parallel to this diploma thesis construction as related project, but it is not explicitly required by specification.} |
| This method was used in order to meet modern requirements on radioastronomy equipment, which needs precise frequency and phase stability on wide area for effective radioastronomy imaging. |
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| Every ADC module will be directly connected to CLKHUB02A module. This module takes sampling clock delevered by FPGA from main local oscillator. This signal should use high quality differential signaling cable -- SATA cable should be used for this purpose. |
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| \secc Signal connectors |
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| 49,19 → 62,56 |
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| * SAS/miniSAS |
| \enditems |
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| MiniSAS connector was chosen as the best for use in connection multiple ADC modules. This miniSAS connector is compatible with existing SATA cabling system. Translation between SATA and miniSAS is achieved by SAS to SATA adapter cable. This cable is used in servers to connecting SAS controller to multiple SATA hard disc in RAID systems. |
| MiniSAS connector was chosen as the best for use in connection multiple ADC modules. This miniSAS connector is compatible with existing SATA cabling system and agregates multiple SATA cables to single connector. Translation between SATA and miniSAS is achieved by SAS to SATA adapter cable. This cable is used in servers to connecting SAS controller to multiple SATA hard disc in RAID systems thus is commercially available. |
| One drawback is that miniSAS PCB connectors are mainufactured in SMT versions only. But outer metal housing of connector is standard trough hole type. This mechannical design should degrade durability of this connector type. |
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| \secc Design of ADC modules |
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| This modules have MLAB standard construction with four mounting holes in corner aligned in defined raster. |
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| Data serial data output of ADC module should be connected directly to FPGA for basic primary signal processing. Used ADC chip has selectable bit width of data output bus thus output SATA connectors has signals arranged to contain a single bit from every ADC channel. This signal concept enables selection of proper bus bitwidth according to sampling rate. (Higher bus bitwidth downgrades signaling speed and vice versa.) |
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| For connection of this signaling layout, miniSAS to multiple SATA cable should be used. |
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| For PCB layout KiCAD design suite was used. Used version has the CERN Push \& Shove routing capability integrated but was slightly unstable and sometimes falls on exception during routing. Design must be often saved due to this stability issues. But Open-source KiCAD works well compared to commercial solutions as MentorGraphics PADS or Cadence Orcad. And much better than widely used Eagle software. |
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| New PCB footprints must be designed for FMC, SATA a and miniSAS connectors. These new footprints were committed to KiCAD github library repository. They are now publicly accessible from official KiCAD repository at GitHub. |
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| New PCB footprints have been designed for FMC, SATA a and miniSAS connectors. These new footprints were committed to KiCAD github library repository. And they are now publicly accessible from official KiCAD repository at GitHub. |
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| \secc ADC selection |
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| Several ADC signaling formats currently exist for communication with FPGA. |
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| \begitems |
| * DDR LVDS |
| * JEDEC 204B |
| * JESD204A |
| * Paralel LVDS |
| * Serdes |
| * serial LVDS |
| \enditems |
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| Serial LVDS has been selected because uses lowest number of differencial pairs. This parameter is mandatory for construction complexity and reliability. \url{http://www.ti.com/lit/pdf/snaa110} |
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| An ultrasound AFE chips should be ideal for this purpose -- this chips has front-end amplifiers and filters integrated. But theirs drawback is incapability of handling differential input signal and relatively low dynamic range (consists 12bit ADC). This IO has many ADC channels thus scalling are possible in factor of 4 receivers (8 analog channels). |
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| If we reduce range of usable chips by requirement of separate output for every analog channel and 16bit deph. Only several ADCs currently exists. |
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| \begitems |
| *[[http://www.linear.com/product/LTC2271|LTC2271]] |
| *[[http://www.linear.com/product/LTC2191|LTC2190-2195]]. |
| \enditems |
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| All parts in this category are compatible with one board layout. |
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| \secc ADC modules interface |
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| All two ADCdual01A modules was connected to FPGA ML605 board trough FMC2DIFF01A adapter board. Construction of this adapter module suppose FMC LPC connector. And this board is not MLAB compatible design. But this board is designed to meet VITA 57 standard specification for boards which uses zone 1 and zone 3. |
| This specification guarantee compatibility with others FPGA board which has FMC LPC connector for mezzane cards. Schematic diagram of this adapter board is included in appendix. |
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| Primary purpose of this PCB is to enable connection of ADC modules from space excluded from PC case. (In PC box analog circuits cannot be realised without using of massive RFI mitigation techniques). |
| Differential signaling connectors should be used for conducting digital signal over relatively long cable. Signalintegrity sensitive links (clocks) are equiped by output driver and translator to LVPECL logic for better signal transmission quality. |
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| \midinsert |
| \picw=10cm \cinspic ./img/ML605-board.jpg |
| \caption/f Used FPGA ML605 development board. |