| 7,22 → 7,22 |
|---|
| \Xpage{-6} |
| \Xpage{1} |
| \Xchap{1}{Introduction }{1} |
| \Xsec{1.1}{Modern Radio astronomy receiver }{1} |
| \Xsecc{1.1.1}{Observation types }{1} |
| \Xsec{1.1}{Current radioastronomy problems }{1} |
| \Xpage{2} |
| \Xsec{1.2}{Requirements }{2} |
| \Xsecc{1.2.1}{Sensitivity and noise number }{2} |
| \Xsecc{1.2.2}{Dynamic range }{2} |
| \Xsecc{1.2.3}{Bandwidth }{2} |
| \Xsec{1.3}{Current radioastronomy problems }{2} |
| \Xsec{1.2}{Modern Radio astronomy receiver }{2} |
| \Xpage{3} |
| \Xchap{2}{Testing construction }{3} |
| \Xsec{2.1}{Required parameters }{3} |
| \Xsec{2.2}{Sampling frequency }{3} |
| \Xsecc{1.2.1}{Observation types }{3} |
| \Xsec{1.3}{Required receiver parameters }{3} |
| \Xsecc{1.3.1}{Sensitivity and noise number }{3} |
| \Xsecc{1.3.2}{Dynamic range }{3} |
| \Xsecc{1.3.3}{Bandwidth }{3} |
| \Xpage{4} |
| \Xchap{2}{Testing construction }{4} |
| \Xsec{2.1}{Required parameters }{4} |
| \Xsec{2.2}{Sampling frequency }{4} |
| \Xsec{2.3}{System scalability }{4} |
| \Xsecc{2.3.1}{Differential signalling }{4} |
| \Xpage{5} |
| \Xsecc{2.3.1}{Differential signalling }{5} |
| \Xsecc{2.3.2}{Phase matching }{5} |
| \Xsec{2.4}{System description }{5} |
| \Xsecc{2.4.1}{Frequency synthesis }{5} |
| 32,37 → 32,36 |
|---|
| \Xfig{img-miniSAS-cable}{2.1}{Used miniSAS cable} |
| \Xlabel{img-miniSAS-cable}{2.1} |
| \Xsecc{2.4.3}{Signal integrity requirements }{6} |
| \Xsecc{2.4.4}{Design of ADC modules }{6} |
| \Xpage{7} |
| \Xsecc{2.4.4}{Design of ADC modules }{7} |
| \Xsecc{2.4.5}{ADC selection }{7} |
| \Xpage{8} |
| \Xtab{ADC-types}{2.1}{Available ADC types} |
| \Xlabel{ADC-types}{2.1} |
| \Xpage{8} |
| \Xsecc{2.4.6}{ADC modules interface }{8} |
| \Xsecc{2.4.7}{Output data format }{8} |
| \Xsec{2.5}{Achieved parameters }{8} |
| \Xpage{9} |
| \Xsecc{2.4.7}{Output data format }{9} |
| \Xsec{2.5}{Achieved parameters }{9} |
| \Xsecc{2.5.1}{Data reading and recording }{9} |
| \Xsecc{2.5.2}{ADC module parameters }{9} |
| \Xpage{10} |
| \Xsecc{2.5.1}{Data reading and recording }{10} |
| \Xsecc{2.5.2}{ADC module parameters }{10} |
| \Xpage{11} |
| \Xpage{12} |
| \Xchap{3}{Proposed final system }{12} |
| \Xsec{3.1}{Custom design of FPGA board }{12} |
| \Xsec{3.2}{Parralella board computer }{12} |
| \Xsec{3.3}{GPU based computational system }{12} |
| \Xpage{13} |
| \Xchap{3}{Proposed final system }{13} |
| \Xsec{3.1}{Custom design of FPGA board }{13} |
| \Xsec{3.2}{Parralella board computer }{13} |
| \Xpage{14} |
| \Xsec{3.3}{GPU based computational system }{14} |
| \Xfig{img-NVIDIA-K1}{3.1}{NVIDIA Jetson TK1 Development Kit} |
| \Xlabel{img-NVIDIA-K1}{3.1} |
| \Xpage{14} |
| \Xchap{4}{Conclusion }{14} |
| \Xsec{4.1}{Possible future improvements }{14} |
| \Xpage{15} |
| \Xchap{4}{Conclusion }{15} |
| \Xsec{4.1}{Possible future improvements }{15} |
| \Xchap{A}{Circuit diagram of ADCdual01A module }{15} |
| \Xpage{16} |
| \Xchap{B}{Circuit diagram of FMC2DIFF module }{16} |
| \Xpage{17} |
| \Xchap{A}{Circuit diagram of ADCdual01A module }{17} |
| \Xpage{18} |
| \Xchap{B}{Circuit diagram of FMC2DIFF module }{18} |
| \Xpage{19} |
| \Xpage{20} |
| \Xpage{21} |
| \Xpage{22} |