| 17,7 → 17,7 |
|---|
| \Xsecc{1.3.2}{Dynamic range }{3} |
| \Xsecc{1.3.3}{Bandwidth }{3} |
| \Xpage{4} |
| \Xchap{2}{Testing construction }{4} |
| \Xchap{2}{Trial design }{4} |
| \Xsec{2.1}{Required parameters }{4} |
| \Xsec{2.2}{Sampling frequency }{4} |
| \Xsec{2.3}{System scalability }{4} |
| 27,8 → 27,8 |
|---|
| \Xsec{2.4}{System description }{5} |
| \Xsecc{2.4.1}{Frequency synthesis }{5} |
| \Xfnote |
| \Xsecc{2.4.2}{Signal cable connectors }{5} |
| \Xpage{6} |
| \Xsecc{2.4.2}{Signal cable connectors }{6} |
| \Xfig{img-miniSAS-cable}{2.1}{Used miniSAS cable} |
| \Xlabel{img-miniSAS-cable}{2.1} |
| \Xsecc{2.4.3}{Signal integrity requirements }{6} |
| 40,8 → 40,8 |
|---|
| \Xpage{8} |
| \Xsecc{2.4.6}{ADC modules interface }{8} |
| \Xsecc{2.4.7}{Output data format }{8} |
| \Xsec{2.5}{Achieved parameters }{8} |
| \Xpage{9} |
| \Xsec{2.5}{Achieved parameters }{9} |
| \Xsecc{2.5.1}{Data reading and recording }{9} |
| \Xsecc{2.5.2}{ADC module parameters }{9} |
| \Xpage{10} |
| 54,9 → 54,6 |
|---|
| \Xpage{13} |
| \Xfig{img-NVIDIA-K1}{3.1}{NVIDIA Jetson TK1 Development Kit} |
| \Xlabel{img-NVIDIA-K1}{3.1} |
| \Xpage{14} |
| \Xchap{4}{Conclusion }{14} |
| \Xsec{4.1}{Possible future improvements }{14} |
| \Xpage{15} |
| \Xchap{A}{Circuit diagram of ADCdual01A module }{15} |
| \Xpage{16} |