| 8,7 → 8,7 |
|---|
| |
| \label[ADC1-gain] |
| $$ |
| A = {806 R_1 \over R_1 + R_2} \eqmark\,, |
| A = {806 R_1 \over R_1 + R_2}\,, \eqmark |
| $$ |
| % |
| where |
| 19,13 → 19,12 |
|---|
| \enditems |
| |
| We have $R_2 = 1000\, \Omega$ and $R_1 = 50\, \Omega$ which imply that $A = 0.815$. This value of A was further confirmed by the measurement. |
| In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator. Circuit diagram of the used transformer circuit is shown in Figure~\ref[balun-circuit] and circuit realization in Figure~\ref[SMA2SATA-nest]. |
| In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator, see Figure~\ref[balun-circuit]. |
| |
| \midinsert |
| \clabel[balun-circuit]{Balun transformer circuit} |
| \picw=7cm \cinspic ./img/SMA2SATA.pdf |
| \picw=8cm \cinspic ./img/SMA2SATA_nest1.JPG |
| \caption/f Simplified balun transformer circuit diagram. |
| \picw=7cm \hbox{\inspic ./img/SMA2SATA.pdf \picw=8cm \inspic ./img/SMA2SATA_nest1.JPG } |
| \caption/f Simplified balun transformer circuit diagram (left) and balun transformer constructed from H1012 transformer salvaged from an old Ethernet card (right). |
| \endinsert |
| |
| The signal generator Agilent 33220A which we used, does not have optimal parameters for this type of dynamic range measurement. Signal distortion and spurious levels are only -70 dBc according to Agilent datasheet \cite[33220A-generator]. We have managed to measure an ADC saturation voltage of 706 mV (generator output) with this setup. The main result of our measurement, seen as a FFT plot shown in Figure~\ref[ADC1-FFT], confirms $>$80 dB dynamic range at ADC module input. |
| 32,7 → 31,7 |
|---|
| |
| \midinsert |
| \clabel[ADC1-FFT]{ADC1 sine test FFT} |
| \picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png |
| \picw=15cm \cinspic ./img/screenshots/ADC1_CH1_FFT.png |
| \caption/f Sine signal sampled by ADC1 module with LTC2190 and LT6600-5 devices. |
| \endinsert |
| |
| 41,7 → 40,7 |
|---|
| |
| \label[ADC2-gain] |
| $$ |
| A = {1580 R_1 \over R_1 + R_2} \eqmark\,. |
| A = {1580 R_1 \over R_1 + R_2}\,. \eqmark |
| $$ |
| % |
| The ADC2 module has LT6600-2.5 amplifiers populated on it with a gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well within the parameter tolerances of the used setup. Again, FFT plot shown in Figure~\ref[ADC2-FFT] confirms $>$ 80 dB dynamic range. |
| 53,13 → 52,6 |
|---|
| \caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices. |
| \endinsert |
| |
| \midinsert |
| \clabel[SMA2SATA-nest]{Used balun transformer} |
| \picw=15cm \cinspic ./img/SMA2SATA_nest1.JPG |
| \caption/f Balun transformer circuit used for ADC parameters measurement. It is constructed from H1012 transformer salvaged from an old Ethernet card. |
| \endinsert |
| |
| |
| \sec Example of usage |
| |
| At current state the constructed radioastronomy digitization unit paired with SDRX01B receiver module could be used in several experiments. We describe overall ideas of these experiments and show preliminary results in cases where we obtain the data. |
| 66,11 → 58,11 |
|---|
| |
| \secc Simple polarimeter station |
| |
| If we use two antennas with different linear polarization (Crossed Yagi antennas for example), we should determine polarization state of received signal. Such kind of measurement is useful if we need an additional information about reflection to distinguish between targets. This configuration needs more complicated antenna configuration and we had no experience with this type of observation, so we have not implemented this experiment. |
| If we use two antennas with different linear polarization (Crossed Yagi antennas for example), we should determine polarization state of received signal. Such kind of measurement is useful if we need an additional information about reflection to distinguish between targets. This configuration needs more complicated antenna configuration and we had no experience with this type of observation, so we have not implemented this experiment. However, this is exactly the scenario the system is designed for. |
| |
| \secc Basic interferometric station |
| |
| Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in the image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N, 14$^\circ$ 25' 4.170'' E. |
| Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in the Figure~\ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N, 14$^\circ$ 25' 4.170'' E. |
| Antennae were equipped with LNA01A amplifiers. All coaxial cables had the same length of 5 meters. Antennae were isolated by common mode ferrite bead mounted on cable to minimise the signal coupling between antennas. Evaluation system consisted of SDGPSDO local oscillator subsystem used to tune the local oscillator frequency. |
| |
| \midinsert |
| 83,12 → 75,12 |
|---|
| |
| Despite of the schematic diagram proposed at beginning of system description \ref[expected-block-schematic]. |
| We have used two separate oscillators -- one oscillator drives ENC signal to ADCs still through FPGA based divider and the other one drives it to SDRX01B mixer. |
| The reason for this modification was an attempt to simplify the frequency tuning during the experiment. A single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA schema. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA scheme is changed. Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver. |
| The reason for this modification was an attempt to simplify the frequency tuning during the experiment. A single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA design. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA design is changed. Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver. |
| We have used ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators. |
| |
| \midinsert |
| \clabel[phase-difference]{Phase difference} |
| \picw=10cm \cinspic ./img/screenshots/phase_difference.png |
| \picw=15cm \cinspic ./img/screenshots/phase_difference.png |
| \caption/f Demonstration of phase difference between antennae. |
| \endinsert |
| |
| 104,7 → 96,7 |
|---|
| |
| \midinsert |
| \clabel[meteor-reflection]{Meteor reflection} |
| \picw=10cm \cinspic ./img/screenshots/observed_meteor.png |
| \picw=13cm \cinspic ./img/screenshots/observed_meteor.png |
| \caption/f Meteor reflection (the red spot in centre of image) received by an evaluation design. |
| \endinsert |
| |
| 111,7 → 103,7 |
|---|
| |
| \chap Proposition of the final system |
| |
| The construction of the final system, that is supposed to be employed for real radioastronomy observations will be described in this chapter. It is mainly a theoretical analysis of the data handling systems. Realization of the described ideas might be possible as a part of our future development after we fully evaluate and test the current trial design. |
| The construction of the final system, that is supposed to be employed for real radioastronomy observations is described in this chapter. It is mainly a theoretical analysis of the data handling systems. Realization of the described ideas might be possible as a part of our future development after we fully evaluate and test the current trial design. |
| |
| The system requires proper handling of huge amounts of data and either huge and fast storage capacity is needed to store the captured signal data, or enormous computational power is required for online data processing and filtering. Several hardware approaches currently exist and are in use for data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially constructed ASICs are used for this task. |
| |
| 120,7 → 112,7 |
|---|
| In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than the trial design. It should be compatible with MLAB internal standards which are further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface. |
| Thunderbolt technology standard was expected to be used in this PC to PCIe module communication which further communicates with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as they are only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need to preserve standard PC as a main computational platform. |
| |
| However, these PCI express external systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing the thesis. Therefore, a better solution probably needs to be found. |
| However, these PCI express external systems and cables are still very expensive. The Opal Kelly XEM6110 \cite[fpga-pcie] is an example, with its price tag reaching 995 USD at time of writing the thesis. Therefore, a better solution probably needs to be found. |
| |
| An interface problem will by probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to an increased demand of embedded technologies, which require high computation capacity, low power consumption and small size -- especially smartphones. Many of those ARM based systems have interesting parameters of signal processing. These facts make Intel's ix86 architecture unattractive for future projects. |
| |