| 21,7 → 21,7 |
|---|
| |
| \sec System scalability |
| |
| For analog channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each I/Q channel in ACD module. ADC module must also have separate inputs for sampling and data output clocks. These parameters allow for conduction at relatively low digital data rates. Then the digital signal can be conducted even through long wires. |
| For analogue channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each I/Q channel in ADC module. ADC module must also have separate inputs for sampling and data output clocks. These parameters allow for conduction at relatively low digital data rates. Then the digital signal can be conducted even through long wires. |
| |
| Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes. (Failure detection, jitter measurement etc.) |
| |
| 47,9 → 47,9 |
|---|
| \secc Frequency synthesis |
| |
| We have used centralised topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used while other working frequencies have been derived by its division. This central oscillator has a software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by specification.} |
| This method has been used in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability on wide area for effective radioastronomy imaging. |
| Frequency monitoring compensation method has been used in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability on wide area for effective radioastronomy imaging. |
| |
| Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock delivered by FPGA from main local oscillator. This signal should use high quality differential signaling cable -- SATA cable should be used for this purpose. |
| Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock delivered by FPGA from main local oscillator. This signal should use high quality differential signalling cable -- SATA cable should be used for this purpose. |
| |
| \secc Signal cable connectors |
| |
| 81,9 → 81,9 |
|---|
| |
| This modules have MLAB standard construction with four mounting holes in corner aligned in defined raster. |
| |
| Data serial data output of ADC module should be connected directly to FPGA for basic primary signal processing. Used ADC chip has selectable bit width of data output bus thus output SATA connectors has signals arranged to contain a single bit from every ADC channel. This signal concept enables selection of proper bus bitwidth according to sampling rate. (Higher bus bit-width downgrades signalling speed and vice versa.) |
| Data serial data output of ADC module should be connected directly to FPGA for basic primary signal processing. Used ADC chip has selectable bit width of data output bus thus output SATA connectors has signals arranged to contain a single bit from every ADC channel. This signal concept enables selection of proper bus bit-width according to sampling rate. (Higher bus bit-width downgrades signalling speed and vice versa.) |
| |
| For connection of this signaling layout, miniSAS to multiple SATA cable should be used. |
| For connection of this signalling layout, miniSAS to multiple SATA cable should be used. |
| |
| For PCB layout KiCAD design suite was used. Used version has the CERN Push \& Shove routing capability integrated but was slightly unstable and sometimes falls on exception during routing. Design must be often saved due to this stability issues. But Open-source KiCAD works well compared to commercial solutions as MentorGraphics PADS or Cadence Orcad. And much better than widely used Eagle software. |
| |
| 92,7 → 92,7 |
|---|
| |
| \secc ADC selection |
| |
| Several ADC signaling formats currently exist for communication with FPGA. |
| Several ADC signalling formats currently exist for communication with FPGA. |
| |
| \begitems |
| * DDR LVDS |
| 127,7 → 127,7 |
|---|
| \secc ADC modules interface |
| |
| All two ADCdual01A modules was connected to FPGA ML605 board trough FMC2DIFF01A adapter board. Construction of this adapter module suppose FMC LPC connector. And this board is not MLAB compatible design. But this board is designed to meet VITA 57 standard specification for boards which uses zone 1 and zone 3. |
| This specification guarantee compatibility with others FPGA board which has FMC LPC connector for mezzane cards. Schematic diagram of this adapter board is included in appendix. |
| This specification guarantee compatibility with others FPGA board which has FMC LPC connector for Mezzanine Card. Schematic diagram of this adapter board is included in appendix. |
| |
| Primary purpose of this PCB is to enable connection of ADC modules from space excluded from PC case. (In PC box analog circuits cannot be realised without using of massive RFI mitigation techniques). |
| Differential signaling connectors should be used for conducting digital signal over relatively long cable. Signalintegrity sensitive links (clocks) are equiped by output driver and translator to LVPECL logic for better signal transmission quality. |
| 187,7 → 187,6 |
|---|
| \caption/f Sine signal from ADC1 module with LTC21190 and LT6600-5 devices. |
| \endinsert |
| |
| T |
| |
| ADC1 CH1 maximal input 705.7 mV |
| |
| 225,7 → 224,7 |
|---|
| |
| \sec Parralella board computer |
| |
| Parallella is gon |
| %Parallella is gon |
| |
| \sec GPU based computational system |
| |
| 237,12 → 236,3 |
|---|
| \caption/f The NVIDIA Jetson TK1 Development Kit \url{https://developer.nvidia.com/jetson-tk1}. |
| \endinsert |
| |
| |
| |
| \chap Conclusion |
| |
| Special design of scalable data-aquisition system was proposed. This system has parameters |
| |
| \sec Possible future improvements |
| |
| Several ADC module imperfections, such as useless separation of FRAME and DCO signal to two connectors, should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest. |