MLABlibrarysvnkaklikMLAB_E8magsvn

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/dokumenty/skolni/diplomka/desctription.tex
129,17 → 129,17
Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter module expects the presence of FMC LPC connector and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support zone 1 and zone 3.
This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of this adapter board is included in the appendix.
The primary purpose of the PCB is to enable the connection of ADC modules from space excluded from PC case. (In PC box analog circuits cannot be realised without using of massive RFI mitigation techniques).
Differential signalling connectors should be used for conducting digital signal over relatively long cable. Signalintegrity sensitive links (clocks) are equiped by output driver and translator to LVPECL logic for better signal transmission quality.
The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case. (In PC box analog circuits cannot be realised without the use of massive RFI mitigation techniques).
Differential signalling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
\midinsert
\picw=10cm \cinspic ./img/ML605-board.jpg
\caption/f Used FPGA ML605 development board.
\caption/f FPGA ML605 development board.
\endinsert
Several SATA connectors and two miniSAS connectors are populated on this board. This set of connectors allows connection of any number of ADC modules in range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors. Other supporting signal should be routed directly to SATA connectors on adapter.
Several SATA connectors and two miniSAS connectors are populated on this board. This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter.
Signal configuration used in testing construction is described in tables.
Signal configuration used in our trial design is described in the following tables.
\secc Output data format
159,24 → 159,24
\secc Data reading and recording
For reading data stream from ADC driver Gnuradio software was used. Gnuradio suite consist gnuradio-companion which is a graphical tool for creating signal flow graphs and generating flow-graph source code. This tool was used to create basic RAW data grabber to record and interactive wiev data stream output from ADC modules.
We use Gnuradio software to read the data stream from the ADC drive. Gnuradio suite consist of gnuradio-companion which is a graphical tool for creating signal-flow graphs and generating flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view the data stream output from ADC modules.
\midinsert
\picw=15cm \cinspic ./img/screenshots/Grabber.grc.png
\caption/f ADC recorder flow graph created in gnuradio-companion.
\caption/f An ADC recorder flow graph created in gnuradio-companion.
\endinsert
\midinsert
\picw=15cm \cinspic ./img/screenshots/Grabber_running.png
\caption/f User interface window of running ADC grabber.
\caption/f User interface window of a running ADC grabber.
\endinsert
Interactive graber wiewer user interface shows live osciloscope-like time-value display for all data channels and live time-frequency scrolling display (waterfall wiev) for displaying frequency components of grabbed signal.
Interactive grabber viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal.
\secc ADC module parameters
Two pieces of ADC module design were realised and tested first piece denoted as ADC1 has LTC21190
ADC chip populated with LT660015 front-end operational apmlifier. This ADC1 module has 1kOhm resistors populated on inputs which gives to module internal attenuation of input signal. Value of this attenuation $A$ is described by formula
Two pieces of ADC modules were completed and tested. The first piece, labeled ADC1, has LTC21190
ADC chip populated with LT660015 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which gives it an ability of an internal attenuation of input signal. The value of this attenuation $A$ is described by the following formula
$$
A = {1580 \times R_1 \over R_1 + R_2}
212,15 → 212,15
\chap Proposed final system
Construction of final system which should be used for real radioastronomy observations will be described. This chapter is mainly theoretical analysis of systems which should be used for data handling. Realisation of these ideas are planed for future development after full evaluation and testing of actual functional example design.
Construction of a final system which is supposed to be employed for real radioastronomy observations will be described. This chapter is mainly a theoretical analysis of data handling systems. Realisation of these ideas might be possible as a part of our future development after we fully evaluate and test the current trial design.
\sec Custom design of FPGA board
In beginning of the project coustom design of FPGA interface board was supposed. This FPGA board should include PCI express interface and should have lower price than functional example construction. This board should have MLAB compatible design which is backward compatible with existing or improved design of ADC modules. For connection of this board an another adapter board with PCIe host interface was supposed.
Thunderbolt technology standard was supposed for use in this PC to PCIe -> FPGA module. Thunderbolt chips are currently available on the market for reasonable prices. But specification for these devices are accessible for licensed users only and Intel has mass market oriented licensing policy, which makes this technology inaccessible for low quantity product design. In consequence of this external PCI Express cabling and expansion slots should be better solution.
In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than trial design. It should be compatible with MLAB which is further backward compatible with the existing or improved design of ADC modules. For a connection of this board to another adapter board with PCIe we expect a use of a host interface.
Thunderbolt technology standard was expected to be used in this PC to PCIe -> FPGA module. Thunderbolt chips are currently available on the market for reasonable prices. However, a problem lies in the accessibility to their specifications, as they are only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution.
But this systems and cables are still very expensive. For example (http://www.opalkelly.com/products/xem6110/) has price tag 995 USD at time of writing this thesis.
Therefore better approach must be found.
However, these systems and cables are still very expensive. Take (http://www.opalkelly.com/products/xem6110/) as an example, with its price tag reaching 995 USD at time of writing of thesis.
Therefore, a better solution probably needs to be found.
\sec Parralella board computer
228,7 → 228,7
\sec GPU based computational system
A new GPU development board NVIDIA K1 has been released in recent time it is shown on image \ref[img-NVIDIA-K1]. This board are intended for use in computer vision, robotics, medicine, security, and automotive. This board has ideal parameters for signal processing for this relatively low price 192 USD. But it is currently in pre-order release stage (in April 2014).
A new GPU development board NVIDIA K1, shown in the following picture \ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have ideal parameters for signal processing for a relatively low price of 192 USD. Unfortunately, they are currently only in pre-order release stage (in April 2014).
\midinsert
\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}