| 105,22 → 105,22 |
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| The construction of the final system, which is supposed to be employed for real radioastronomy observations, is described in this chapter. It deals mainly with the theoretical analysis of the data handling systems. The implementation of the described ideas might be possible as part of our future development after we fully evaluate and test the current trial design. |
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| The system requires proper handling of huge amounts of data. Either a huge and fast storage capacity is needed to store the captured signal data, or an enormous computational power is required for the online data processing and filtering. Several hardware approaches currently exist and are in use for the data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially constructed ASICs are used for this task. |
| The system requires proper handling of huge amounts of data. Either a huge and fast storage capacity is needed to store the captured signal data, or an enormous computational power is required for the online data processing and filtering. Several hardware approaches currently exist and are in use for the data processing problem handling. Either powerful multi-gigahertz CPUs, GPUs, FPGAs, or specially constructed ASICs are used for this task. |
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| \sec Custom design of FPGA board |
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| In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than the trial design. It should be compatible with MLAB internal standards which are further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface. |
| Thunderbolt technology standard was expected to be used in this PC to PCIe module communication which further communicates with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as they are only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need to preserve standard PC as a main computational platform. |
| At the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than the trial design. It should be compatible with MLAB internal standards which are further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe, we expect the use of a PCIe host interface. |
| Thunderbolt technology standard was expected to be used in this PC to PCIe module communication, which further talks to MLAB compatible FPGA module. Thunderbolt chips are currently available on the market at a reasonable price~\cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as they are only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, the external PCI Express cabling and expansion slots should be considered as a better solution, if we need to preserve standard PC as a main computational platform. |
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| However, these PCI express external systems and cables are still very expensive. The Opal Kelly XEM6110 \cite[fpga-pcie] is an example, with its price tag reaching 995 USD at time of writing the thesis. Therefore, a better solution probably needs to be found. |
| Nevertheless, these PCI express external systems and cables are still very expensive. Opal Kelly XEM6110~\cite[fpga-pcie] is the example. Its price reached 995 USD at the time of writing the thesis. Therefore, a better solution probably needs to be found. |
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| An interface problem will by probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to an increased demand of embedded technologies, which require high computation capacity, low power consumption and small size -- especially smartphones. Many of those ARM based systems have interesting parameters of signal processing. These facts make Intel's ix86 architecture unattractive for future projects. |
| The interface problem will by probably resolved by other than Intel ix86 architecture. Many ARM computers have occurred on the market due to an increased demand for embedded technologies requiring a high computation capacity, low power consumption and small size. The smartphones market is a driving force here. Many of those ARM based systems have interesting signal processing parameters. These facts make Intel's ix86 architecture unattractive for future projects. |
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| \sec Parralella board computer |
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| Parallella is a new product created by Adapteva, Inc. \cite[parallella-board]. It represents a small supercomputer, that has been in development for almost two years with only testing series of boards produced until now (first single-board computers with 16-core Epiphany chip were shipped in December 2013) \cite[parallella-board]. The board has nearly ideal parameters for signal processing (as it provides around 50 GFLOPS of computational power). It is is equipped with Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and operating frequency of 866 MHz, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition to this, the board consumes only 3 Watts of power if both Zynq and Epiphany cores are running simultaneously. |
| Parallella is a new product created by Adapteva, Inc.~\cite[parallella-board]. It represents a small supercomputer, which has been in development for almost two years with only testing series of boards produced until now~\cite[parallella-board]. First single-board computers with the 16-core Epiphany chip were shipped in December 2013 for the first time. The board has nearly ideal parameters for signal processing (as it provides around 50 GFLOPS of the computational power). The board is is equipped with Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and operating frequency of 866 MHz, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition to this, the board consumes only 3 Watts of power if both Zynq and Epiphany cores are running simultaneously. |
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| The main disadvantage of Parralella board is its unknown lead time and an absence of SATA interface or other interface suitable for data storage connection. Fast data storage interface would be useful and would allow bulk processing of captured data. Following that, the results of data processing may be sent over the Ethernet interface to data storage server. |
| The main disadvantage of Parralella board is its unknown lead time and the absence of SATA interface or other interface suitable for data storage connection. Fast data storage interface would be useful and would allow bulk processing of captured data. Following that, the results of data processing may be sent over the Ethernet interface to the data storage server. |
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| \midinsert |
| \clabel[img-parallella-board]{Parallella board overview} |
| 132,7 → 132,7 |
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| \sec GPU based computational system |
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| A new GPU development board NVIDIA K1, shown in the following picture \ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have good parameters for signal processing for a relatively low price of 192 USD. Unfortunately, they are currently only in pre-order release stage (in April 2014). |
| A new GPU development board NVIDIA K1, shown in Figure~\ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have good parameters for signal processing for a relatively low price of 192 USD. Unfortunately, they are currently only in pre-order release stage (in April 2014). |
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| \midinsert |
| \clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit} |
| 149,6 → 149,6 |
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| Other embedded ARM based computers, for example ODROID-XU, lack a suitable high speed interface \cite[mlab-arm]. Their highest speed interface is USB 3.0 which has currently unsettled development support and needs commercial software tools for evaluation and testing. |
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| From the summary analysis mentioned above, the Parrallella board seems to be a best candidate for computational board in radioastronomy data acquisition system, as it is optimised for high data flow processing. On one hand, Parrallella does not have much memory to cache the processing data but on the other hand it has wide bandwidth data channels instead. Other boards might provide much more computational power -- 300 GFLOPS in case of NVIDIA K1, but they are optimised for heavy computational tasks on limited amount of data which represents a typical problem in computer graphics. However, in our application we do not need such extreme computation power at data acquisition system level. |
| As a result we should presumably wait until Parallella becomes widely available. Following that, a new ADCdual interface board should be designed and prepared to be used in new scalable radio astronomy data acquisition system. In the meantime, before suitable computing hardware become accessible, the required applications and algorithms should be optimised using the proposed trial version with FPGA development board on standard PC host computer (having a PCI Express interface to development board). |
| From the summary analysis mentioned above, the Parrallella board seems to be the best candidate for the computational board serving the radioastronomy data acquisition system, as it is optimised for high data flow processing. On one hand, Parrallella does not have much memory to cache the processing data but on the other hand it has wide bandwidth data channels instead. Other boards might provide much more computational power -- 300 GFLOPS in case of NVIDIA K1, but they are optimised for heavy computational tasks on limited amount of data which represents a typical problem in computer graphics. However, in our application we do not need such extreme computation power at data acquisition system level. |
| As a result, we should presumably wait until Parallella becomes widely available. Following that, a new ADCdual interface board should be designed and prepared to be used in a new scalable radio astronomy data acquisition system. In the meantime, before the suitable computing hardware becomes accessible, the required applications and algorithms should be optimised using the proposed trial version with FPGA development board on the standard PC host computer (having a PCI Express interface to development board). |
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