| 6,16 → 6,16 |
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| \sec Possible hardware improvements |
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| PCB design of used modules might need more precise high speed optimization of differential pairs. Improvement in high-speed routing allows possible use of fastest ADC from Linear Technology devices family. Use of faster ADCs even improve range of possible usage. |
| The PCB design of the used modules might need more precise high-speed optimalization of differential pairs. Improvement in high-speed routing allows a possible use of the fastest ADC from the Linear Technology devices family. The use of the faster ADCs even improve a range of possible usages. |
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| \secc ADC modules weakness |
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| Several ADC module imperfections, such as useless separation of FRAME and DCO signal to two connectors, should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest. |
| Several ADC module imperfections, such as the unnecessary separation of FRAME and DCO signal to two connectors, should be mitigated. These two signals should be merged together to one SATA connector. With this modification we are able to remove one redundant SATA cable between the analog to digital converter nest and between computational unit nest. |
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| \sec Possible software improvements |
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| In future versions of device, the Xillybus IP core and interface should be swapped with an open-source alternative PCIe interfacing module or PCIe may be completely avoided. |
| In the future versions of the device, the Xillybus IP core and interface should be swapped with an open-source alternative PCIe interfacing module or PCIe might be completely avoided. |
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| SPI configuration data read back should be implemented. |