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| /dokumenty/skolni/diplomka/SCH/FMC2DIFF.pdf |
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| /dokumenty/skolni/diplomka/appendix.tex |
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| 13,7 → 13,7 |
| \egroup |
| } |
| %\app Zadání práce |
| %\app Thesis specification |
| %\picw=\hsize % obrázek na šířku sazby |
| %\cinspic ./img/zadani.jpg |
| %\nextoddpage |
| 20,12 → 20,13 |
| \app Circuit diagram of ADCdual01A module |
| \picw=\hsize \cinspic /home/kaklik/svn/svnMLAB/Modules/ADconverters/ADCdual01A/SCH_PCB/ADCdual.pdf |
| \adddocument{./SCH/ADCdual} |
| %\pdfrotate{90} \cinspic /home/kaklik/svn/svnMLAB/Modules/ADconverters/ADCdual01A/SCH_PCB/ADCdual.pdf |
| \app Circuit diagram of FMC2DIFF module |
| \adddocument{/home/kaklik/svn/svnMLAB/Modules/Universal/FMC2DIFF01A/SCH_PCB/FMC2DIFF} |
| \adddocument{./SCH/FMC2DIFF} |
| \app Content of enclosed CD |
| /dokumenty/skolni/diplomka/description.tex |
|---|
| 183,6 → 183,16 |
| The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques). |
| Differential signaling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality. |
| LVPECL level signal connectors on FMC2DIFF01A board are dedicated for clock signals. We selected the SY55855V and SY55857L dual translators. Dual configuration in useful due to fact that SATA cable contains two differential pairs. |
| The SY55855V is a fully differential, CML/PECL/LVPECL-to-LVDS translator. It achieves LVDS signaling up to 1.5Gbps, depending on the distance and the characteristics of the media and noise coupling sources. |
| LVDS is intended to drive 50 $\Omega$ impedance transmission |
| line media such as PCB traces, backplanes, or cables. SY55855V inputs can be terminated with a single resistor between the true and the complement pins of a given input \cite[SY55855V-chip]. |
| The SY55857L is a fully differential, high-speed dual translator optimized to accept any logic standard from single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is guaranteed for speeds up to 2.5Gbps (2.5GHz toggle frequency). The SY55857L does not internally terminate its inputs, as different interfacing standards have different termination requirements. |
| \midinsert |
| \picw=10cm \cinspic ./img/ML605-board.jpg |
| \caption/f FPGA ML605 development board. |
| /dokumenty/skolni/diplomka/diplomka.pdf |
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| /dokumenty/skolni/diplomka/mybase.bib |
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| 176,5 → 176,22 |
| NOTE = {\url{https://aleph.cvut.cz:443/F?func=direct&doc_number=000672041&local_base=DUPL&format=999}}, |
| } |
| @MANUAL{SY55855V-chip, |
| AUTHOR = {Micrel, Inc}, |
| TITLE = {SY55855V datasheet}, |
| YEAR = {2005}, |
| MONTH = November , |
| NOTE = {\url{http://www.micrel.com/_PDF/HBW/sy55855v.pdf}}, |
| URLDATE= {2014-5-4}, |
| } |
| @MANUAL{SY55857L-chip, |
| AUTHOR = {Micrel, Inc}, |
| TITLE = {SY55857L datasheet}, |
| YEAR = {2006}, |
| MONTH = August, |
| NOTE = {\url{http://www.micrel.com/_PDF/HBW/sy55857l.pdf}}, |
| URLDATE= {2014-5-4}, |
| } |