0,0 → 1,34 |
#include <18F2550.h> |
#device adc=8 |
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#FUSES NOWDT //No Watch Dog Timer |
#FUSES WDT128 //Watch Dog Timer uses 1:128 Postscale |
#FUSES XT //Crystal osc <= 4mhz for PCM/PCH , 3mhz to 10 mhz for PCD |
#FUSES NOPROTECT //Code not protected from reading |
#FUSES NOBROWNOUT //No brownout reset |
#FUSES BORV20 //Brownout reset at 2.0V |
#FUSES NOPUT //No Power Up Timer |
#FUSES NOCPD //No EE protection |
#FUSES STVREN //Stack full/underflow will cause reset |
#FUSES NODEBUG //No Debug mode for ICD |
#FUSES NOLVP //No low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O |
#FUSES NOWRT //Program memory not write protected |
#FUSES NOWRTD //Data EEPROM not write protected |
#FUSES IESO //Internal External Switch Over mode enabled |
#FUSES FCMEN //Fail-safe clock monitor enabled |
#FUSES PBADEN //PORTB pins are configured as analog input channels on RESET |
#FUSES NOWRTC //configuration not registers write protected |
#FUSES NOWRTB //Boot block not write protected |
#FUSES NOEBTR //Memory not protected from table reads |
#FUSES NOEBTRB //Boot block not protected from table reads |
#FUSES NOCPB //No Boot Block code protection |
#FUSES MCLR //Master Clear pin enabled |
#FUSES LPT1OSC //Timer1 configured for low-power operation |
#FUSES NOXINST //Extended set extension and Indexed Addressing mode disabled (Legacy mode) |
#FUSES PLL12 //Divide By 12(48MHz oscillator input) |
#FUSES CPUDIV4 //System Clock by 4 |
#FUSES USBDIV //USB clock source comes from PLL divide by 2 |
#FUSES VREGEN //USB voltage regulator enabled |
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#use delay(clock=4000000) |
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