/schemata/praxe/lampickaLED/CAM_PROFI/V2.rep |
---|
File deleted |
/schemata/praxe/lampickaLED/CAM_PROFI/DRILL.rep |
---|
File deleted |
/schemata/praxe/lampickaLED/CAM_PROFI/DRILL.lst |
---|
File deleted |
/schemata/praxe/lampickaLED/CAM_PROFI/BOARD.rep |
---|
File deleted |
/schemata/Layou1.pcb |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/schemata/Layou2.pcb |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/schemata/Layout.err |
---|
0,0 → 1,3 |
Reading file -- C:\Program Files\Mentor Graphics\PADS\2005_1\Settings\default.asc |
**NO ERRORS FOUND** |
/schemata/Layout.log |
---|
0,0 → 1,18 |
PADS Layout ECO Generator (Version 6.1b) 21.6.2006 20:43:55 |
Copyright (c) 2003 Mentor Graphics Corp. - All rights reserved |
ASCII reading (part types and decals) - 5 msec |
ASCII reading (part types and decals) - 5 msec |
Reading the OLD DESIGN |
There are 19 parts in the design |
There are 14 signals in the design |
There are 49 pins in the design |
ASCII reading (parts, nets, attributes) - 18 msec |
Reading the NEW DESIGN |
There are 21 parts in the design |
There are 14 signals in the design |
There are 53 pins in the design |
ASCII reading (parts, nets, attributes) - 15 msec |
Final cost=416 |
Partitioning - 1 msec |
Final Matching - 1 msec |
Deleted pins: 3, Added pins: 7 |
/schemata/Layout.pcb |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/schemata/Layout.rep |
---|
0,0 → 1,45 |
*PADS-ECO-V3.0-MILS* |
*REMARK* old file: D:\KAKLIK\schemata\ecogtmp0.asc |
*REMARK* new file: D:\KAKLIK\schemata\ecogtmp1.asc |
*REMARK* created by ECOGEN (Version 6.1b) on 21.6.2006 20:43:55 |
PART DIFFERENCES |
---------------- |
OLD DESIGN NEW DESIGN |
Ref-des Part-type:Decal Ref-des Part-type:Decal |
D1 LED <none> |
<none> C3 C |
<none> J1 SCW2 |
<none> J2 SCW2 |
NET DIFFERENCES |
---------------- |
OLD DESIGN NEW DESIGN |
<none> N03786 |
SWAPPED GATE DIFFERENCES |
------------------------ |
OLD DESIGN NEW DESIGN |
SWAPPED PIN DIFFERENCES |
------------------------ |
OLD DESIGN NEW DESIGN |
UNMATCHED NET PINS IN OLD DESIGN |
-------------------------------- |
N03786 D1.C Q1.C |
VCC D1.A |
UNMATCHED NET PINS IN NEW DESIGN |
-------------------------------- |
GND J1.1 C3.2 |
N03786 J2.2 Q1.C |
VCC C3.1 J2.1 J1.2 |
ATTRIBUTE DIFFERENCES |
--------------------- |
Attribute Level [ OLD DESIGN Parent -> NEW DESIGN Parent ] |
Attribute Name Old Value New Value |
/schemata/Logic.err |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
/Router_06_21_21_25.bre |
---|
Property changes: |
Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/schemata/Router_06_21_21_45.bre |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/schemata/RoutingReport.txt |
---|
0,0 → 1,1373 |
PADS Router 2005 SPac1, Routing report |
Design: D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Wed Jun 21 21:08:06 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+39) |
Vias: 0(+0) |
Trace length: 18330(+18330) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:07 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+39) |
Vias: 0(+0) |
Trace length: 18456(+18456) Mils |
Duration 00:00:02(+00:00:02) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18330(-126) Mils |
Rerouted: 0 |
Duration 00:00:07(+00:00:05) |
============================================================================================== |
Wed Jun 21 21:08:28 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18239(-91) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18330(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18239(-91) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:08:58 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+4) |
Vias: 0(+0) |
Trace length: 18197(+1112) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+4) |
Vias: 0(+0) |
Trace length: 18286(+1201) Mils |
Duration 00:00:01(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18197(-89) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:09:09 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18197(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18197(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18197(+0) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:10:07 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+7) |
Vias: 0(+0) |
Trace length: 17634(+3285) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:06 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+7) |
Vias: 0(+0) |
Trace length: 17653(+3304) Mils |
Duration 00:00:01(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17634(-19) Mils |
Rerouted: 0 |
Duration 00:00:06(+00:00:05) |
============================================================================================== |
Wed Jun 21 21:11:11 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+9) |
Vias: 0(+0) |
Trace length: 17264(+3659) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+9) |
Vias: 0(+0) |
Trace length: 17347(+3742) Mils |
Duration 00:00:01(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17264(-83) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:11:18 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17297(+33) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:04 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17264(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17297(+33) Mils |
Rerouted: 0 |
Duration 00:00:04(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:11:41 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 38(+3) |
Vias: 0(+0) |
Trace length: 16203(+3778) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:08 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 38(+3) |
Vias: 0(+0) |
Trace length: 16222(+3797) Mils |
Duration 00:00:02(+00:00:02) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 16203(-19) Mils |
Rerouted: 0 |
Duration 00:00:08(+00:00:06) |
============================================================================================== |
Wed Jun 21 21:11:50 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 38(+0) |
Vias: 0(+0) |
Trace length: 16203(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 38(+0) |
Vias: 0(+0) |
Trace length: 16203(+0) Mils |
Duration 00:00:01(+00:00:01) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 16203(+0) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:12:24 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+1) |
Vias: 0(+0) |
Trace length: 18010(+1245) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:16 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+1) |
Vias: 0(+0) |
Trace length: 18165(+1400) Mils |
Duration 00:00:01(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18010(-155) Mils |
Rerouted: 0 |
Duration 00:00:16(+00:00:15) |
============================================================================================== |
Wed Jun 21 21:12:54 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17141(-129) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:07 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17270(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17141(-129) Mils |
Rerouted: 0 |
Duration 00:00:07(+00:00:07) |
============================================================================================== |
Wed Jun 21 21:13:26 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 38(+0) |
Vias: 0(+0) |
Trace length: 17100(+1) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:04 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 38(+0) |
Vias: 0(+0) |
Trace length: 17099(+0) Mils |
Duration 00:00:01(+00:00:01) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17100(+1) Mils |
Rerouted: 0 |
Duration 00:00:04(+00:00:03) |
============================================================================================== |
Wed Jun 21 21:13:49 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 38(+0) |
Vias: 0(+0) |
Trace length: 17114(-81) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:04 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 38(+0) |
Vias: 0(+0) |
Trace length: 17195(+0) Mils |
Duration 00:00:01(+00:00:01) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17114(-81) Mils |
Rerouted: 0 |
Duration 00:00:04(+00:00:03) |
============================================================================================== |
Wed Jun 21 21:14:22 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+1) |
Vias: 0(+0) |
Trace length: 18523(+1285) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+1) |
Vias: 0(+0) |
Trace length: 19299(+2061) Mils |
Duration 00:00:01(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18523(-776) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:14:28 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18523(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:04 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18523(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18523(+0) Mils |
Rerouted: 0 |
Duration 00:00:04(+00:00:03) |
============================================================================================== |
Wed Jun 21 21:15:23 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+11) |
Vias: 0(+0) |
Trace length: 16987(+4341) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+11) |
Vias: 0(+0) |
Trace length: 17038(+4392) Mils |
Duration 00:00:01(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 16987(-51) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:15:30 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 16987(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 16987(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 16987(+0) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:15:37 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 16987(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 16987(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 16987(+0) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:15:44 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 16987(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 16987(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 16987(+0) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:26:09 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+4) |
Vias: 0(+0) |
Trace length: 17122(+1362) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+4) |
Vias: 0(+0) |
Trace length: 17122(+1362) Mils |
Duration 00:00:01(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17122(+0) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:26:16 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17122(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17122(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17122(+0) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:26:35 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+2) |
Vias: 0(+0) |
Trace length: 17143(+747) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+2) |
Vias: 0(+0) |
Trace length: 17158(+762) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17143(-15) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:26:42 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17143(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17143(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17143(+0) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:28:12 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+6) |
Vias: 0(+0) |
Trace length: 18223(+3788) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:04 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+6) |
Vias: 0(+0) |
Trace length: 18232(+3797) Mils |
Duration 00:00:01(+00:00:01) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18223(-9) Mils |
Rerouted: 0 |
Duration 00:00:04(+00:00:02) |
============================================================================================== |
Wed Jun 21 21:28:17 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18027(-196) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:04 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18223(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18027(-196) Mils |
Rerouted: 0 |
Duration 00:00:03(+00:00:03) |
============================================================================================== |
Wed Jun 21 21:28:47 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+39) |
Vias: 0(+0) |
Trace length: 18066(+18066) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:08 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+39) |
Vias: 0(+0) |
Trace length: 18165(+18165) Mils |
Duration 00:00:03(+00:00:02) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18066(-99) Mils |
Rerouted: 0 |
Duration 00:00:08(+00:00:05) |
============================================================================================== |
Wed Jun 21 21:35:48 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+3) |
Vias: 0(+0) |
Trace length: 17526(+1871) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:08 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+3) |
Vias: 0(+0) |
Trace length: 17492(+1837) Mils |
Duration 00:00:01(+00:00:01) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17526(+34) Mils |
Rerouted: 0 |
Duration 00:00:08(+00:00:07) |
============================================================================================== |
Wed Jun 21 21:36:04 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17526(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:06 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17526(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17526(+0) Mils |
Rerouted: 0 |
Duration 00:00:06(+00:00:06) |
============================================================================================== |
Wed Jun 21 21:37:07 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+4) |
Vias: 0(+0) |
Trace length: 18099(+2886) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:04 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+4) |
Vias: 0(+0) |
Trace length: 18403(+3190) Mils |
Duration 00:00:01(+00:00:01) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18099(-304) Mils |
Rerouted: 0 |
Duration 00:00:04(+00:00:03) |
============================================================================================== |
Wed Jun 21 21:38:08 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+7) |
Vias: 0(+0) |
Trace length: 17550(+2325) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:07 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+7) |
Vias: 0(+0) |
Trace length: 17712(+2487) Mils |
Duration 00:00:01(+00:00:01) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17550(-162) Mils |
Rerouted: 0 |
Duration 00:00:07(+00:00:06) |
============================================================================================== |
Wed Jun 21 21:38:15 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17550(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:06 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17550(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17550(+0) Mils |
Rerouted: 0 |
Duration 00:00:06(+00:00:06) |
============================================================================================== |
Wed Jun 21 21:39:28 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17550(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:06 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17550(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17550(+0) Mils |
Rerouted: 0 |
Duration 00:00:06(+00:00:06) |
============================================================================================== |
Wed Jun 21 21:41:21 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+10) |
Vias: 0(+0) |
Trace length: 17178(+2753) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:06 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+10) |
Vias: 0(+0) |
Trace length: 17250(+2825) Mils |
Duration 00:00:01(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17178(-72) Mils |
Rerouted: 0 |
Duration 00:00:06(+00:00:06) |
============================================================================================== |
Wed Jun 21 21:41:31 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17178(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:06 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 17178(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17178(+0) Mils |
Rerouted: 0 |
Duration 00:00:06(+00:00:05) |
============================================================================================== |
Wed Jun 21 21:42:14 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+2) |
Vias: 0(+0) |
Trace length: 17146(+430) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:06 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+2) |
Vias: 0(+0) |
Trace length: 17146(+430) Mils |
Duration 00:00:01(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 17146(+0) Mils |
Rerouted: 0 |
Duration 00:00:06(+00:00:05) |
============================================================================================== |
Wed Jun 21 21:42:25 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+10) |
Vias: 0(+0) |
Trace length: 16965(+2836) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:03 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+10) |
Vias: 0(+0) |
Trace length: 16980(+2851) Mils |
Duration 00:00:01(+00:00:01) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 16965(-15) Mils |
Rerouted: 0 |
Duration 00:00:02(+00:00:01) |
============================================================================================== |
Wed Jun 21 21:42:34 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 16965(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 16965(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 16965(+0) Mils |
Rerouted: 0 |
Duration 00:00:04(+00:00:04) |
============================================================================================== |
Wed Jun 21 21:42:58 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+4) |
Vias: 0(+0) |
Trace length: 18810(+5337) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:07 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+4) |
Vias: 0(+0) |
Trace length: 18862(+5389) Mils |
Duration 00:00:01(+00:00:01) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18810(-52) Mils |
Rerouted: 0 |
Duration 00:00:07(+00:00:05) |
============================================================================================== |
Wed Jun 21 21:43:08 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18810(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18810(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18810(+0) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:05) |
============================================================================================== |
Wed Jun 21 21:44:18 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+3) |
Vias: 0(+0) |
Trace length: 18825(+1125) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:06 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+3) |
Vias: 0(+0) |
Trace length: 18825(+1125) Mils |
Duration 00:00:01(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18825(+0) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:05) |
============================================================================================== |
Wed Jun 21 21:45:11 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18825(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18825(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18825(+0) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:05) |
============================================================================================== |
Wed Jun 21 21:46:32 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+5) |
Vias: 0(+0) |
Trace length: 18804(+1048) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:06 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+5) |
Vias: 0(+0) |
Trace length: 18824(+1068) Mils |
Duration 00:00:01(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18804(-20) Mils |
Rerouted: 0 |
Duration 00:00:06(+00:00:05) |
============================================================================================== |
Wed Jun 21 21:47:06 2006 |
Autorouting D:\KAKLIK\schemata\default_blz1.pcb |
============================================================================================== |
Pre-routing analysis |
Warning:Not enough vias for routing from the top to the bottom of the design. |
To correct the problem, define additional vias or enable vias for routing using |
the Via Biasing tab of the Design Properties dialog box. |
============================================================================================== |
Passes Processed: Route, Optimize |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18804(+0) Mils |
Test points: 0(+0) |
Accessible nets: 0(+0) |
Duration 00:00:05 |
============================================================================================== |
Pass: 3 (Route) |
Routed Connections: 39(+0) |
Vias: 0(+0) |
Trace length: 18804(+0) Mils |
Duration 00:00:00(+00:00:00) |
============================================================================================== |
Pass: 4 (Optimize) |
Vias: 0(+0) |
Trace length: 18804(+0) Mils |
Rerouted: 0 |
Duration 00:00:05(+00:00:05) |
============================================================================================== |
/schemata/Session.log |
---|
0,0 → 1,834 |
`<000> |
----------------- |
Loading PCB file 'D:\KAKLIK\schemata\default_blz1.pcb'... |
PCB file loaded -- `DESIGN[D:\KAKLIK\schemata\default_blz1.pcb][D:\KAKLIK\schemata\default_blz1.pcb] -- version 2005.0 |
Integrity Test in progress... |
No database integrity problems found |
... Integrity test report saved -- `FILE[D:\KAKLIK\schemata\TestIntegrity.txt][D:\KAKLIK\schemata\TestIntegrity.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 39 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:02 (+00:00:02) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(-0) Inches Duration 00:00:07 (+00:00:05) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:07 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(-0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 4 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(-0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(+0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 7 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(-0) Inches Duration 00:00:06 (+00:00:05) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:06 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 9 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(-0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:04 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:04 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 3 Total 38 of 39 (97.4%) Vias 0 Duration 00:00:02 (+00:00:02) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 16(-0) Inches Duration 00:00:08 (+00:00:06) |
----------------- |
Done> Unroutes 1 Routed 38 of 39 (97.4%) Vias 0 Duration 00:00:08 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 38 of 39 (97.4%) Vias 0 Duration 00:00:01 (+00:00:01) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 16(+0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 1 Routed 38 of 39 (97.4%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
Pre-routing analysis finished. |
Route All Nets: Routed 2 Total 38 of 39 (97.4%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:01 (+00:00:00) |
----------------- |
Done> Unroutes 1 Routed 38 of 39 (97.4%) Vias 0 Duration 00:00:01 |
----------------- |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 1 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(-0) Inches Duration 00:00:16 (+00:00:15) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:16 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
Pre-routing analysis finished. |
Route All Nets: Routed 2 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:01 (+00:00:00) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:01 |
----------------- |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(-0) Inches Duration 00:00:07 (+00:00:07) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:07 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
Pre-routing analysis finished. |
Route All Nets: Routed 3 Total 38 of 39 (97.4%) Vias 0 Duration 00:00:02 (+00:00:02) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:02 (+00:00:00) |
----------------- |
Done> Unroutes 1 Routed 38 of 39 (97.4%) Vias 0 Duration 00:00:02 |
----------------- |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 38 of 39 (97.4%) Vias 0 Duration 00:00:01 (+00:00:01) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:04 (+00:00:03) |
----------------- |
Done> Unroutes 1 Routed 38 of 39 (97.4%) Vias 0 Duration 00:00:04 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
Pre-routing analysis finished. |
Route All Nets: Routed 2 Total 38 of 39 (97.4%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:00 (+00:00:00) |
----------------- |
Done> Unroutes 1 Routed 38 of 39 (97.4%) Vias 0 Duration 00:00:00 |
----------------- |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 38 of 39 (97.4%) Vias 0 Duration 00:00:01 (+00:00:01) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(-0) Inches Duration 00:00:04 (+00:00:03) |
----------------- |
Done> Unroutes 1 Routed 38 of 39 (97.4%) Vias 0 Duration 00:00:04 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
Pre-routing analysis finished. |
Route All Nets: Routed 2 Total 38 of 39 (97.4%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:01 (+00:00:00) |
----------------- |
Done> Unroutes 1 Routed 38 of 39 (97.4%) Vias 0 Duration 00:00:01 |
----------------- |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 1 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 19(-1) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 19(+0) Inches Duration 00:00:04 (+00:00:03) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:04 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 11 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(-0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Saving PCB file 'D:\KAKLIK\@dokumenty\skola\SPSSE\E2B\praxe\lampickaLED\default_blz1.pcb'... |
PCB file saved -- `DESIGN[D:\KAKLIK\@dokumenty\skola\SPSSE\E2B\praxe\lampickaLED\default_blz1.pcb][D:\KAKLIK\@dokumenty\skola\SPSSE\E2B\praxe\lampickaLED\default_blz1.pcb] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 4 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 37 of 39 (94.9%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 16(+0) Inches Duration 00:00:00 (+00:00:00) |
----------------- |
Done> Unroutes 2 Routed 37 of 39 (94.9%) Vias 0 Duration 00:00:00 |
----------------- |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 2 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(-0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:05 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 6 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:01) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(-0) Inches Duration 00:00:04 (+00:00:02) |
----------------- |
User stop> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:04 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(-0) Inches Duration 00:00:03 (+00:00:03) |
----------------- |
User stop> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:04 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
Protect in progress... |
...Protect finished. |
Unprotect in progress... |
...Unprotect finished. |
Unroute in progress... |
...Unroute finished. |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 39 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:03 (+00:00:02) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(-0) Inches Duration 00:00:08 (+00:00:05) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:08 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 3 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:01) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(+0) Inches Duration 00:00:08 (+00:00:07) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:08 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(+0) Inches Duration 00:00:06 (+00:00:06) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:06 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
Pre-routing analysis finished. |
Route All Nets: Routed 2 Total 35 of 39 (89.7%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 15(+0) Inches Duration 00:00:00 (+00:00:00) |
----------------- |
Done> Unroutes 4 Routed 35 of 39 (89.7%) Vias 0 Duration 00:00:01 |
----------------- |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 4 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:01) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(-0) Inches Duration 00:00:04 (+00:00:03) |
----------------- |
User stop> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:04 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 7 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:01) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(-0) Inches Duration 00:00:07 (+00:00:06) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:07 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(+0) Inches Duration 00:00:06 (+00:00:06) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:06 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 18(+0) Inches Duration 00:00:06 (+00:00:06) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:06 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 10 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(-0) Inches Duration 00:00:06 (+00:00:06) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:06 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:06 (+00:00:05) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:06 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 2 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:06 (+00:00:05) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:06 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
Unroute in progress... |
...Unroute finished. |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
Pre-routing analysis finished. |
Route All Nets: Routed 10 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:01) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(-0) Inches Duration 00:00:02 (+00:00:01) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:03 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 17(+0) Inches Duration 00:00:04 (+00:00:04) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
Unroute in progress... |
...Unroute finished. |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 4 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:01) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 19(-0) Inches Duration 00:00:07 (+00:00:05) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:07 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 19(+0) Inches Duration 00:00:05 (+00:00:05) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 3 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 19(+0) Inches Duration 00:00:05 (+00:00:05) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:06 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 19(+0) Inches Duration 00:00:05 (+00:00:05) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 5 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:01 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 19(-0) Inches Duration 00:00:06 (+00:00:05) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:06 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Batch Router Statistics |
Pre-routing analysis in progress... |
`<001> |
Not enough vias for routing from the top to the bottom of the design. To correct the problem, define additional vias or enable vias for routing using the Via Biasing tab of the Design Properties dialog box. |
`<000> |
Pre-routing analysis finished. |
Route All Nets: Routed 0 Total 39 of 39 (100.0%) Vias 0 Duration 00:00:00 (+00:00:00) |
----------------- |
Optimize All Nets: Vias 0(+0) Trace length 19(+0) Inches Duration 00:00:05 (+00:00:05) |
----------------- |
Done> Unroutes 0 Routed 39 of 39 (100.0%) Vias 0 Duration 00:00:05 |
----------------- |
Routing report -- `FILE[D:\KAKLIK\schemata\RoutingReport.txt][D:\KAKLIK\schemata\RoutingReport.txt] |
----------------- |
Saving PCB file 'D:\KAKLIK\@dokumenty\skola\SPSSE\E2B\praxe\lampickaLED\default_blz1.pcb'... |
PCB file saved -- `DESIGN[D:\KAKLIK\@dokumenty\skola\SPSSE\E2B\praxe\lampickaLED\default_blz1.pcb][D:\KAKLIK\@dokumenty\skola\SPSSE\E2B\praxe\lampickaLED\default_blz1.pcb] |
/schemata/TestIntegrity.txt |
---|
0,0 → 1,3 |
PADS Router. Database Integrity Test results for <D:\KAKLIK\schemata\default_blz1.pcb> |
No database integrity problems found. |
/schemata/Untitled.eco |
---|
0,0 → 1,24 |
*PADS-ECO-V3.0-MILS* |
*REMARK* old file: D:\KAKLIK\schemata\ecogtmp0.asc |
*REMARK* new file: D:\KAKLIK\schemata\ecogtmp1.asc |
*REMARK* created by ECOGEN (Version 6.1b) on 21.6.2006 20:43:55 |
*DELPIN* |
D1.A VCC |
D1.C N03786 |
Q1.C N03786 |
*DELPART* |
D1 LED |
*PART* |
C3 C |
J1 SCW2 |
J2 SCW2 |
*NET* |
*SIGNAL* GND |
J1.1 C3.2 |
*SIGNAL* N03786 |
J2.2 Q1.C |
*SIGNAL* VCC |
C3.1 J2.1 J1.2 |
*REMARK* Deleted pins: 3, Added pins: 7 |
*END* |
/schemata/ascii.err |
---|
0,0 → 1,12 |
Reading file -- D:\KAKLIK\@dokumenty\skola\SPSSE\E2B\praxe\lampickaLED\LAMPICKA.asc |
*Unspecified or unsupported version of ASCII file |
*PADS-PCB* |
Loading <C0805> from library |
Cannot create attribute with name <Description> |
Warning: Attribute of type Description not allowed for specified object |
Loading <C0805> from library |
Cannot create attribute with name <Value> |
Warning: Attribute of type Value not allowed for specified object |
**INPUT WARNINGS FOUND** |
/schemata/asciitmp.asc |
---|
0,0 → 1,914 |
!PADS-POWERPCB-V2005.0-MILS! DESIGN DATABASE ASCII FILE 1.0 |
*MISC* MISCELLANEOUS PARAMETERS |
*REMARK* PARENT_KEYWORD PARENT_VALUE |
*REMARK* [ { |
*REMARK* CHILD_KEYWORD CHILD_VALUE |
*REMARK* [ CHILD_KEYWORD CHILD_VALUE |
*REMARK* [ { |
*REMARK* GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...] |
*REMARK* } ]] |
*REMARK* } ] |
RULES_SECTION MILS |
{ |
NET_CLASS DATA |
GROUP DATA |
DESIGN RULES |
{ |
RULE_SET (1) |
{ |
FOR : |
{ |
DEFAULT : |
} |
AGAINST : |
{ |
DEFAULT : |
} |
LAYER 0 |
CLEARANCE_RULE : |
{ |
TRACK_TO_TRACK 6 |
VIA_TO_TRACK 6 |
VIA_TO_VIA 6 |
PAD_TO_TRACK 6 |
PAD_TO_VIA 6 |
PAD_TO_PAD 6 |
SMD_TO_TRACK 6 |
SMD_TO_VIA 6 |
SMD_TO_PAD 6 |
SMD_TO_SMD 6 |
COPPER_TO_TRACK 6 |
COPPER_TO_VIA 6 |
COPPER_TO_PAD 6 |
COPPER_TO_SMD 6 |
TEXT_TO_TRACK 6 |
TEXT_TO_VIA 6 |
TEXT_TO_PAD 6 |
TEXT_TO_SMD 6 |
OUTLINE_TO_TRACK 6 |
OUTLINE_TO_VIA 6 |
OUTLINE_TO_PAD 6 |
OUTLINE_TO_SMD 6 |
OUTLINE_TO_COPPER 6 |
DRILL_TO_TRACK 6 |
DRILL_TO_VIA 6 |
DRILL_TO_PAD 6 |
DRILL_TO_SMD 6 |
DRILL_TO_COPPER 6 |
SAME_NET_SMD_TO_VIA 6 |
SAME_NET_SMD_TO_CRN 6 |
SAME_NET_VIA_TO_VIA 6 |
SAME_NET_PAD_TO_CRN 6 |
MIN_TRACK_WIDTH 12 |
REC_TRACK_WIDTH 12 |
MAX_TRACK_WIDTH 12 |
DRILL_TO_DRILL 6 |
BODY_TO_BODY 6 |
SAME_NET_TRACK_TO_CRN 0 |
} |
} |
RULE_SET (2) |
{ |
FOR : |
{ |
DEFAULT : |
} |
AGAINST : |
{ |
DEFAULT : |
} |
LAYER 0 |
HIGH_SPEED_RULE : |
{ |
MIN_LENGTH 0 |
MAX_LENGTH 50000 |
STUB_LENGTH 0 |
PARALLEL_LENGTH 1000 |
PARALLEL_GAP 200 |
TANDEM_LENGTH 1000 |
TANDEM_GAP 200 |
MIN_DELAY 0.000000 |
MAX_DELAY 10.000000 |
MIN_CAPACITANCE 0.000000 |
MAX_CAPACITANCE 10.000000 |
MIN_IMPEDANCE 50.000000 |
MAX_IMPEDANCE 150.000000 |
SHIELD_NET * |
SHIELD_GAP 200 |
MATCH_LENGTH_TOLERANCE 200 |
} |
} |
RULE_SET (3) |
{ |
FOR : |
{ |
DEFAULT : |
} |
AGAINST : |
{ |
DEFAULT : |
} |
LAYER 0 |
ROUTE_RULE : |
{ |
LENGTH_MINIMIZATION_TYPE 1 |
VIA_SHARE Y |
TRACE_SHARE Y |
AUTO_ROUTE Y |
RIPUP Y |
SHOVE Y |
ROUTE_PRIORITY 3 |
VALID_LAYER 1 |
VALID_LAYER 2 |
VALID_VIA_TYPE STANDARDVIA |
} |
} |
} |
} |
*MISC* MISCELLANEOUS PARAMETERS |
ATTRIBUTES DICTIONARY |
{ |
ATTRIBUTE DFT.Nail Count Per Net |
{ |
TYPE INTEGER |
MIN 0 |
MAX 1000 |
INHERITANCE NET NETCLASS PCB |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE Rules.PadEntry.Side |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.PadEntry.Corner |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.PadEntry.AnyAngle |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.PadEntry.Soft |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.ViaAtSMD |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.ViaAtSMD.FitInside |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.ViaAtSMD.Center |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.ViaAtSMD.Ends |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Alignment |
{ |
TYPE LIST N |
{ |
Aligned |
Alternate |
} |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Alignment.Multi-Row |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Direction |
{ |
TYPE LIST N |
{ |
Inside |
Outside |
Both Sides |
} |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.ViaSpacing |
{ |
TYPE LIST N |
{ |
Use Grid |
1 Trace |
2 Trace |
} |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Sharing.Pin |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Sharing.SMD |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Sharing.Via |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Sharing.Trace |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Nets.Plane |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Nets.Signal |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Nets.UnusedPins |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Length.Unlimited |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Length.Maximum |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 2000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Trace.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Via.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Via.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Pad.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Pad.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Pad.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.SMD.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.SMD.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.SMD.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.SMD.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Copper.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Copper.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Copper.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Copper.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Text.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Text.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Text.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Text.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Board.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Board.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Board.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Board.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Drill.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Drill.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Drill.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Drill.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.SMD.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.SMD.Crn |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.Via.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.Pad.Crn |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.Trace.Crn |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Width.Minimum |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 250.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Width.Recommended |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 250.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Width.Maximum |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 250.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
} |
ATTRIBUTE VALUES |
{ |
PCB DEFAULT |
{ |
Rules.ViaAtSMD No |
Rules.Fanout.Alignment Alternate |
Rules.Fanout.Direction Both Sides |
Rules.Fanout.ViaSpacing Use Grid |
Rules.Fanout.Alignment.Multi-Row Yes |
Rules.Fanout.Length.Maximum 250.00mil |
Rules.Fanout.Length.Unlimited Yes |
Rules.Fanout.Nets.Plane Yes |
Rules.Fanout.Nets.Signal No |
Rules.Fanout.Nets.UnusedPins No |
Rules.Fanout.Sharing.Pin Yes |
Rules.Fanout.Sharing.SMD Yes |
Rules.Fanout.Sharing.Trace Yes |
Rules.Fanout.Sharing.Via Yes |
Rules.PadEntry.AnyAngle Yes |
Rules.PadEntry.Corner Yes |
Rules.PadEntry.Side Yes |
Rules.PadEntry.Soft Yes |
Rules.ViaAtSMD.Center Yes |
Rules.ViaAtSMD.Ends Yes |
Rules.ViaAtSMD.FitInside Yes |
} |
} |
*END* OF ASCII OUTPUT FILE |
/schemata/backup.pcb |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/schemata/default_blz1.pcb |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Added: svn:mime-type |
+application/octet-stream |
\ No newline at end of property |
/schemata/eco.err |
---|
0,0 → 1,9 |
** ECO In Report ** |
Wed Jun 21 20:44:48 2006 |
Input File : D:\KAKLIK\schemata\Untitled.eco |
Current Job : default_blz.pcb |
No errors found |
/schemata/ecogtmp0.asc |
---|
0,0 → 1,4647 |
!PADS-POWERPCB-V2005.0-METRIC! DESIGN DATABASE ASCII FILE 1.0 |
*PCB* GENERAL PARAMETERS OF THE PCB DESIGN |
UNITS 1 2=Inches 1=Metric 0=Mils |
USERGRID 2.54 2.54 Space between USER grid points |
MAXIMUMLAYER 2 Maximum routing layer |
WORKLEVEL 0 Level items will be created on |
DISPLAYLEVEL 1 toggle for displaying working level last |
LAYERPAIR 1 2 Layer pair used to route connection |
VIAMODE T Type of via to use when routing between layers |
LINEWIDTH 0.254 Width items will be created with |
TEXTSIZE 2.54 0.254 Height and LineWidth text will be created with |
JOBTIME 22 Amount of time spent on this PCB design |
DOTGRID 25.4 25.4 Space between graphic dots |
SCALE 12.202 Scale of window expansion |
ORIGIN 254 254 User defined origin location |
WINDOWCENTER 758.19 691.33296 Point defining the center of the window |
BACKUPTIME 20 Number of minutes between database backups |
REAL WIDTH 0.254 Widths greater then this are displayed real size |
ALLSIGONOFF 1 All signal nets displayed on/off |
REFNAMESIZE 2.54 0.254 Height and LineWidth used by part ref. names |
HIGHLIGHT 0 Highlight nets flag |
JOBNAME default_blz.pcb |
CONCOL 1 |
FBGCOL 1 0 |
HATCHGRID 0.254 Copper pour hatching grid |
TEARDROP 2713690 Teardrop tracks |
THERLINEWID 0.381 Copper pour thermal line width |
PSVIAGRID 0.635 0.635 Push & Shove Via Grid |
PADFILLWID 0.254 CAM finger pad fill width |
THERSMDWID 0.254 Copper pour thermal line width for SMD |
MINHATAREA 0 Minimum hatch area |
HATCHMODE 0 Hatch generation mode |
HATCHDISP 0 Hatch display flag |
DRILLHOLE 0.1524 Drill hole checking spacing |
MITRERADII 0.5 1.0 1.5 2.0 2.5 3.0 3.5 |
MITRETYPE 1 Mitring type |
HATCHRAD 0.500000 Hatch outline smoothing radius |
MITREANG 180 180 180 180 180 180 90 |
HATCHANG 0 Hatch angle |
THERFLAGS 0 Copper pour thermal line flags |
DRLOVERSIZE 0.0762 Drill oversize for plated holes |
PLANERAD 0.000000 Plane outline smoothing radius |
PLANEFLAGS OUTLINE THERMALS Y Y Y N N Y Y Y N N Y Y N Y Y N N N Plane and Test Points flags |
COMPHEIGHT 0 Board Top Component Height Restriction |
KPTHATCHGRID 2.54 Copper pour hatching grid |
BOTCMPHEIGHT 0 Board Bottom Component Height Restriction |
FANOUTGRID 0.635 0.635 Fanout grid |
FANOUTLENGTH 6.35 Maximum fanout length |
ROUTERFLAGS 83879441 Autorouter specific flags |
VERIFYFLAGS 1861 Verify Design flags |
FABCHKFLAGS 3967 Fabrication checks flags |
ATMAXSIZE 0.0762 Acid Traps Maximum Size |
ATMAXANGLE 161999820 Acid Traps Maximum Angle |
SLMINCOPPER 0.0762 Slivers Minimum Copper |
SLMINMASK 0.0762 Slivers Minimum Mask |
STMINCLEAR 5 Starved Thermal Minimum Clearance |
STMINSPOKES 4 Starved Thermal Minimum Spokes |
TPMINWIDTH 0.0762 Minimum Trace Width |
TPMINSIZE 0.0762 Mimimum Pad Size |
SSMINGAP 0.0762 Silk Screen Over Pads Minimum Gap |
SBMINGAP 0.0762 Solder Bridges Minimum Gap |
SBLAYER 1 Solder Bridges Layer |
ARPTOM 0.0762 Pad To Mask Annular Ring |
ARPTOMLAYER 1 Pad To Mask Annular Ring Layer |
ARDTOM 0.0762 Drill To Mask Annular Ring |
ARDTOMLAYER 1 Drill To Mask Annular Ring Layer |
ARDTOP 0.0762 Drill To Pad Annular Ring |
ARDTOPLAYER 0 Drill To Pad Annular Ring Layer |
PLNSEPGAP 0.1524 Plane separation gap |
IDFSHAPELAY 0 IDF shapes layer |
TEARDROPDATA 90 90 |
*PARTDECAL* ITEMS |
*REMARK* NAME UNITS ORIX ORIY PIECES TERMINALS STACKS TEXT LABELS |
*REMARK* PIECETYPE CORNERS WIDTHHGHT LEVEL RESTRICTIONS |
*REMARK* PIECETYPE CORNERS WIDTH LEVEL PINNUM |
*REMARK* XLOC YLOC BEGINANGLE DELTAANGLE |
*REMARK* XLOC YLOC ORI LEVEL HEIGHT WIDTH MIRRORED HJUST VJUST |
*REMARK* VISIBLE XLOC YLOC ORI LEVEL HEIGTH WIDTH MIRRORED HJUST VJUST RIGHTREADING |
*REMARK* FONTSTYLE FONTFACE |
*REMARK* T XLOC YLOC NMXLOC NMYLOC |
*REMARK* PAD PIN STACKLINES |
*REMARK* LEVEL SIZE SHAPE IDIA DRILL [PLATED] |
*REMARK* LEVEL SIZE SHAPE FINORI FINLENGTH FINOFFSET DRILL [PLATED] |
C0805 M 0 0 2 2 1 0 2 |
OPEN 4 0.2032 0 |
-0.4064 0.9652 |
-1.7272 0.9652 |
-1.7272 -0.9652 |
-0.4064 -0.9652 |
OPEN 4 0.2032 0 |
0.4064 0.9652 |
1.7272 0.9652 |
1.7272 -0.9652 |
0.4064 -0.9652 |
VALUE -1.5494 3.8608 0.000 1 1.524 0.2032 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -1.4986 1.2446 0.000 1 1.524 0.2032 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-0.9652 0 -1.04 -0.4 |
T0.9652 0 0.77 -0.39 |
PAD 0 5 |
-2 0.9906 RF 90.000 1.4224 0 0 N |
-1 0 R |
0 0 R |
21 1.143 RF 90.000 1.5748 0 |
23 0.889 RF 90.000 1.3208 0 |
C0603 I 0 0 2 2 1 0 2 |
OPEN 4 8 0 |
-12 30 |
-58 30 |
-58 -30 |
-12 -30 |
OPEN 4 8 0 |
12 30 |
58 30 |
58 -30 |
12 -30 |
VALUE -58.66 150.79 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -57.87 46.06 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-30 0 -35 -15 |
T30 0 22 -15 |
PAD 0 5 |
-2 35 RF 90.000 40 0 0 N |
-1 0 R |
0 0 R |
21 41 RF 90.000 46 0 |
23 31 RF 90.000 36 0 |
C1206 I 0 0 2 2 1 0 2 |
OPEN 4 8 0 |
-34 45 |
-90 45 |
-90 -45 |
-34 -45 |
OPEN 4 8 0 |
34 45 |
90 45 |
90 -45 |
34 -45 |
VALUE -59 61 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -66 172 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-57 0 -59.94 -15.75 |
T57 0 49.31 -15.35 |
PAD 0 5 |
-2 43 RF 90.000 70 0 0 N |
-1 0 R |
0 0 R |
21 49 RF 90.000 76 0 |
23 37 RF 90.000 66 0 |
CK025 M 0 0 2 2 1 0 2 |
OPEN 2 0.2 0 |
1.25 1.5 |
-1.25 1.5 |
OPEN 2 0.2 0 |
1.25 -1.5 |
-1.25 -1.5 |
VALUE -1.5 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.7 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-1.254 0 -1.35 -0.4 |
T1.254 0 1.05 -0.3 |
PAD 0 5 |
-2 1.524 R 0.889 |
-1 1.524 R |
0 1.524 R |
21 1.674 R |
28 1.674 R |
CK050 M 0 0 2 2 1 0 2 |
OPEN 2 0.2 0 |
2.6 1.5 |
-2.6 1.5 |
OPEN 2 0.2 0 |
2.6 -1.5 |
-2.6 -1.5 |
VALUE -1.5 4.7 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -1.5 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-2.504 0 -2.6 -0.4 |
T2.504 0 2.3 -0.3 |
PAD 0 5 |
-2 1.524 R 0.889 |
-1 1.524 R |
0 1.524 R |
21 1.674 R |
28 1.674 R |
C0805/1206 I 0 0 2 2 1 0 2 |
OPEN 4 8 0 |
32 45 |
90 45 |
90 -45 |
32 -45 |
OPEN 4 8 0 |
-32 45 |
-90 45 |
-90 -45 |
-32 -45 |
VALUE -53 62 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -53 169 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-45 0 -47.94 -15.75 |
T45 0 37.31 -15.35 |
PAD 0 5 |
-2 70 S 0 N |
-1 0 R |
0 0 R |
21 76 S |
23 66 S |
C1210 I 0 0 2 2 1 0 2 |
OPEN 4 8 0 |
-41 62 |
-105 62 |
-105 -62 |
-41 -62 |
OPEN 4 8 0 |
41 62 |
105 62 |
105 -62 |
41 -62 |
VALUE -59 49 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -61 152 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-70 0 -72.94 -15.75 |
T70 0 62.31 -15.35 |
PAD 0 5 |
-2 52 RF 90.000 105 0 0 N |
-1 0 R |
0 0 R |
21 58 RF 90.000 111 0 |
23 48 RF 90.000 101 0 |
C1812 I 0 0 2 2 1 0 2 |
OPEN 4 8 0 |
-65 73 |
-141 73 |
-141 -73 |
-65 -73 |
OPEN 4 8 0 |
65 73 |
141 73 |
141 -73 |
65 -73 |
VALUE -59 49 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -61 152 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-100 0 -102.94 -15.75 |
T100 0 92.31 -15.35 |
PAD 0 5 |
-2 67 RF 90.000 130 0 0 N |
-1 0 R |
0 0 R |
21 73 RF 90.000 136 0 |
23 63 RF 90.000 126 0 |
C2220 I 0 0 2 2 1 0 2 |
OPEN 4 8 0 |
-87 116 |
-188 116 |
-188 -116 |
-87 -116 |
OPEN 4 8 0 |
87 116 |
188 116 |
188 -116 |
87 -116 |
VALUE -61 152 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -59 49 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-135 0 -137.94 -15.75 |
T135 0 127.31 -15.35 |
PAD 0 5 |
-2 87 RF 90.000 213 0 0 N |
-1 0 R |
0 0 R |
21 93 RF 90.000 219 0 |
23 83 RF 90.000 209 0 |
ELYTA I 0 0 2 2 1 0 2 |
OPEN 6 8 0 |
-27 44 |
-101.43 44 |
-109.43 36 |
-109.43 -36 |
-101.43 -44 |
-27 -44 |
OPEN 4 8 0 |
27 44 |
107 44 |
107 -44 |
27 -44 |
VALUE -55.6 63.8 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -52.24 173.48 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-63 0 -65.94 -15.75 |
T63 0 55.31 -15.35 |
PAD 0 5 |
-2 65 S 0 N |
-1 0 R |
0 0 R |
21 71 S |
23 61 S |
ELYTB I 0 0 2 2 1 0 2 |
OPEN 6 8 0 |
-35 62 |
-95 62 |
-103 54 |
-103 -54 |
-95 -62 |
-35 -62 |
OPEN 4 8 0 |
35 62 |
103 62 |
103 -62 |
35 -62 |
VALUE -59.69 265.98 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -59.69 157.89 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-65 0 -67.94 -15.75 |
T65 0 57.31 -15.35 |
PAD 0 5 |
-2 55 RF 90.000 100 0 0 |
-1 0 R |
0 0 R |
21 61 RF 90.000 106 0 |
23 51 RF 90.000 96 0 |
ELYTC I 0 0 2 2 1 0 2 |
OPEN 6 8 0 |
-55 70 |
-145 70 |
-153 62.41 |
-153 -61.91 |
-145 -70 |
-55 -70 |
OPEN 4 8 0 |
55 70 |
153 70 |
153 -70 |
55 -70 |
VALUE -64.97 198.8 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -61.55 88.37 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-100 0 -102.94 -15.75 |
T100 0 92.31 -15.35 |
PAD 0 5 |
-2 85 RF 90.000 100 0 0 |
-1 0 R |
0 0 R |
21 91 RF 90.000 106 0 |
23 81 RF 90.000 96 0 |
ELYTD I 0 0 2 2 1 1 2 |
OPEN 6 8 0 |
-80 92 |
-170 92 |
-180 82 |
-180 -82 |
-170 -92 |
-78 -92 |
OPEN 4 8 0 |
80 92 |
180 92 |
180 -92 |
80 -92 |
-136.59 -15.94 0.000 26 60 8 N LEFT DOWN 0 |
Regular <PADS Stroke Font> |
K |
VALUE -55.71 114.39 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -56.97 228.14 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-126 0 -128.94 -15.75 |
T126 0 118.31 -15.35 |
PAD 0 5 |
-2 85 RF 90.000 120 0 0 |
-1 0 R |
0 0 R |
21 91 RF 90.000 126 0 |
23 81 RF 90.000 116 0 |
CE020X5 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
105 0 |
-105 0 |
VALUE -56 174 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -56 280 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-40 0 -43.78 -15.75 |
T40 0 31.97 -11.81 |
PAD 0 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
PAD 2 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
CE025X6 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
130 0 |
-130 0 |
VALUE -56 280 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -56 174 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-50 0 -53.78 -15.75 |
T50 0 41.97 -11.81 |
PAD 0 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
PAD 2 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
CE035X8 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
170 0 |
-170 0 |
VALUE -48.01 295.22 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -49.23 191.31 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-69 0 -72.78 -15.75 |
T69 0 60.97 -11.81 |
PAD 0 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
PAD 2 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
CE050X10 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
210 0 |
-210 0 |
VALUE -52.12 339.78 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -49.7 229.88 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-100 0 -103.78 -15.75 |
T100 0 91.97 -11.81 |
PAD 0 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
PAD 2 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
CE050X13 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
270 0 |
-270 0 |
VALUE -50 430 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -50 310 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-100 0 -103.78 -15.75 |
T100 0 91.97 -11.81 |
PAD 0 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
PAD 2 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
CE075X16 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
325 0 |
-325 0 |
VALUE -60 460 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
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-2 80 R 44 |
-1 60 R |
0 80 R |
21 86 R |
28 86 R |
PUSH120SQ I 0 0 3 4 1 0 2 |
OPEN 2 8 0 |
-225 100 1565 -3129 -245.83 -250.44 255.04 250.44 |
-225 -100 |
OPEN 2 8 0 |
-225 100 |
-225 -100 |
CLOSED 5 8 0 |
-149.61 -149.61 |
149.61 -149.61 |
149.61 149.61 |
-149.61 149.61 |
-149.61 -149.61 |
VALUE 0 0 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE 0 0 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-100 100 -100 100 |
T-100 -100 -100 -100 |
T100 -100 100 -100 |
T100 100 100 100 |
PAD 0 5 |
-2 80 R 44 |
-1 60 R |
0 80 R |
21 86 R |
28 86 R |
P-B1727 I 0 0 6 4 1 0 2 |
CLOSED 3 10 0 |
-196.85 157.48 |
-196.85 196.85 |
-196.85 157.48 |
OPEN 4 8 0 |
-196.85 157.48 |
-196.85 196.85 |
196.85 196.85 |
196.85 157.48 |
OPEN 2 8 0 |
196.85 39.37 |
196.85 -39.37 |
OPEN 4 8 0 |
196.85 -157.48 |
196.85 -196.85 |
-196.85 -196.85 |
-196.85 -157.48 |
OPEN 2 8 0 |
-196.85 -39.37 |
-196.85 39.37 |
CIRCLE 2 8 0 |
-111.36 0 |
111.36 0 |
VALUE 0 0 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE 0 0 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-196.85 98.43 -196.85 98.43 |
T-196.85 -98.43 -196.85 -98.43 |
T196.85 -98.43 196.85 -98.43 |
T196.85 98.43 196.85 98.43 |
PAD 0 5 |
-2 80 R 45 |
-1 80 R |
0 80 R |
21 86 R |
22 86 R |
PUSH050X050 I 0 0 5 4 1 0 2 |
CIRCLE 2 8 0 |
55 0 |
-55 0 |
OPEN 2 8 0 |
-121 45 |
-121 -45 |
OPEN 2 8 0 |
121 45 |
121 -45 |
OPEN 2 8 0 |
112 -121 |
-112 -121 |
OPEN 2 8 0 |
112 121 |
-112 121 |
VALUE -39 220 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -39 220 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-126 85 -126 85 |
T-126 -85 -126 -85 |
T126 -85 126 -85 |
T126 85 126 85 |
PAD 0 5 |
-2 65 R 35 |
-1 65 R |
0 65 R |
21 71 R |
28 71 R |
DIP14_300 I 0 0 1 14 2 0 2 |
CLOSED 9 8 0 |
-100 350 |
-30 350 |
-30 290 |
30 290 |
30 350 |
100 350 |
100 -350 |
-100 -350 |
-100 350 |
VALUE -59.06 436.88 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -59.06 436.88 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-150 300 -150 300 |
T-150 200 -150 200 |
T-150 100 -150 100 |
T-150 0 -150 0 |
T-150 -100 -150 -100 |
T-150 -200 -150 -200 |
T-150 -300 -150 -300 |
T150 -300 150 -300 |
T150 -200 150 -200 |
T150 -100 150 -100 |
T150 0 150 0 |
T150 100 150 100 |
T150 200 150 200 |
T150 300 150 300 |
PAD 0 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 66 R |
28 66 R |
PAD 1 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 66 S |
28 66 S |
*PARTTYPE* ITEMS |
*REMARK* NAME DECALNM UNITS TYPE GATES SIGPINS PINNMS FLAGS ECO |
*REMARK* G/S SWAPTYPE PINS |
*REMARK* PIN.SWAPTYPE.PINTYPE.FUNCNAME |
*REMARK* SIGPIN PIN WIDTH SIGNAME |
C C0805:C0603:C1206:CK025:CK050:C0805/1206:C1210:C1812:C2220 I CAP 1 0 0 0 Y |
G 0 2 |
1.1.Z 2.1.Z |
C-ELYT ELYTA:ELYTB:ELYTC:ELYTD:CE020X5:CE025X6:CE035X8:CE050X10:CE050X13:CE075X16:CE075X18:CE020X5/L:CE025X6/L:CE035X8/L:CE050X10/L I CAP 1 0 2 0 Y |
G 0 2 |
1.0.U 2.0.U |
A C |
LED LED0603:LED0805-1206:LED0805:LED1206:LED1.8:LED3:LED10:LED5 I DIO 1 0 2 0 Y |
G 0 2 |
1.0.U 2.0.U |
C A |
ARK210/2 ARK210/2 I CON 0 0 0 0 Y |
T-CEB TO92:TO92/B:TO92/BSMD:TO92/L:TO39:SOT37:SOT37/SMD I TRX 0 0 4 0 Y |
C E B 4 |
R R0805:R0603:R1206:RS025:RL090:RL140:RS040:R1812 I RES 1 0 0 0 Y |
G 0 2 |
1.0.Z 2.0.Z |
PB4PIN PUSH050X050SMD:PUSH120:PUSH120SQ:P-B1727:PUSH050X050 I SWI 0 0 0 0 Y |
DIP14_300 DIP14_300 I DIP 0 0 0 0 Y |
*PART* ITEMS |
*REMARK* REFNM PTYPENM X Y ORI GLUE MIRROR ALT CLSTID CLSTATTR BROTHERID LABELS |
*REMARK* .REUSE. INSTANCE RPART |
*REMARK* VISIBLE XLOC YLOC ORI LEVEL HEIGTH WIDTH MIRRORED HJUST VJUST RIGHTREADING |
*REMARK* FONTSTYLE FONTFACE |
C1 C 512.34581 443.54334 90.000 U N 4 -1 0 -1 2 |
VALUE -1.5 4.7 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -1.5 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
C2 C-ELYT 525.51482 437.70708 90.000 U N 4 -1 0 -1 2 |
VALUE -1.4224 4.4196 0.000 1 1.524 0.2032 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.4224 7.112 0.000 1 1.524 0.2032 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
D1 LED 472.68913 449.9782 270.000 U N 7 -1 0 -1 2 |
VALUE -1.4224 7.112 0.000 1 1.524 0.2032 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -1.4224 4.4196 0.000 1 1.524 0.2032 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
M1 ARK210/2 524.61693 448.78102 90.000 U N 0 -1 0 -1 2 |
VALUE -1.5 7.5 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -1.5 5 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
R1 R 514.14158 429.77574 270.000 U N 4 -1 0 -1 2 |
VALUE -1.3 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.8 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R10 R 502.15394 448.42951 90.000 U N 4 -1 0 -1 2 |
VALUE -1.3 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.8 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R11 R 508.50644 448.5924 90.000 U N 4 -1 0 -1 2 |
VALUE -1.3 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.8 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R2 R 515.93736 448.33207 270.000 U N 4 -1 0 -1 2 |
VALUE -1.3 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.8 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R3 R 478.53569 438.98221 90.000 U N 4 -1 0 -1 2 |
VALUE -1.3 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.8 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R4 R 505.46 439.42 270.000 U N 4 -1 0 -1 2 |
VALUE -1.3 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.8 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R5 R 506.50954 432.17011 0.000 U N 4 -1 0 -1 2 |
VALUE -1.3 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.8 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R6 R 513.69264 437.55743 180.000 U N 4 -1 0 -1 2 |
VALUE -1.3 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.8 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R7 R 483.09645 439.14509 90.000 U N 4 -1 0 -1 2 |
VALUE -1.3 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.8 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R8 R 495.3 429.26 180.000 U N 4 -1 0 -1 2 |
VALUE -1.3 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.8 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R9 R 487.68 439.42 270.000 U N 4 -1 0 -1 2 |
VALUE -1.3 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.8 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
SW1 PB4PIN 471.64159 437.70708 90.000 U N 4 -1 0 -1 2 |
VALUE -0.9906 5.588 0.000 1 1.524 0.2032 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -0.9906 5.588 0.000 1 1.524 0.2032 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
U1 DIP14_300 495.3 441.96 0.000 U N 0 -1 0 -1 2 |
VALUE -1.5 11.09675 0.000 1 1.524 0.2032 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -1.5 11.09675 0.000 1 1.524 0.2032 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
Q2 T-CEB 521.92327 429.17715 0.000 U N 1 -1 0 -1 2 |
VALUE -0.3556 4.5974 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -0.3048 5.0038 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
Q1 T-CEB 482.6 449.58 180.000 U N 1 -1 0 -1 2 |
VALUE -0.3556 4.5974 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -0.3048 5.0038 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
*CONNECTION* |
*REMARK* *SIGNAL* SIGNAME SIGFLAG COLOR |
*REMARK* REFNM.PIN .REUSE. INSTANCE RSIG REFNM.PIN .REUSE. INSTANCE RSIG |
*SIGNAL* GND 0 -2 |
R6.1 C2.C |
M1.2 C2.C |
R2.1 M1.2 |
R11.1 R2.1 |
R11.1 R4.1 |
R4.1 R10.1 |
U1.11 R10.1 |
R8.1 U1.11 |
*SIGNAL* N00814 0 -2 |
SW1.2 U1.5 |
SW1.2 R6.2 |
Q2.E R6.2 |
Q2.E C2.A |
*SIGNAL* VCC 0 -2 |
R1.2 Q2.C |
SW1.1 R1.2 |
SW1.1 R3.2 |
R3.2 R7.2 |
D1.A R3.2 |
R7.2 U1.4 |
*SIGNAL* N02087 0 -2 |
R5.1 U1.8 |
*SIGNAL* N02123 0 -2 |
R5.2 Q2.B |
*SIGNAL* N02699 0 -2 |
R9.2 U1.7 |
*SIGNAL* N01929 0 -2 |
R2.2 C1.2 |
U1.10 C1.2 |
*SIGNAL* N01826 0 -2 |
R4.2 U1.9 |
R3.1 R4.2 |
*SIGNAL* N02014 0 -2 |
M1.1 C1.1 |
R1.1 C1.1 |
*SIGNAL* N02635 0 -2 |
U1.6 R7.1 |
U1.6 R8.2 |
*SIGNAL* N02735 0 -2 |
U1.3 R9.1 |
R10.2 U1.3 |
*SIGNAL* N02885 0 -2 |
U1.1 Q1.B |
*SIGNAL* N03786 0 -2 |
D1.C Q1.C |
*SIGNAL* N03815 0 -2 |
U1.2 R11.2 |
U1.2 Q1.E |
*MISC* MISCELLANEOUS PARAMETERS |
*REMARK* PARENT_KEYWORD PARENT_VALUE |
*REMARK* [ { |
*REMARK* CHILD_KEYWORD CHILD_VALUE |
*REMARK* [ CHILD_KEYWORD CHILD_VALUE |
*REMARK* [ { |
*REMARK* GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...] |
*REMARK* } ]] |
*REMARK* } ] |
RULES_SECTION METRIC |
{ |
NET_CLASS DATA |
GROUP DATA |
DESIGN RULES |
{ |
RULE_SET (1) |
{ |
FOR : |
{ |
DEFAULT : |
} |
AGAINST : |
{ |
DEFAULT : |
} |
LAYER 0 |
CLEARANCE_RULE : |
{ |
TRACK_TO_TRACK 0.508 |
VIA_TO_TRACK 0.508 |
VIA_TO_VIA 0.508 |
PAD_TO_TRACK 0.508 |
PAD_TO_VIA 0.508 |
PAD_TO_PAD 0.508 |
SMD_TO_TRACK 0.508 |
SMD_TO_VIA 0.508 |
SMD_TO_PAD 0.508 |
SMD_TO_SMD 0.508 |
COPPER_TO_TRACK 0.508 |
COPPER_TO_VIA 0.508 |
COPPER_TO_PAD 0.508 |
COPPER_TO_SMD 0.508 |
TEXT_TO_TRACK 0.508 |
TEXT_TO_VIA 0.508 |
TEXT_TO_PAD 0.508 |
TEXT_TO_SMD 0.508 |
OUTLINE_TO_TRACK 0.508 |
OUTLINE_TO_VIA 0.508 |
OUTLINE_TO_PAD 0.508 |
OUTLINE_TO_SMD 0.508 |
OUTLINE_TO_COPPER 0.508 |
DRILL_TO_TRACK 0.508 |
DRILL_TO_VIA 0.508 |
DRILL_TO_PAD 0.508 |
DRILL_TO_SMD 0.508 |
DRILL_TO_COPPER 0.508 |
SAME_NET_SMD_TO_VIA 0.254 |
SAME_NET_SMD_TO_CRN 0.254 |
SAME_NET_VIA_TO_VIA 0.254 |
SAME_NET_PAD_TO_CRN 0.254 |
MIN_TRACK_WIDTH 0.508 |
REC_TRACK_WIDTH 0.635 |
MAX_TRACK_WIDTH 1.143 |
DRILL_TO_DRILL 0.1524 |
BODY_TO_BODY 0.1524 |
SAME_NET_TRACK_TO_CRN 0.254 |
} |
} |
RULE_SET (2) |
{ |
FOR : |
{ |
DEFAULT : |
} |
AGAINST : |
{ |
DEFAULT : |
} |
LAYER 0 |
HIGH_SPEED_RULE : |
{ |
MIN_LENGTH 0 |
MAX_LENGTH 1269.99996 |
STUB_LENGTH 0 |
PARALLEL_LENGTH 25.4 |
PARALLEL_GAP 5.08 |
TANDEM_LENGTH 25.4 |
TANDEM_GAP 5.08 |
MIN_DELAY 0.000000 |
MAX_DELAY 10.000000 |
MIN_CAPACITANCE 0.000000 |
MAX_CAPACITANCE 10.000000 |
MIN_IMPEDANCE 50.000000 |
MAX_IMPEDANCE 150.000000 |
SHIELD_NET * |
SHIELD_GAP 5.08 |
MATCH_LENGTH_TOLERANCE 5.08 |
} |
} |
RULE_SET (3) |
{ |
FOR : |
{ |
DEFAULT : |
} |
AGAINST : |
{ |
DEFAULT : |
} |
LAYER 0 |
ROUTE_RULE : |
{ |
LENGTH_MINIMIZATION_TYPE 1 |
VIA_SHARE Y |
TRACE_SHARE Y |
AUTO_ROUTE Y |
RIPUP Y |
SHOVE Y |
ROUTE_PRIORITY 3 |
VALID_LAYER 2 |
} |
} |
} |
} |
*MISC* MISCELLANEOUS PARAMETERS |
ATTRIBUTES DICTIONARY |
{ |
ATTRIBUTE Value |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE DECAL |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE Tolerance |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE Part Number |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM N |
HIDDEN N |
} |
ATTRIBUTE Description |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE DECAL |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM N |
HIDDEN N |
} |
ATTRIBUTE Cost |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM N |
HIDDEN N |
} |
ATTRIBUTE Manufacturer #1 |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM N |
HIDDEN N |
} |
ATTRIBUTE Manufacturer #2 |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM N |
HIDDEN N |
} |
ATTRIBUTE PowerGround |
{ |
TYPE BOOLEAN |
INHERITANCE NET NETCLASS PCB |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE Voltage |
{ |
TYPE QUANTITY |
QUANTITY Voltage |
ABBR V |
UNIT Volt |
MIN -100kV |
MAX 100kV |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE Geometry.Height |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 635.00000mm |
INHERITANCE PCB |
INHERITANCE PART PARTTYPE DECAL |
ECO_REGISTRATION N |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE DFT.Nail Count Per Net |
{ |
TYPE INTEGER |
MIN 0 |
MAX 1000 |
INHERITANCE NET NETCLASS PCB |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE DFT.Nail Diameter |
{ |
TYPE FREETEXT N |
INHERITANCE PIN |
INHERITANCE VIA |
ECO_REGISTRATION N |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE DFT.Nail Number |
{ |
TYPE FREETEXT N |
INHERITANCE PIN |
INHERITANCE VIA |
ECO_REGISTRATION N |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Model |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Model File |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Sim Direction |
{ |
TYPE LIST N |
{ |
SIM_BOTH |
SIM_IN |
SIM_OUT |
} |
INHERITANCE PIN |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Frequency |
{ |
TYPE QUANTITY |
QUANTITY Frequency |
ABBR Hz |
UNIT Hertz |
MIN 0Hz |
MAX 1000GHz |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Duty Cycle |
{ |
TYPE QUANTITY |
QUANTITY |
ABBR % |
UNIT percent |
MIN 0% |
MAX 100% |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Signal Type |
{ |
TYPE LIST N |
{ |
Address |
Analog High Speed |
Analog Low Speed |
Clock |
Data |
Do Not Analyze |
Power Supply |
Strobe |
} |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Default IC.Model |
{ |
TYPE FREETEXT N |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Default IC.Model File |
{ |
TYPE FREETEXT N |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Default IC.Model Pin |
{ |
TYPE FREETEXT N |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE Strategy.Fanout.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.FormatId |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.ChipLength |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.ChipWidth |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.ChipHeight |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WBRules.MinLength |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WBRules.MaxLength |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WBRules.WToWDistance |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WBRules.WBtoPad |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WBRules.MaxAngle |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.SBPCount |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.SBP1 |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.CBPCount |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.CBP1 |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WBCount |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WB1 |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.SBPGuideCount |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.SBPGuide1 |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.CBPAssignment1 |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Marker_Shape |
{ |
TYPE FREETEXT N |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Text_NumberPrecision |
{ |
TYPE FREETEXT N |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Text_AngularPrecision |
{ |
TYPE FREETEXT N |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Text_Suffix |
{ |
TYPE FREETEXT N |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Text_Layer |
{ |
TYPE INTEGER |
MIN 0 |
MAX 250 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Line_Layer |
{ |
TYPE INTEGER |
MIN 0 |
MAX 250 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Preview_Type |
{ |
TYPE INTEGER |
MIN 1 |
MAX 5 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.PadEntry.Side |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.PadEntry.Corner |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.PadEntry.AnyAngle |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.PadEntry.Soft |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.ViaAtSMD |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.ViaAtSMD.FitInside |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.ViaAtSMD.Center |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.ViaAtSMD.Ends |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Alignment |
{ |
TYPE LIST N |
{ |
Aligned |
Alternate |
} |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Alignment.Multi-Row |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Direction |
{ |
TYPE LIST N |
{ |
Inside |
Outside |
Both Sides |
} |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.ViaSpacing |
{ |
TYPE LIST N |
{ |
Use Grid |
1 Trace |
2 Trace |
} |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Sharing.Pin |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Sharing.SMD |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Sharing.Via |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Sharing.Trace |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Nets.Plane |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Nets.Signal |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Nets.UnusedPins |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Length.Unlimited |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Length.Maximum |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 50.80000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.AlignmentBGA |
{ |
TYPE LIST N |
{ |
Diagonal |
Quadrant |
X-pattern |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.DirectionBGA |
{ |
TYPE LIST N |
{ |
45 |
135 |
225 |
315 |
Clockwise |
Counterclockwise |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.DirectionBGAstaggered |
{ |
TYPE LIST N |
{ |
Horizontal |
Vertical |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Trace.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Via.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Via.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Pad.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Pad.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Pad.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.SMD.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.SMD.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.SMD.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.SMD.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Copper.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Copper.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Copper.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Copper.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Text.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Text.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Text.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Text.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Board.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Board.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Board.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Board.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Drill.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Drill.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Drill.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Drill.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.SMD.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.SMD.Crn |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.Via.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.Pad.Crn |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.Trace.Crn |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 25.40000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Width.Minimum |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 6.35000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Width.Recommended |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 6.35000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Width.Maximum |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 6.35000mm |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Placement.Grid.Use |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Placement.Grid.X |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 50.80000mm |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Placement.Grid.Y |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 50.80000mm |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Accordion.Amplitude.Min |
{ |
TYPE INTEGER |
MIN 3 |
MAX 30 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Accordion.Gap.Min |
{ |
TYPE INTEGER |
MIN 1 |
MAX 10 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Routing.MaxChannelWidth |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00000mm |
MAX 254.00000mm |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Routing.SoftLengthRrules |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Routing.MeanderBeforeTune |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE MatchLength.Name |
{ |
TYPE FREETEXT N |
INHERITANCE NET NETCLASS |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Planning.Scheduled |
{ |
TYPE BOOLEAN |
INHERITANCE NET |
ECO_REGISTRATION Y |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Library.Timestamp |
{ |
TYPE FREETEXT N |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Design.Timestamp |
{ |
TYPE FREETEXT N |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DiffPair.MinControlledLength |
{ |
TYPE FLOAT |
MIN 20 |
MAX 100 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DiffPair.MaxIrregularLength |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Guard.BandColor |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Blaze.TestPoint.Color |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Blaze.Thermal.Color |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
} |
ATTRIBUTE VALUES |
{ |
PART C1 |
{ |
Value CK050 |
} |
PART C2 |
{ |
Value 47UF |
} |
PART D1 |
{ |
Value LED5MM |
} |
PART M1 |
{ |
Value MIKE |
} |
PART R1 |
{ |
Value 15K |
} |
PART R10 |
{ |
Value 10K |
} |
PART R11 |
{ |
Value 18 |
} |
PART R2 |
{ |
Value M1 |
} |
PART R3 |
{ |
Value 22K |
} |
PART R4 |
{ |
Value 5K6 |
} |
PART R5 |
{ |
Value 6K8 |
} |
PART R6 |
{ |
Value 1M |
} |
PART R7 |
{ |
Value M39 |
} |
PART R8 |
{ |
Value M1 |
} |
PART R9 |
{ |
Value M1 |
} |
PART SW1 |
{ |
Value PUSH050X050 |
} |
PART U1 |
{ |
Value LM124 |
} |
PART Q2 |
{ |
Value BC547 |
} |
PART Q1 |
{ |
Value BC547 |
} |
DECAL C0805 |
{ |
Description keramicky kondenzator SMD velikost 0805 |
Geometry.Height 1.5mm |
Value ??? |
} |
DECAL C0603 |
{ |
Description keramicky kondenzator SMD velikost 0603 |
Geometry.Height 1.5mm |
Value ??? |
} |
DECAL C1206 |
{ |
Description keramicky kondenzator SMD velikost 1206 |
Geometry.Height 1.5mm |
Value ??? |
} |
DECAL CK025 |
{ |
Description kramicky kondenzator roztec 2.54 mm ,100 mils |
Geometry.Height 8mm |
Value ??? |
} |
DECAL CK050 |
{ |
Description keramicky kondenzator roztec 5,08 mm ,200 mils |
Geometry.Height 8mm |
Value ??? |
} |
DECAL C0805/1206 |
{ |
Description univerzalni plosky pro C0805 a C1206 |
Geometry.Height 1.50000mm |
Value ??? |
} |
DECAL C1210 |
{ |
Description keramicky kondenzator SMD velikost 1210 |
Geometry.Height 2mm |
Value ??? |
} |
DECAL C1812 |
{ |
Description keramicky kondenzator SMD velikost 1812 |
Geometry.Height 2mm |
Value ??? |
} |
DECAL C2220 |
{ |
Description keramicky kondenzator SMD velikost 2220 |
Geometry.Height 2mm |
Value ??? |
} |
DECAL ELYTA |
{ |
Description elektrolyt SMD velikost A |
Geometry.Height 1.8 mm |
Value ??? |
} |
DECAL ELYTB |
{ |
Description elektrolyt SMD velikost B |
Geometry.Height 2 mm |
Value ??? |
} |
DECAL ELYTC |
{ |
Description elektrolyt SMD velikost C |
Geometry.Height 2.8 mm |
Value ??? |
} |
DECAL ELYTD |
{ |
Description elektrolyt SMD velikost D |
Geometry.Height 3 mm |
Value ??? |
} |
DECAL CE020X5 |
{ |
Description Elyt prumer 5mm, roztec 2.032mm - 80 mils |
Geometry.Height 12 mm |
Value ??? |
} |
DECAL CE025X6 |
{ |
Description Elyt prumer 6.3mm, roztec 2.54mm - 100 mils |
Geometry.Height 12 mm |
Value ??? |
} |
DECAL CE035X8 |
{ |
Description Elyt prumer 8 mm, roztec3.505 mm - 138 mils |
Geometry.Height 12 mm |
Value ??? |
} |
DECAL CE050X10 |
{ |
Description Elyt prumer 10mm, roztec 5.08mm - 200 mils |
Geometry.Height 17 mm |
Value ??? |
} |
DECAL CE050X13 |
{ |
Description Elyt prumer 13mm, roztec 5.08mm - 200 mils |
Geometry.Height 27 mm |
Value ??? |
} |
DECAL CE075X16 |
{ |
Description Elyt prumer 16mm, roztec 7.5mm - 300 mils |
Geometry.Height 26 mm |
Value ??? |
} |
DECAL CE075X18 |
{ |
Description Elyt prumer 18mm, roztec 7.5mm - 300 mils |
Geometry.Height 43 mm |
Value ??? |
} |
DECAL CE020X5/L |
{ |
Description Elyt prumer 5mm na lezato, roztec 2.032mm - 80 mils |
Geometry.Height 5.5 mm |
Value ??? |
} |
DECAL CE025X6/L |
{ |
Description Elyt prumer 6.3mm na lezato, roztec 2.54mm - 100 mils |
Geometry.Height 6.5 mm |
Value ??? |
} |
DECAL CE035X8/L |
{ |
Description Elyt prumer 8 mm na lezato, roztec3.505 mm - 138 mils |
Geometry.Height 8.5 mm |
Value ??? |
} |
DECAL CE050X10/L |
{ |
Description Elyt prumer 10mm na lezato, roztec 5.08mm - 200 mils |
Geometry.Height 10.5 mm |
Value ??? |
} |
DECAL LED0603 |
{ |
Description rezistor SMD velikost 0603 |
Geometry.Height 1mm |
Value ??? |
} |
DECAL LED0805-1206 |
{ |
Description univerzalni plosky pro LED pro pouzdro 0805 i 1206 |
Geometry.Height 1.50000mm |
Value ??? |
} |
DECAL LED0805 |
{ |
Description rezistor SMD velikost 0805 |
Geometry.Height 1mm |
Value ??? |
} |
DECAL LED1206 |
{ |
Description rezistor SMD velikost 1206 |
Geometry.Height 1mm |
Value ??? |
} |
DECAL LED1.8 |
{ |
Description LED 1.8 mm roztec 2.54 mm - 100 mils |
Geometry.Height 10mm |
Value ??? |
} |
DECAL LED3 |
{ |
Description LED 3 mm, roztec 2.54 mm - 100 mils |
Geometry.Height 10mm |
Value ??? |
} |
DECAL LED10 |
{ |
Description LED 10 mm roztec 2.54 mm - 100 mils |
Geometry.Height 10mm |
Value ??? |
} |
DECAL LED5 |
{ |
Description LED 5 mm roztec 2.54 mm - 100 mils |
Geometry.Height 10mm |
Value ??? |
} |
DECAL ARK210/2 |
{ |
Description svorkovnice se dvema piny, roztec 5.08 mm - 200 mils |
Geometry.Height 13 mm |
Value ??? |
} |
DECAL TO92 |
{ |
Description tranzistorove pouzdro TO92, kolektor uprostred |
Geometry.Height 10mm |
Value ??? |
} |
DECAL TO92/B |
{ |
Description TO92, kolektor uprostred, pro bastleni |
Geometry.Height 10mm |
Value ??? |
} |
DECAL TO92/BSMD |
{ |
Description TO92, kolektor uprostred, vyvody v jedne rade |
Geometry.Height 10mm |
Value ??? |
} |
DECAL TO92/L |
{ |
Description TO92, kolektor uprostred, vyvody v jedne rade |
Geometry.Height 10mm |
Value ??? |
} |
DECAL TO39 |
{ |
Description velke kovove pouzdro TO39 |
Geometry.Height 10 mm |
} |
DECAL SOT37 |
{ |
Description pouzdro pro tranzistory BFR... |
Geometry.Height 2.5 mm |
} |
DECAL SOT37/SMD |
{ |
Description pouzdro pro tranzistory BFR... montaz SMD |
Geometry.Height 2.5 mm |
} |
DECAL R0805 |
{ |
Description rezistor SMD velikost 0805 |
Geometry.Height 1mm |
Value ??? |
} |
DECAL R0603 |
{ |
Description rezistor SMD velikost 0603 |
Geometry.Height 1mm |
Value ??? |
} |
DECAL R1206 |
{ |
Description rezistor SMD velikost 1206 |
Geometry.Height 1mm |
Value ??? |
} |
DECAL RS025 |
{ |
Description bezny rezistor nastojato roztec 2,54 mm, 100 mils |
Geometry.Height 9 mm |
Value ??? |
} |
DECAL RL090 |
{ |
Description bezny rezistor roztec 8.89mm, 350mils |
Geometry.Height 3mm |
Value ??? |
} |
DECAL RL140 |
{ |
Description rezistor 2W nalezato roztec 13.97mm, 550mils |
Geometry.Height 4.6mm |
Value ??? |
} |
DECAL RS040 |
{ |
Description rezistor 2W nastojato, roztec 3.81 mm ,150 mils |
Geometry.Height 15mm |
Value ??? |
} |
DECAL R1812 |
{ |
Description rezistor SMD velikost 1812 |
Geometry.Height 1mm |
Value ??? |
} |
DECAL PUSH050X050SMD |
{ |
Description ctvercove SMD spinaci tlacitko , vyvody 1-4 a 2-3 propojeny |
Geometry.Height 5.00000mm |
Value ??? |
} |
DECAL PUSH120 |
{ |
Description Kulate tlacitko s vyvody v rosteci 5x5mm |
Geometry.Height 8 mm |
} |
DECAL PUSH120SQ |
{ |
Description Kulate tlacitko s vyvody v rastru 5x5mm s hranatym hmatnikem |
Geometry.Height 8 mm |
} |
DECAL P-B1727 |
{ |
Description hranate tlacitko 10x10mm |
Geometry.Height 8 mm |
} |
DECAL PUSH050X050 |
{ |
Description ctvercove spinaci tlacitko , vyvody 1-4 a 2-3 propojeny |
Geometry.Height 5.00000mm |
} |
DECAL DIP14_300 |
{ |
Description pozdro DIP14 roztec 7.62 mm - 300 mils |
Geometry.Height 6 mm |
Value ??? |
} |
PARTTYPE C |
{ |
Description ruzne druhy kondenzatoru |
Value ??? |
} |
PARTTYPE C-ELYT |
{ |
Description ruzne druhy elektrolytickych kondenzatoru |
Value ??? |
} |
PARTTYPE LED |
{ |
Description ruzne druhy LED |
Value ??? |
} |
PARTTYPE T-CEB |
{ |
Description Tanzistory s poradim nozicek 1=C 2-E 3=B |
Value ??? |
} |
PARTTYPE R |
{ |
Description rezistory ruznych typu |
Value ??? |
} |
PARTTYPE DIP14_300 |
{ |
Value ??? |
} |
PCB DEFAULT |
{ |
Accordion.Amplitude.Min 3 |
Accordion.Gap.Min 1 |
AutoDimensioning.Line_Layer 24 |
AutoDimensioning.Marker_Shape YYNNNY |
AutoDimensioning.Preview_Type 1 |
AutoDimensioning.Text_AngularPrecision 0 0 0 |
AutoDimensioning.Text_Layer 24 |
AutoDimensioning.Text_NumberPrecision 0 1 2 |
AutoDimensioning.Text_Suffix mil##mm##" |
Blaze.TestPoint.Color 8 |
Blaze.Thermal.Color 8 |
DiffPair.MaxIrregularLength 12.70000mm |
DiffPair.MinControlledLength 80 |
Guard.BandColor 7 |
Placement.Grid.Use No |
Placement.Grid.X 2.54000mm |
Placement.Grid.Y 2.54000mm |
Routing.MaxChannelWidth 2.54000mm |
Routing.MeanderBeforeTune Yes |
Routing.SoftLengthRrules Yes |
Rules.ViaAtSMD No |
Rules.Fanout.Alignment Alternate |
Rules.Fanout.AlignmentBGA Quadrant |
Rules.Fanout.Direction Both Sides |
Rules.Fanout.DirectionBGA 45 |
Rules.Fanout.DirectionBGAstaggered Horizontal |
Rules.Fanout.ViaSpacing Use Grid |
Rules.Fanout.Alignment.Multi-Row Yes |
Rules.Fanout.Length.Maximum 6.35000mm |
Rules.Fanout.Length.Unlimited Yes |
Rules.Fanout.Nets.Plane Yes |
Rules.Fanout.Nets.Signal No |
Rules.Fanout.Nets.UnusedPins No |
Rules.Fanout.Sharing.Pin Yes |
Rules.Fanout.Sharing.SMD Yes |
Rules.Fanout.Sharing.Trace Yes |
Rules.Fanout.Sharing.Via Yes |
Rules.PadEntry.AnyAngle Yes |
Rules.PadEntry.Corner Yes |
Rules.PadEntry.Side Yes |
Rules.PadEntry.Soft Yes |
Rules.ViaAtSMD.Center Yes |
Rules.ViaAtSMD.Ends Yes |
Rules.ViaAtSMD.FitInside Yes |
Strategy.Center.Intensity Low |
Strategy.Center.Pass No |
Strategy.Center.Pause No |
Strategy.Center.PlanePriority 0 |
Strategy.Center.Priority 1 |
Strategy.Center.Protect No |
Strategy.Fanout.Intensity Medium |
Strategy.Fanout.Pass No |
Strategy.Fanout.Pause No |
Strategy.Fanout.PlanePriority 0 |
Strategy.Fanout.Priority 1 |
Strategy.Fanout.Protect No |
Strategy.Miters.Intensity Low |
Strategy.Miters.Pass No |
Strategy.Miters.Pause No |
Strategy.Miters.PlanePriority 0 |
Strategy.Miters.Priority 1 |
Strategy.Miters.Protect No |
Strategy.Optimize.Intensity Low |
Strategy.Optimize.Pass Done |
Strategy.Optimize.Pause No |
Strategy.Optimize.PlanePriority 0 |
Strategy.Optimize.Priority 1 |
Strategy.Optimize.Protect No |
Strategy.Patterns.Intensity Medium |
Strategy.Patterns.Pass No |
Strategy.Patterns.Pause No |
Strategy.Patterns.PlanePriority 0 |
Strategy.Patterns.Priority 1 |
Strategy.Patterns.Protect No |
Strategy.Route.Intensity Medium |
Strategy.Route.Pass Done |
Strategy.Route.Pause No |
Strategy.Route.PlanePriority 0 |
Strategy.Route.Priority 1 |
Strategy.Route.Protect No |
Strategy.TestPoint.Intensity Low |
Strategy.TestPoint.Pass No |
Strategy.TestPoint.Pause No |
Strategy.TestPoint.PlanePriority 0 |
Strategy.TestPoint.Priority 1 |
Strategy.TestPoint.Protect No |
Strategy.Tune.Intensity Medium |
Strategy.Tune.Pass No |
Strategy.Tune.Pause No |
Strategy.Tune.PlanePriority 0 |
Strategy.Tune.Priority 1 |
Strategy.Tune.Protect No |
} |
} |
*END* OF ASCII OUTPUT FILE |
/schemata/ecogtmp1.asc |
---|
0,0 → 1,4248 |
!PADS-POWERPCB-V2005.0-MILS! DESIGN DATABASE ASCII FILE 1.0 |
*PCB* GENERAL PARAMETERS OF THE PCB DESIGN |
UNITS 0 2=Inches 1=Metric 0=Mils |
USERGRID 100 100 Space between USER grid points |
MAXIMUMLAYER 2 Maximum routing layer |
WORKLEVEL 1 Level items will be created on |
DISPLAYLEVEL 1 toggle for displaying working level last |
LAYERPAIR 1 2 Layer pair used to route connection |
VIAMODE T Type of via to use when routing between layers |
LINEWIDTH 10 Width items will be created with |
TEXTSIZE 100 10 Height and LineWidth text will be created with |
JOBTIME 0 Amount of time spent on this PCB design |
DOTGRID 1000 1000 Space between graphic dots |
SCALE 3.465 Scale of window expansion |
ORIGIN 10000 10000 User defined origin location |
WINDOWCENTER 10000 10000 Point defining the center of the window |
BACKUPTIME 20 Number of minutes between database backups |
REAL WIDTH 10 Widths greater then this are displayed real size |
ALLSIGONOFF 1 All signal nets displayed on/off |
REFNAMESIZE 100 10 Height and LineWidth used by part ref. names |
HIGHLIGHT 0 Highlight nets flag |
JOBNAME Untitled |
CONCOL 1 |
FBGCOL 1 0 |
HATCHGRID 10 Copper pour hatching grid |
TEARDROP 2713690 Teardrop tracks |
THERLINEWID 15 Copper pour thermal line width |
PSVIAGRID 25 25 Push & Shove Via Grid |
PADFILLWID 10 CAM finger pad fill width |
THERSMDWID 10 Copper pour thermal line width for SMD |
MINHATAREA 0 Minimum hatch area |
HATCHMODE 0 Hatch generation mode |
HATCHDISP 0 Hatch display flag |
DRILLHOLE 6 Drill hole checking spacing |
MITRERADII 0.5 1.0 1.5 2.0 2.5 3.0 3.5 |
MITRETYPE 1 Mitring type |
HATCHRAD 0.500000 Hatch outline smoothing radius |
MITREANG 180 180 180 180 180 180 90 |
HATCHANG 0 Hatch angle |
THERFLAGS 0 Copper pour thermal line flags |
DRLOVERSIZE 3 Drill oversize for plated holes |
PLANERAD 0.000000 Plane outline smoothing radius |
PLANEFLAGS OUTLINE THERMALS Y Y Y N N Y Y Y N N Y Y N Y Y N N N Plane and Test Points flags |
COMPHEIGHT 0 Board Top Component Height Restriction |
KPTHATCHGRID 100 Copper pour hatching grid |
BOTCMPHEIGHT 0 Board Bottom Component Height Restriction |
FANOUTGRID 25 25 Fanout grid |
FANOUTLENGTH 250 Maximum fanout length |
ROUTERFLAGS 83879441 Autorouter specific flags |
VERIFYFLAGS 1861 Verify Design flags |
FABCHKFLAGS 3967 Fabrication checks flags |
ATMAXSIZE 3 Acid Traps Maximum Size |
ATMAXANGLE 161999820 Acid Traps Maximum Angle |
SLMINCOPPER 3 Slivers Minimum Copper |
SLMINMASK 3 Slivers Minimum Mask |
STMINCLEAR 5 Starved Thermal Minimum Clearance |
STMINSPOKES 4 Starved Thermal Minimum Spokes |
TPMINWIDTH 3 Minimum Trace Width |
TPMINSIZE 3 Mimimum Pad Size |
SSMINGAP 3 Silk Screen Over Pads Minimum Gap |
SBMINGAP 3 Solder Bridges Minimum Gap |
SBLAYER 1 Solder Bridges Layer |
ARPTOM 3 Pad To Mask Annular Ring |
ARPTOMLAYER 1 Pad To Mask Annular Ring Layer |
ARDTOM 3 Drill To Mask Annular Ring |
ARDTOMLAYER 1 Drill To Mask Annular Ring Layer |
ARDTOP 3 Drill To Pad Annular Ring |
ARDTOPLAYER 0 Drill To Pad Annular Ring Layer |
PLNSEPGAP 6 Plane separation gap |
IDFSHAPELAY 0 IDF shapes layer |
TEARDROPDATA 90 90 |
*PARTDECAL* ITEMS |
*REMARK* NAME UNITS ORIX ORIY PIECES TERMINALS STACKS TEXT LABELS |
*REMARK* PIECETYPE CORNERS WIDTHHGHT LEVEL RESTRICTIONS |
*REMARK* PIECETYPE CORNERS WIDTH LEVEL PINNUM |
*REMARK* XLOC YLOC BEGINANGLE DELTAANGLE |
*REMARK* XLOC YLOC ORI LEVEL HEIGHT WIDTH MIRRORED HJUST VJUST |
*REMARK* VISIBLE XLOC YLOC ORI LEVEL HEIGTH WIDTH MIRRORED HJUST VJUST RIGHTREADING |
*REMARK* FONTSTYLE FONTFACE |
*REMARK* T XLOC YLOC NMXLOC NMYLOC |
*REMARK* PAD PIN STACKLINES |
*REMARK* LEVEL SIZE SHAPE IDIA DRILL [PLATED] |
*REMARK* LEVEL SIZE SHAPE FINORI FINLENGTH FINOFFSET DRILL [PLATED] |
C0805 M 0 0 2 2 1 0 2 |
OPEN 4 0.2032 0 |
-0.4064 0.9652 |
-1.7272 0.9652 |
-1.7272 -0.9652 |
-0.4064 -0.9652 |
OPEN 4 0.2032 0 |
0.4064 0.9652 |
1.7272 0.9652 |
1.7272 -0.9652 |
0.4064 -0.9652 |
VALUE -1.5494 3.8608 0.000 1 1.524 0.2032 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -1.4986 1.2446 0.000 1 1.524 0.2032 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-0.9652 0 -1.04 -0.4 |
T0.9652 0 0.77 -0.39 |
PAD 0 5 |
-2 0.9906 RF 90.000 1.4224 0 0 N |
-1 0 R |
0 0 R |
21 1.143 RF 90.000 1.5748 0 |
23 0.889 RF 90.000 1.3208 0 |
C0603 I 0 0 2 2 1 0 2 |
OPEN 4 8 0 |
-12 30 |
-58 30 |
-58 -30 |
-12 -30 |
OPEN 4 8 0 |
12 30 |
58 30 |
58 -30 |
12 -30 |
VALUE -58.66 150.79 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -57.87 46.06 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-30 0 -35 -15 |
T30 0 22 -15 |
PAD 0 5 |
-2 35 RF 90.000 40 0 0 N |
-1 0 R |
0 0 R |
21 41 RF 90.000 46 0 |
23 31 RF 90.000 36 0 |
C1206 I 0 0 2 2 1 0 2 |
OPEN 4 8 0 |
-34 45 |
-90 45 |
-90 -45 |
-34 -45 |
OPEN 4 8 0 |
34 45 |
90 45 |
90 -45 |
34 -45 |
VALUE -59 61 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -66 172 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-57 0 -59.94 -15.75 |
T57 0 49.31 -15.35 |
PAD 0 5 |
-2 43 RF 90.000 70 0 0 N |
-1 0 R |
0 0 R |
21 49 RF 90.000 76 0 |
23 37 RF 90.000 66 0 |
CK025 M 0 0 2 2 1 0 2 |
OPEN 2 0.2 0 |
1.25 1.5 |
-1.25 1.5 |
OPEN 2 0.2 0 |
1.25 -1.5 |
-1.25 -1.5 |
VALUE -1.5 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -1.5 4.7 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-1.254 0 -1.35 -0.4 |
T1.254 0 1.05 -0.3 |
PAD 0 5 |
-2 1.524 R 0.889 |
-1 1.524 R |
0 1.524 R |
21 1.674 R |
28 1.674 R |
CK050 M 0 0 2 2 1 0 2 |
OPEN 2 0.2 0 |
2.6 1.5 |
-2.6 1.5 |
OPEN 2 0.2 0 |
2.6 -1.5 |
-2.6 -1.5 |
VALUE -1.5 4.7 0.000 1 1.524 0.2 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -1.5 2 0.000 1 1.524 0.2 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-2.504 0 -2.6 -0.4 |
T2.504 0 2.3 -0.3 |
PAD 0 5 |
-2 1.524 R 0.889 |
-1 1.524 R |
0 1.524 R |
21 1.674 R |
28 1.674 R |
C0805/1206 I 0 0 2 2 1 0 2 |
OPEN 4 8 0 |
32 45 |
90 45 |
90 -45 |
32 -45 |
OPEN 4 8 0 |
-32 45 |
-90 45 |
-90 -45 |
-32 -45 |
VALUE -53 62 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -53 169 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-45 0 -47.94 -15.75 |
T45 0 37.31 -15.35 |
PAD 0 5 |
-2 70 S 0 N |
-1 0 R |
0 0 R |
21 76 S |
23 66 S |
C1210 I 0 0 2 2 1 0 2 |
OPEN 4 8 0 |
-41 62 |
-105 62 |
-105 -62 |
-41 -62 |
OPEN 4 8 0 |
41 62 |
105 62 |
105 -62 |
41 -62 |
VALUE -59 49 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -61 152 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-70 0 -72.94 -15.75 |
T70 0 62.31 -15.35 |
PAD 0 5 |
-2 52 RF 90.000 105 0 0 N |
-1 0 R |
0 0 R |
21 58 RF 90.000 111 0 |
23 48 RF 90.000 101 0 |
C1812 I 0 0 2 2 1 0 2 |
OPEN 4 8 0 |
-65 73 |
-141 73 |
-141 -73 |
-65 -73 |
OPEN 4 8 0 |
65 73 |
141 73 |
141 -73 |
65 -73 |
VALUE -59 49 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -61 152 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-100 0 -102.94 -15.75 |
T100 0 92.31 -15.35 |
PAD 0 5 |
-2 67 RF 90.000 130 0 0 N |
-1 0 R |
0 0 R |
21 73 RF 90.000 136 0 |
23 63 RF 90.000 126 0 |
C2220 I 0 0 2 2 1 0 2 |
OPEN 4 8 0 |
-87 116 |
-188 116 |
-188 -116 |
-87 -116 |
OPEN 4 8 0 |
87 116 |
188 116 |
188 -116 |
87 -116 |
VALUE -61 152 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -59 49 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-135 0 -137.94 -15.75 |
T135 0 127.31 -15.35 |
PAD 0 5 |
-2 87 RF 90.000 213 0 0 N |
-1 0 R |
0 0 R |
21 93 RF 90.000 219 0 |
23 83 RF 90.000 209 0 |
ELYTA I 0 0 2 2 1 0 2 |
OPEN 6 8 0 |
-27 44 |
-101.43 44 |
-109.43 36 |
-109.43 -36 |
-101.43 -44 |
-27 -44 |
OPEN 4 8 0 |
27 44 |
107 44 |
107 -44 |
27 -44 |
VALUE -55.6 63.8 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -52.24 173.48 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-63 0 -65.94 -15.75 |
T63 0 55.31 -15.35 |
PAD 0 5 |
-2 65 S 0 N |
-1 0 R |
0 0 R |
21 71 S |
23 61 S |
ELYTB I 0 0 2 2 1 0 2 |
OPEN 6 8 0 |
-35 62 |
-95 62 |
-103 54 |
-103 -54 |
-95 -62 |
-35 -62 |
OPEN 4 8 0 |
35 62 |
103 62 |
103 -62 |
35 -62 |
VALUE -59.69 265.98 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -59.69 157.89 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-65 0 -67.94 -15.75 |
T65 0 57.31 -15.35 |
PAD 0 5 |
-2 55 RF 90.000 100 0 0 |
-1 0 R |
0 0 R |
21 61 RF 90.000 106 0 |
23 51 RF 90.000 96 0 |
ELYTC I 0 0 2 2 1 0 2 |
OPEN 6 8 0 |
-55 70 |
-145 70 |
-153 62.41 |
-153 -61.91 |
-145 -70 |
-55 -70 |
OPEN 4 8 0 |
55 70 |
153 70 |
153 -70 |
55 -70 |
VALUE -64.97 198.8 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -61.55 88.37 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-100 0 -102.94 -15.75 |
T100 0 92.31 -15.35 |
PAD 0 5 |
-2 85 RF 90.000 100 0 0 |
-1 0 R |
0 0 R |
21 91 RF 90.000 106 0 |
23 81 RF 90.000 96 0 |
ELYTD I 0 0 2 2 1 1 2 |
OPEN 6 8 0 |
-80 92 |
-170 92 |
-180 82 |
-180 -82 |
-170 -92 |
-78 -92 |
OPEN 4 8 0 |
80 92 |
180 92 |
180 -92 |
80 -92 |
-136.59 -15.94 0.000 26 60 8 N LEFT DOWN 0 |
Regular <PADS Stroke Font> |
K |
VALUE -55.71 114.39 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -56.97 228.14 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-126 0 -128.94 -15.75 |
T126 0 118.31 -15.35 |
PAD 0 5 |
-2 85 RF 90.000 120 0 0 |
-1 0 R |
0 0 R |
21 91 RF 90.000 126 0 |
23 81 RF 90.000 116 0 |
CE020X5 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
105 0 |
-105 0 |
VALUE -56 174 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -56 280 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-40 0 -43.78 -15.75 |
T40 0 31.97 -11.81 |
PAD 0 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
PAD 2 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
CE025X6 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
130 0 |
-130 0 |
VALUE -56 280 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -56 174 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-50 0 -53.78 -15.75 |
T50 0 41.97 -11.81 |
PAD 0 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
PAD 2 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
CE035X8 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
170 0 |
-170 0 |
VALUE -48.01 295.22 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -49.23 191.31 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-69 0 -72.78 -15.75 |
T69 0 60.97 -11.81 |
PAD 0 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
PAD 2 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
CE050X10 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
210 0 |
-210 0 |
VALUE -52.12 339.78 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -49.7 229.88 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-100 0 -103.78 -15.75 |
T100 0 91.97 -11.81 |
PAD 0 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
PAD 2 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
CE050X13 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
270 0 |
-270 0 |
VALUE -50 430 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -50 310 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-100 0 -103.78 -15.75 |
T100 0 91.97 -11.81 |
PAD 0 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
PAD 2 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
CE075X16 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
325 0 |
-325 0 |
VALUE -60 460 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -64.3 354.09 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-150 0 -153.78 -15.75 |
T150 0 141.97 -11.81 |
PAD 0 5 |
-2 80 R 45 |
-1 80 R |
0 80 R |
21 86 R |
28 86 R |
PAD 1 5 |
-2 80 S 40 |
-1 80 S |
0 80 S |
21 86 S |
28 86 S |
CE075X18 I 0 0 1 2 2 0 2 |
CIRCLE 2 8 0 |
367 0 |
-367 0 |
VALUE -58.64 391.11 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -60 500 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
T-150 0 -153.78 -15.75 |
T150 0 141.97 -11.81 |
PAD 0 5 |
-2 80 R 40 |
-1 80 R |
0 80 R |
21 86 R |
28 86 R |
PAD 1 5 |
-2 80 S 40 |
-1 80 S |
0 80 S |
21 86 S |
28 86 S |
CE020X5/L I 0 0 3 2 2 0 2 |
CLOSED 5 8 0 |
-105 -60 |
101 -60 |
101 -487 |
-105 -487 |
-105 -60 |
OPEN 2 8 0 |
-37 -40 |
-37 -60 |
OPEN 2 8 0 |
40 -40 |
40 -60 |
VALUE -56 280 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -56 174 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-40 0 -43.78 -15.75 |
T40 0 31.97 -11.81 |
PAD 0 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
PAD 1 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
CE025X6/L I 0 0 3 2 2 0 2 |
CLOSED 5 8 0 |
-129 -60 |
129 -60 |
129 -485 |
-129 -485 |
-129 -60 |
OPEN 3 8 0 |
-48 -40 |
-49 -60 |
-51 -59 |
OPEN 2 8 0 |
50 -40 |
50 -60 |
VALUE -56 280 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -56 174 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-50 0 -53.78 -15.75 |
T50 0 41.97 -11.81 |
PAD 0 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
PAD 2 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
CE035X8/L I 0 0 3 2 2 0 2 |
CLOSED 5 8 0 |
-168 -60 |
169 -60 |
169 -487 |
-168 -487 |
-168 -60 |
OPEN 2 8 0 |
-68 -40 |
-68 -60 |
OPEN 2 8 0 |
71 -40 |
71 -60 |
VALUE -48.01 295.22 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -49.23 191.31 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
T-69 0 -72.78 -15.75 |
T69 0 60.97 -11.81 |
PAD 0 5 |
-2 60 S 35 |
-1 60 S |
0 60 S |
21 65.91 S |
28 65.91 S |
PAD 2 5 |
-2 60 R 35 |
-1 60 R |
0 60 R |
21 65.91 R |
28 65.91 R |
CE050X10/L I 0 0 3 2 2 0 2 |
CLOSED 5 8 0 |
-210 -70 |
208 -70 |
208 -682 |
-210 -682 |
-210 -70 |
OPEN 2 8 0 |
-100 -40 |
-100 -70 |
OPEN 2 8 0 |
100 -40 |
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*PARTTYPE* ITEMS |
*REMARK* NAME DECALNM UNITS TYPE GATES SIGPINS PINNMS FLAGS ECO |
*REMARK* G/S SWAPTYPE PINS |
*REMARK* PIN.SWAPTYPE.PINTYPE.FUNCNAME |
*REMARK* SIGPIN PIN WIDTH SIGNAME |
C C0805:C0603:C1206:CK025:CK050:C0805/1206:C1210:C1812:C2220 I CAP 1 0 0 0 Y |
G 0 2 |
1.1.Z 2.1.Z |
C-ELYT ELYTA:ELYTB:ELYTC:ELYTD:CE020X5:CE025X6:CE035X8:CE050X10:CE050X13:CE075X16:CE075X18:CE020X5/L:CE025X6/L:CE035X8/L:CE050X10/L I CAP 1 0 2 0 Y |
G 0 2 |
1.0.U 2.0.U |
A C |
SCW2 ARK210/2 I CON 0 0 0 0 Y |
ARK210/2 ARK210/2 I CON 0 0 0 0 Y |
T-CEB TO92:TO92/B:TO92/BSMD:TO92/L:TO39:SOT37:SOT37/SMD I TRX 0 0 4 0 Y |
C E B 4 |
R R0805:R0603:R1206:RS025:RL090:RL140:RS040:R1812 I RES 1 0 0 0 Y |
G 0 2 |
1.0.Z 2.0.Z |
PB4PIN PUSH050X050SMD:PUSH120:PUSH120SQ:P-B1727:PUSH050X050 I SWI 0 0 0 0 Y |
DIP14_300 DIP14_300 I DIP 0 0 0 0 Y |
*PART* ITEMS |
*REMARK* REFNM PTYPENM X Y ORI GLUE MIRROR ALT CLSTID CLSTATTR BROTHERID LABELS |
*REMARK* .REUSE. INSTANCE RPART |
*REMARK* VISIBLE XLOC YLOC ORI LEVEL HEIGTH WIDTH MIRRORED HJUST VJUST RIGHTREADING |
*REMARK* FONTSTYLE FONTFACE |
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Part Type |
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Part Type |
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Part Type |
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VALUE -14 181 0.000 1 60 7.87 N LEFT UP |
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Regular <PADS Stroke Font> |
Part Type |
R4 R 0 0 0.000 U N 4 -1 0 -1 2 |
VALUE -51.18 78.74 0.000 1 60 7.87 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -59.06 188.98 0.000 1 60 7.87 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R5 R 0 0 0.000 U N 4 -1 0 -1 2 |
VALUE -51.18 78.74 0.000 1 60 7.87 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -59.06 188.98 0.000 1 60 7.87 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R6 R 0 0 0.000 U N 4 -1 0 -1 2 |
VALUE -51.18 78.74 0.000 1 60 7.87 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -59.06 188.98 0.000 1 60 7.87 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R7 R 0 0 0.000 U N 4 -1 0 -1 2 |
VALUE -51.18 78.74 0.000 1 60 7.87 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -59.06 188.98 0.000 1 60 7.87 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R8 R 0 0 0.000 U N 4 -1 0 -1 2 |
VALUE -51.18 78.74 0.000 1 60 7.87 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -59.06 188.98 0.000 1 60 7.87 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
R9 R 0 0 0.000 U N 4 -1 0 -1 2 |
VALUE -51.18 78.74 0.000 1 60 7.87 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
VALUE -59.06 188.98 0.000 1 60 7.87 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
SW1 PB4PIN 0 0 0.000 U N 4 -1 0 -1 2 |
VALUE -39 220 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -39 220 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
U1 DIP14_300 0 0 0.000 U N 0 -1 0 -1 2 |
VALUE -59.06 436.88 0.000 1 60 8 N LEFT UP |
Regular <PADS Stroke Font> |
Part Type |
VALUE -59.06 436.88 0.000 1 60 8 N LEFT DOWN |
Regular <PADS Stroke Font> |
Ref.Des. |
*CONNECTION* |
*REMARK* *SIGNAL* SIGNAME SIGFLAG COLOR |
*REMARK* REFNM.PIN .REUSE. INSTANCE RSIG REFNM.PIN .REUSE. INSTANCE RSIG |
*SIGNAL* GND 0 -2 |
R6.1 C3.2 |
R11.1 R6.1 |
R4.1 R11.1 |
R2.1 R4.1 |
R2.1 C2.C |
C2.C M1.2 |
R10.1 M1.2 |
U1.11 R10.1 |
R8.1 U1.11 |
J1.1 R8.1 |
*SIGNAL* N00814 0 -2 |
U1.5 SW1.2 |
U1.5 R6.2 |
R6.2 Q2.E |
C2.A Q2.E |
*SIGNAL* VCC 0 -2 |
C3.1 J1.2 |
SW1.1 C3.1 |
R3.2 SW1.1 |
R3.2 R1.2 |
R1.2 J2.1 |
U1.4 J2.1 |
R7.2 U1.4 |
Q2.C R7.2 |
*SIGNAL* N02087 0 -2 |
R5.1 U1.8 |
*SIGNAL* N02123 0 -2 |
Q2.B R5.2 |
*SIGNAL* N02699 0 -2 |
U1.7 R9.2 |
*SIGNAL* N01929 0 -2 |
U1.10 R2.2 |
R2.2 C1.2 |
*SIGNAL* N01826 0 -2 |
R3.1 R4.2 |
R4.2 U1.9 |
*SIGNAL* N02014 0 -2 |
R1.1 C1.1 |
C1.1 M1.1 |
*SIGNAL* N02635 0 -2 |
U1.6 R7.1 |
R7.1 R8.2 |
*SIGNAL* N02735 0 -2 |
R9.1 U1.3 |
U1.3 R10.2 |
*SIGNAL* N02885 0 -2 |
U1.1 Q1.B |
*SIGNAL* N03786 0 -2 |
J2.2 Q1.C |
*SIGNAL* N03815 0 -2 |
U1.2 Q1.E |
Q1.E R11.2 |
*MISC* MISCELLANEOUS PARAMETERS |
*REMARK* PARENT_KEYWORD PARENT_VALUE |
*REMARK* [ { |
*REMARK* CHILD_KEYWORD CHILD_VALUE |
*REMARK* [ CHILD_KEYWORD CHILD_VALUE |
*REMARK* [ { |
*REMARK* GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...] |
*REMARK* } ]] |
*REMARK* } ] |
RULES_SECTION MILS |
{ |
NET_CLASS DATA |
GROUP DATA |
DESIGN RULES |
{ |
RULE_SET (1) |
{ |
FOR : |
{ |
DEFAULT : |
} |
AGAINST : |
{ |
DEFAULT : |
} |
LAYER 0 |
CLEARANCE_RULE : |
{ |
TRACK_TO_TRACK 6 |
VIA_TO_TRACK 6 |
VIA_TO_VIA 6 |
PAD_TO_TRACK 6 |
PAD_TO_VIA 6 |
PAD_TO_PAD 6 |
SMD_TO_TRACK 6 |
SMD_TO_VIA 6 |
SMD_TO_PAD 6 |
SMD_TO_SMD 6 |
COPPER_TO_TRACK 6 |
COPPER_TO_VIA 6 |
COPPER_TO_PAD 6 |
COPPER_TO_SMD 6 |
TEXT_TO_TRACK 6 |
TEXT_TO_VIA 6 |
TEXT_TO_PAD 6 |
TEXT_TO_SMD 6 |
OUTLINE_TO_TRACK 6 |
OUTLINE_TO_VIA 6 |
OUTLINE_TO_PAD 6 |
OUTLINE_TO_SMD 6 |
OUTLINE_TO_COPPER 6 |
DRILL_TO_TRACK 6 |
DRILL_TO_VIA 6 |
DRILL_TO_PAD 6 |
DRILL_TO_SMD 6 |
DRILL_TO_COPPER 6 |
SAME_NET_SMD_TO_VIA 6 |
SAME_NET_SMD_TO_CRN 6 |
SAME_NET_VIA_TO_VIA 6 |
SAME_NET_PAD_TO_CRN 6 |
MIN_TRACK_WIDTH 12 |
REC_TRACK_WIDTH 12 |
MAX_TRACK_WIDTH 12 |
DRILL_TO_DRILL 6 |
BODY_TO_BODY 6 |
SAME_NET_TRACK_TO_CRN 0 |
} |
} |
RULE_SET (2) |
{ |
FOR : |
{ |
DEFAULT : |
} |
AGAINST : |
{ |
DEFAULT : |
} |
LAYER 0 |
HIGH_SPEED_RULE : |
{ |
MIN_LENGTH 0 |
MAX_LENGTH 50000 |
STUB_LENGTH 0 |
PARALLEL_LENGTH 1000 |
PARALLEL_GAP 200 |
TANDEM_LENGTH 1000 |
TANDEM_GAP 200 |
MIN_DELAY 0.000000 |
MAX_DELAY 10.000000 |
MIN_CAPACITANCE 0.000000 |
MAX_CAPACITANCE 10.000000 |
MIN_IMPEDANCE 50.000000 |
MAX_IMPEDANCE 150.000000 |
SHIELD_NET * |
SHIELD_GAP 200 |
MATCH_LENGTH_TOLERANCE 200 |
} |
} |
RULE_SET (3) |
{ |
FOR : |
{ |
DEFAULT : |
} |
AGAINST : |
{ |
DEFAULT : |
} |
LAYER 0 |
ROUTE_RULE : |
{ |
LENGTH_MINIMIZATION_TYPE 1 |
VIA_SHARE Y |
TRACE_SHARE Y |
AUTO_ROUTE Y |
RIPUP Y |
SHOVE Y |
ROUTE_PRIORITY 3 |
VALID_LAYER 1 |
VALID_LAYER 2 |
VALID_VIA_TYPE STANDARDVIA |
} |
} |
} |
} |
*MISC* MISCELLANEOUS PARAMETERS |
ATTRIBUTES DICTIONARY |
{ |
ATTRIBUTE Value |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE DECAL |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE Tolerance |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE Part Number |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM N |
HIDDEN N |
} |
ATTRIBUTE Description |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE DECAL |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM N |
HIDDEN N |
} |
ATTRIBUTE Cost |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM N |
HIDDEN N |
} |
ATTRIBUTE Manufacturer #1 |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM N |
HIDDEN N |
} |
ATTRIBUTE Manufacturer #2 |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM N |
HIDDEN N |
} |
ATTRIBUTE PowerGround |
{ |
TYPE BOOLEAN |
INHERITANCE NET NETCLASS PCB |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE Voltage |
{ |
TYPE QUANTITY |
QUANTITY Voltage |
ABBR V |
UNIT Volt |
MIN -100kV |
MAX 100kV |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE Geometry.Height |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 25000.00mil |
INHERITANCE PCB |
INHERITANCE PART PARTTYPE DECAL |
ECO_REGISTRATION N |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE DFT.Nail Count Per Net |
{ |
TYPE INTEGER |
MIN 0 |
MAX 1000 |
INHERITANCE NET NETCLASS PCB |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE DFT.Nail Diameter |
{ |
TYPE FREETEXT N |
INHERITANCE PIN |
INHERITANCE VIA |
ECO_REGISTRATION N |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE DFT.Nail Number |
{ |
TYPE FREETEXT N |
INHERITANCE PIN |
INHERITANCE VIA |
ECO_REGISTRATION N |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Model |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Model File |
{ |
TYPE FREETEXT N |
INHERITANCE PART PARTTYPE |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Sim Direction |
{ |
TYPE LIST N |
{ |
SIM_BOTH |
SIM_IN |
SIM_OUT |
} |
INHERITANCE PIN |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Frequency |
{ |
TYPE QUANTITY |
QUANTITY Frequency |
ABBR Hz |
UNIT Hertz |
MIN 0Hz |
MAX 1000GHz |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Duty Cycle |
{ |
TYPE QUANTITY |
QUANTITY |
ABBR % |
UNIT percent |
MIN 0% |
MAX 100% |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Signal Type |
{ |
TYPE LIST N |
{ |
Address |
Analog High Speed |
Analog Low Speed |
Clock |
Data |
Do Not Analyze |
Power Supply |
Strobe |
} |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Default IC.Model |
{ |
TYPE FREETEXT N |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Default IC.Model File |
{ |
TYPE FREETEXT N |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE HyperLynx.Default IC.Model Pin |
{ |
TYPE FREETEXT N |
INHERITANCE NET NETCLASS |
ECO_REGISTRATION Y |
READONLY N |
SYSTEM Y |
HIDDEN N |
} |
ATTRIBUTE Strategy.Fanout.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Fanout.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Patterns.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Route.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Optimize.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Miters.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.TestPoint.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Center.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.Pass |
{ |
TYPE LIST N |
{ |
No |
Yes |
Done |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.Protect |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.Pause |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.Intensity |
{ |
TYPE LIST N |
{ |
Low |
Medium |
High |
} |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.PlanePriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.Priority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PART |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.DiffPairPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET |
INHERITANCE PINPAIR |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Strategy.Tune.MLGPriority |
{ |
TYPE INTEGER |
MIN 0 |
INHERITANCE NET NETCLASS PCB |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.FormatId |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.ChipLength |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.ChipWidth |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.ChipHeight |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WBRules.MinLength |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WBRules.MaxLength |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WBRules.WToWDistance |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WBRules.WBtoPad |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WBRules.MaxAngle |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.SBPCount |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.SBP1 |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.CBPCount |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.CBP1 |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WBCount |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.WB1 |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.SBPGuideCount |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.SBPGuide1 |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE DIE.CBPAssignment1 |
{ |
TYPE FREETEXT N |
INHERITANCE DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Marker_Shape |
{ |
TYPE FREETEXT N |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Text_NumberPrecision |
{ |
TYPE FREETEXT N |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Text_AngularPrecision |
{ |
TYPE FREETEXT N |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Text_Suffix |
{ |
TYPE FREETEXT N |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Text_Layer |
{ |
TYPE INTEGER |
MIN 0 |
MAX 250 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Line_Layer |
{ |
TYPE INTEGER |
MIN 0 |
MAX 250 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE AutoDimensioning.Preview_Type |
{ |
TYPE INTEGER |
MIN 1 |
MAX 5 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.PadEntry.Side |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.PadEntry.Corner |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.PadEntry.AnyAngle |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.PadEntry.Soft |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.ViaAtSMD |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.ViaAtSMD.FitInside |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.ViaAtSMD.Center |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.ViaAtSMD.Ends |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Alignment |
{ |
TYPE LIST N |
{ |
Aligned |
Alternate |
} |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Alignment.Multi-Row |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Direction |
{ |
TYPE LIST N |
{ |
Inside |
Outside |
Both Sides |
} |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.ViaSpacing |
{ |
TYPE LIST N |
{ |
Use Grid |
1 Trace |
2 Trace |
} |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Sharing.Pin |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Sharing.SMD |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Sharing.Via |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Sharing.Trace |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Nets.Plane |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Nets.Signal |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Nets.UnusedPins |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Length.Unlimited |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Fanout.Length.Maximum |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 2000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Trace.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Via.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Via.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Pad.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Pad.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Pad.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.SMD.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.SMD.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.SMD.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.SMD.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Copper.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Copper.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Copper.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Copper.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Text.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Text.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Text.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Text.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Board.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Board.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Board.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Board.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Drill.Trace |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Drill.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Drill.Pad |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Clearance.Drill.SMD |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.SMD.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.SMD.Crn |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.Via.Via |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.Pad.Crn |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.SameNet.Trace.Crn |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 1000.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Width.Minimum |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 250.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Width.Recommended |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 250.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Rules.Width.Maximum |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 250.00mil |
INHERITANCE PCB |
INHERITANCE PART DECAL |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Placement.Grid.Use |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Placement.Grid.X |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 2000.00mil |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Placement.Grid.Y |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 2000.00mil |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Accordion.Amplitude.Min |
{ |
TYPE INTEGER |
MIN 3 |
MAX 30 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Accordion.Gap.Min |
{ |
TYPE INTEGER |
MIN 1 |
MAX 10 |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Routing.MaxChannelWidth |
{ |
TYPE QUANTITY |
QUANTITY Size/Dimension |
ABBR |
UNIT |
MIN 0.00mil |
MAX 10000.00mil |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Routing.SoftLengthRrules |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Routing.MeanderBeforeTune |
{ |
TYPE BOOLEAN |
INHERITANCE PCB |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE MatchLength.Name |
{ |
TYPE FREETEXT N |
INHERITANCE NET NETCLASS |
INHERITANCE PINPAIR GROUP |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Planning.Scheduled |
{ |
TYPE BOOLEAN |
INHERITANCE NET |
ECO_REGISTRATION Y |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Library.Timestamp |
{ |
TYPE FREETEXT N |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
ATTRIBUTE Design.Timestamp |
{ |
TYPE FREETEXT N |
ECO_REGISTRATION N |
READONLY Y |
SYSTEM Y |
HIDDEN Y |
} |
} |
ATTRIBUTE VALUES |
{ |
PART C1 |
{ |
Value CK050 |
} |
PART C2 |
{ |
Value 47UF |
} |
PART C3 |
{ |
Value 100NF |
} |
PART J1 |
{ |
Value POWER |
} |
PART J2 |
{ |
Value ARK210/2 |
} |
PART M1 |
{ |
Value MIKE |
} |
PART Q1 |
{ |
Value BC547 |
} |
PART Q2 |
{ |
Value BC547 |
} |
PART R1 |
{ |
Value 15K |
} |
PART R10 |
{ |
Value 10K |
} |
PART R11 |
{ |
Value 18 |
} |
PART R2 |
{ |
Value M1 |
} |
PART R3 |
{ |
Value 22K |
} |
PART R4 |
{ |
Value 5K6 |
} |
PART R5 |
{ |
Value 6K8 |
} |
PART R6 |
{ |
Value 1M |
} |
PART R7 |
{ |
Value M39 |
} |
PART R8 |
{ |
Value M1 |
} |
PART R9 |
{ |
Value M1 |
} |
PART SW1 |
{ |
Value PUSH050X050 |
} |
PART U1 |
{ |
Value LM124 |
} |
DECAL C0805 |
{ |
Description keramicky kondenzator SMD velikost 0805 |
Geometry.Height 1.5mm |
Value ??? |
} |
DECAL C0603 |
{ |
Description keramicky kondenzator SMD velikost 0603 |
Geometry.Height 1.5mm |
Value ??? |
} |
DECAL C1206 |
{ |
Description keramicky kondenzator SMD velikost 1206 |
Geometry.Height 1.5mm |
Value ??? |
} |
DECAL CK025 |
{ |
Description kramicky kondenzator roztec 2.54 mm ,100 mils |
Geometry.Height 8mm |
Value ??? |
} |
DECAL CK050 |
{ |
Description keramicky kondenzator roztec 5,08 mm ,200 mils |
Geometry.Height 8mm |
Value ??? |
} |
DECAL C0805/1206 |
{ |
Description univerzalni plosky pro C0805 a C1206 |
Geometry.Height 1.50000mm |
Value ??? |
} |
DECAL C1210 |
{ |
Description keramicky kondenzator SMD velikost 1210 |
Geometry.Height 2mm |
Value ??? |
} |
DECAL C1812 |
{ |
Description keramicky kondenzator SMD velikost 1812 |
Geometry.Height 2mm |
Value ??? |
} |
DECAL C2220 |
{ |
Description keramicky kondenzator SMD velikost 2220 |
Geometry.Height 2mm |
Value ??? |
} |
DECAL ELYTA |
{ |
Description elektrolyt SMD velikost A |
Geometry.Height 1.8 mm |
Value ??? |
} |
DECAL ELYTB |
{ |
Description elektrolyt SMD velikost B |
Geometry.Height 2 mm |
Value ??? |
} |
DECAL ELYTC |
{ |
Description elektrolyt SMD velikost C |
Geometry.Height 2.8 mm |
Value ??? |
} |
DECAL ELYTD |
{ |
Description elektrolyt SMD velikost D |
Geometry.Height 3 mm |
Value ??? |
} |
DECAL CE020X5 |
{ |
Description Elyt prumer 5mm, roztec 2.032mm - 80 mils |
Geometry.Height 12 mm |
Value ??? |
} |
DECAL CE025X6 |
{ |
Description Elyt prumer 6.3mm, roztec 2.54mm - 100 mils |
Geometry.Height 12 mm |
Value ??? |
} |
DECAL CE035X8 |
{ |
Description Elyt prumer 8 mm, roztec3.505 mm - 138 mils |
Geometry.Height 12 mm |
Value ??? |
} |
DECAL CE050X10 |
{ |
Description Elyt prumer 10mm, roztec 5.08mm - 200 mils |
Geometry.Height 17 mm |
Value ??? |
} |
DECAL CE050X13 |
{ |
Description Elyt prumer 13mm, roztec 5.08mm - 200 mils |
Geometry.Height 27 mm |
Value ??? |
} |
DECAL CE075X16 |
{ |
Description Elyt prumer 16mm, roztec 7.5mm - 300 mils |
Geometry.Height 26 mm |
Value ??? |
} |
DECAL CE075X18 |
{ |
Description Elyt prumer 18mm, roztec 7.5mm - 300 mils |
Geometry.Height 43 mm |
Value ??? |
} |
DECAL CE020X5/L |
{ |
Description Elyt prumer 5mm na lezato, roztec 2.032mm - 80 mils |
Geometry.Height 5.5 mm |
Value ??? |
} |
DECAL CE025X6/L |
{ |
Description Elyt prumer 6.3mm na lezato, roztec 2.54mm - 100 mils |
Geometry.Height 6.5 mm |
Value ??? |
} |
DECAL CE035X8/L |
{ |
Description Elyt prumer 8 mm na lezato, roztec3.505 mm - 138 mils |
Geometry.Height 8.5 mm |
Value ??? |
} |
DECAL CE050X10/L |
{ |
Description Elyt prumer 10mm na lezato, roztec 5.08mm - 200 mils |
Geometry.Height 10.5 mm |
Value ??? |
} |
DECAL ARK210/2 |
{ |
Description svorkovnice se dvema piny, roztec 5.08 mm - 200 mils |
Geometry.Height 13 mm |
Value ??? |
} |
DECAL TO92 |
{ |
Description tranzistorove pouzdro TO92, kolektor uprostred |
Geometry.Height 10mm |
Value ??? |
} |
DECAL TO92/B |
{ |
Description TO92, kolektor uprostred, pro bastleni |
Geometry.Height 10mm |
Value ??? |
} |
DECAL TO92/BSMD |
{ |
Description TO92, kolektor uprostred, vyvody v jedne rade |
Geometry.Height 10mm |
Value ??? |
} |
DECAL TO92/L |
{ |
Description TO92, kolektor uprostred, vyvody v jedne rade |
Geometry.Height 10mm |
Value ??? |
} |
DECAL TO39 |
{ |
Description velke kovove pouzdro TO39 |
Geometry.Height 10 mm |
} |
DECAL SOT37 |
{ |
Description pouzdro pro tranzistory BFR... |
Geometry.Height 2.5 mm |
} |
DECAL SOT37/SMD |
{ |
Description pouzdro pro tranzistory BFR... montaz SMD |
Geometry.Height 2.5 mm |
} |
DECAL R0805 |
{ |
Description rezistor SMD velikost 0805 |
Geometry.Height 1mm |
Value ??? |
} |
DECAL R0603 |
{ |
Description rezistor SMD velikost 0603 |
Geometry.Height 1mm |
Value ??? |
} |
DECAL R1206 |
{ |
Description rezistor SMD velikost 1206 |
Geometry.Height 1mm |
Value ??? |
} |
DECAL RS025 |
{ |
Description bezny rezistor nastojato roztec 2,54 mm, 100 mils |
Geometry.Height 9 mm |
Value ??? |
} |
DECAL RL090 |
{ |
Description bezny rezistor roztec 8.89mm, 350mils |
Geometry.Height 3mm |
Value ??? |
} |
DECAL RL140 |
{ |
Description rezistor 2W nalezato roztec 13.97mm, 550mils |
Geometry.Height 4.6mm |
Value ??? |
} |
DECAL RS040 |
{ |
Description rezistor 2W nastojato, roztec 3.81 mm ,150 mils |
Geometry.Height 15mm |
Value ??? |
} |
DECAL R1812 |
{ |
Description rezistor SMD velikost 1812 |
Geometry.Height 1mm |
Value ??? |
} |
DECAL PUSH050X050SMD |
{ |
Description ctvercove SMD spinaci tlacitko , vyvody 1-4 a 2-3 propojeny |
Geometry.Height 5.00000mm |
Value ??? |
} |
DECAL PUSH120 |
{ |
Description Kulate tlacitko s vyvody v rosteci 5x5mm |
Geometry.Height 8 mm |
} |
DECAL PUSH120SQ |
{ |
Description Kulate tlacitko s vyvody v rastru 5x5mm s hranatym hmatnikem |
Geometry.Height 8 mm |
} |
DECAL P-B1727 |
{ |
Description hranate tlacitko 10x10mm |
Geometry.Height 8 mm |
} |
DECAL PUSH050X050 |
{ |
Description ctvercove spinaci tlacitko , vyvody 1-4 a 2-3 propojeny |
Geometry.Height 5.00000mm |
} |
DECAL DIP14_300 |
{ |
Description pozdro DIP14 roztec 7.62 mm - 300 mils |
Geometry.Height 6 mm |
Value ??? |
} |
PARTTYPE C |
{ |
Description ruzne druhy kondenzatoru |
Value ??? |
} |
PARTTYPE C-ELYT |
{ |
Description ruzne druhy elektrolytickych kondenzatoru |
Value ??? |
} |
PARTTYPE T-CEB |
{ |
Description Tanzistory s poradim nozicek 1=C 2-E 3=B |
Value ??? |
} |
PARTTYPE R |
{ |
Description rezistory ruznych typu |
Value ??? |
} |
PARTTYPE DIP14_300 |
{ |
Value ??? |
} |
PCB DEFAULT |
{ |
Accordion.Amplitude.Min 3 |
Accordion.Gap.Min 1 |
AutoDimensioning.Line_Layer 24 |
AutoDimensioning.Marker_Shape YYNNNY |
AutoDimensioning.Preview_Type 1 |
AutoDimensioning.Text_AngularPrecision 0 0 0 |
AutoDimensioning.Text_Layer 24 |
AutoDimensioning.Text_NumberPrecision 0 1 2 |
AutoDimensioning.Text_Suffix mil##mm##" |
Placement.Grid.Use No |
Placement.Grid.X 100.00mil |
Placement.Grid.Y 100.00mil |
Routing.MaxChannelWidth 100.00mil |
Routing.MeanderBeforeTune No |
Routing.SoftLengthRrules Yes |
Rules.ViaAtSMD No |
Rules.Fanout.Alignment Alternate |
Rules.Fanout.Direction Both Sides |
Rules.Fanout.ViaSpacing Use Grid |
Rules.Fanout.Alignment.Multi-Row Yes |
Rules.Fanout.Length.Maximum 250.00mil |
Rules.Fanout.Length.Unlimited Yes |
Rules.Fanout.Nets.Plane Yes |
Rules.Fanout.Nets.Signal No |
Rules.Fanout.Nets.UnusedPins No |
Rules.Fanout.Sharing.Pin Yes |
Rules.Fanout.Sharing.SMD Yes |
Rules.Fanout.Sharing.Trace Yes |
Rules.Fanout.Sharing.Via Yes |
Rules.PadEntry.AnyAngle Yes |
Rules.PadEntry.Corner Yes |
Rules.PadEntry.Side Yes |
Rules.PadEntry.Soft Yes |
Rules.ViaAtSMD.Center Yes |
Rules.ViaAtSMD.Ends Yes |
Rules.ViaAtSMD.FitInside Yes |
} |
} |
*END* OF ASCII OUTPUT FILE |
/schemata/therm.err |
---|
0,0 → 1,15 |
THERMAL RELIEF ERRORS REPORT -- default_blz1.pcb -- Wed Jun 21 22:19:44 2006 |
Drilled pads with Nondrilled pads with |
less than 50% thermal extensions less than 50% thermal extensions |
Report of Thermal Spokes Generator. |
On Bottom: |
U1.11 (19650, 17400) # = 1 |
C2.C (20543.94, 17352.31) # = 1 |
Total Drilled pads: 2 Total Nondrilled pads: 0 |