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Ignore whitespace Rev 349 → Rev 350

/schemata/mereni/VLF/RECEIVER.DSN
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/schemata/mereni/VLF/PCB/receiver.pcb
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/schemata/mereni/VLF/SCH/APLIFIER.DSN
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/schemata/mereni/VLF/SCH/APLIFIER.asc
0,0 → 1,46
*PADS-PCB*
*PART*
C1 C,15nF@CK050
C2 C,100nF@CK050
C3 C,1nF@CK050
C4 C,100pF@CK050
C5 C,100nF@CK050
C6 C,100nF@CK050
C8 C-ELYT,330uF@CE035X8
D1 D,1N4007@DO41
D2 D,1N4007@DO41
J2 SCW2,ARK210/2@ARK210/2
J3 SCW2,ARK210/2@ARK210/2
J4 SCW2,ARK210/2@ARK210/2
L1 L,3900uH@LL150
Q1 T-FET-GDS,BF245@TO92
R1 R,100@RL090
R2 R,6k8@RL090
R3 R,6k8@RL090
R4 R,10k@RL090
R5 R,100k@RL090
U1 DIP8_300,NE5534@DIP8_300
 
*NET*
*SIGNAL* N00613
C3.1 R4.2
*SIGNAL* N00485
U1.6 R5.2 C4.2 C5.1
*SIGNAL* N00458
U1.2 R5.1 C3.2 C4.1
*SIGNAL* N00764
C5.2 J2.1
*SIGNAL* N01016
D1.A J3.2 D2.C Q1.G
*SIGNAL* N00011
L1.2 C1.2 Q1.S C2.1
*SIGNAL* GND
R1.1 J3.1 J4.1 J2.2 C1.1 R4.1 C8.C C6.1
D1.C U1.4 R3.1 D2.A
*SIGNAL* N00120
R1.2 Q1.D
*SIGNAL* VCC
L1.1 R2.2 C8.A C6.2 U1.7 J4.2
*SIGNAL* N00063
R2.1 C2.2 R3.2 U1.3
*END*
/schemata/mereni/VLF/SIM/RECEIVER.DSN
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/schemata/mereni/VLF/SIM/RECEIVER_0.DBK
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/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.1OP
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/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.cir
0,0 → 1,18
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
 
** Creating circuit file "test.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
 
*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_10.5_Demo\tools\PSpice\PSpice.ini file:
.lib "nom.lib"
 
*Analysis directives:
.AC LIN 5000 10000 30000
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
 
 
.END
/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.dat
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/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.mif
0,0 → 1,2
lib=C:\OrCAD\OrCAD_10.5_Demo\tools\PSpice\Library\breakout.lib, offset=475, size=23
lib=C:\OrCAD\OrCAD_10.5_Demo\tools\PSpice\Library\eval.lib, offset=33414, size=138
/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.mrk
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+application/octet-stream
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/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.out
0,0 → 1,154
**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
 
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
 
 
**** CIRCUIT DESCRIPTION
 
 
******************************************************************************
 
 
 
 
** Creating circuit file "test.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
 
*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_10.5_Demo\tools\PSpice\PSpice.ini file:
.lib "nom.lib"
 
*Analysis directives:
.AC LIN 5000 10000 30000
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
 
 
 
**** INCLUDING SCHEMATIC1.net ****
* source RECEIVER
C_C1 0 N03478 15nF
V_V2 N03432 0 DC 0Vdc AC 1Vac
R_R1 0 N03490 100
E_U1 N03510 0 VALUE {LIMIT(V(N03718,N03634)*1E6,-15V,+15V)} _U1 N03718
+ N03634 1G
 
R_R4 N03718 N03462 6.8k
R_R5 0 N03718 6.8k
C_C5 N03478 N03718 100nF
C_C2 N03518 N03510 1n
R_R6 N03774 N03782 20k
R_R7 0 N03774 100000k
V_V1 N03462 0 12Vdc
R_R2 N03634 N03510 100k
L_L1 N03462 N03478 3900uH
C_C3 N03634 N03510 270pF
X_TX1 N03518 0 N03782 N03774 SCHEMATIC1_TX1
J_J1 N03478 N03432 N03490 JbreakN
C_C4 N03622 N03634 1nF
R_R3 0 N03622 10k
 
.subckt SCHEMATIC1_TX1 1 2 3 4
L1_TX1 1 2 1000
L2_TX1 3 4 1000
K_TX1 L1_TX1 L2_TX1 1 KRM8PL_3C8
.ends SCHEMATIC1_TX1
 
**** RESUMING test.cir ****
.END
**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
 
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
 
 
**** Junction FET MODEL PARAMETERS
 
 
******************************************************************************
 
 
 
 
JbreakN
NJF
VTO -2
BETA 100.000000E-06
 
**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
 
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
 
 
**** Ferromagnetic Core MODEL PARAMETERS
 
 
******************************************************************************
 
 
 
 
KRM8PL_3C8
LEVEL 2
AREA .63
PATH 3.84
MS 415.200000E+03
A 44.82
C .4112
K 25.74
 
**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
 
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
 
 
**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C
 
 
******************************************************************************
 
 
 
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
 
 
(N03432) 0.0000 (N03462) 12.0000 (N03478) 12.0000 (N03490) .0385
 
(N03510) 6.0000 (N03518) 0.0000 (N03622) 0.0000 (N03634) 6.0000
 
(N03718) 6.0000 (N03774) 0.0000 (N03782) 0.0000
 
 
 
 
VOLTAGE SOURCE CURRENTS
NAME CURRENT
 
V_V2 1.206E-11
V_V1 -1.267E-03
 
TOTAL POWER DISSIPATION 1.52E-02 WATTS
 
 
 
JOB CONCLUDED
**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
 
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
 
 
**** JOB STATISTICS SUMMARY
 
 
******************************************************************************
 
 
 
Total job time (using Solver 1) = .89
/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.out.1
0,0 → 1,64
**** 08/21/07 14:53:51 ************** PSpice Lite (Jan 2005) *****************
 
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
 
 
**** CIRCUIT DESCRIPTION
 
 
******************************************************************************
 
 
 
 
** Creating circuit file "test.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
 
*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_10.5_Demo\tools\PSpice\PSpice.ini file:
.lib "nom.lib"
 
*Analysis directives:
.AC LIN 7000 0 250000
-------------$
ERROR -- Invalid value
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
 
 
 
**** INCLUDING SCHEMATIC1.net ****
* source RECEIVER
C_C1 0 N03478 22nF
V_V2 N03432 0 DC 0Vdc AC 1Vac
R_R1 0 N03490 10
E_U1 N03510 0 VALUE {LIMIT(V(N03718,N03634)*1E6,-15V,+15V)} _U1 N03718
+ N03634 1G
 
R_R4 N03718 N03462 4.7k
R_R5 0 N03718 4.7k
C_C5 N03478 N03718 100nF
C_C2 N03518 N03510 1n
R_R6 N03774 N03782 10k
R_R7 0 N03774 100000k
V_V1 N03462 0 12Vdc
R_R2 N03634 N03510 100k
L_L1 N03462 N03478 3mH
C_C3 N03634 N03510 1n
X_TX1 N03518 0 N03782 N03774 SCHEMATIC1_TX1
J_J1 N03478 N03432 N03490 JbreakN
C_C4 N03622 N03634 47nF
R_R3 0 N03622 10k
 
.subckt SCHEMATIC1_TX1 1 2 3 4
L1_TX1 1 2 100
L2_TX1 3 4 100
K_TX1 L1_TX1 L2_TX1 1 KRM8PL_3C8
.ends SCHEMATIC1_TX1
 
**** RESUMING test.cir ****
.END
/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.prb
0,0 → 1,51
[DISPLAYS]
BEGIN DISPLAY LAST SESSION
ANALYSIS AC_SWEEP
SYMBOL ALWAYS
TRACECOLORSCHEME NORMAL
BEGIN ANAPLOT 1
ACTIVE
XBASE
BEGIN XAXIS
XAXISUSERNAME 0 (null)
RANGEFLAG AUTO
TYPE LINEAR
UNIT H
BEGIN GRIDS
AUTOMATIC
MAJORNUMBERS
MAJORSTYLE LINES
MAJORPATTERN SOLID
MINORSTYLE LINES
MINORPATTERN DOT
END GRIDS
END XAXIS
BEGIN YAXIS 1
YAXISSIDE LEFT
ACTIVE
RANGEFLAG AUTO
TYPE LINEAR
UNIT V
BEGIN GRIDS
AUTOMATIC
MAJORNUMBERS
MAJORSTYLE LINES
MAJORPATTERN SOLID
MINORSTYLE LINES
MINORPATTERN DOT
END GRIDS
BEGIN TRACE V(C5:1)
MARKERID 3
TRACEADDEXT
END TRACE V(C5:1)
BEGIN TRACE V(R2:2)
MARKERID 5
TRACEADDEXT
END TRACE V(R2:2)
BEGIN TRACE V(TX1:3)
MARKERID 6
TRACEADDEXT
END TRACE V(TX1:3)
END YAXIS 1
END ANAPLOT 1
END DISPLAY LAST SESSION
/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test.sim
0,0 → 1,124
@OrCAD Simulation Server Version: 1.0
 
@Settings: 2 1
@General:
ProfileName= "test"
ProfileFile= "test.sim"
Connectivity= "SCHEMATIC1.net"
NetlistFile= "test.cir"
DataFile= "test.dat"
OutFile= "test.out"
Notes=
@#$BEGINNOTES
@#$ENDNOTES
@End General
@Analysis: 0 0
+0 0 0
+0 "1000ns"
+1 ""
+2 "0"
+3 ""
+4 ""
+5 ""
+6 ""
@End Analysis
@Analysis: 1 1
+0 0 0
+0 "5000"
+1 "10000"
+2 "30000"
+3 ""
+4 ""
+5 ""
@End Analysis
@Analysis: 2 0
+0 0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
+6 ""
+7 ""
@End Analysis
@Analysis: 3 0
+0 0 0
+0 ""
+1 ""
+2 ""
@End Analysis
@Analysis: 4 0
+0 0 1 0 0 0 2 0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
+6 ""
+7 ""
LoadFile 0 ""
SaveFile 0 ""
@End Analysis
@Analysis: 5 0
+0 0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
+6 ""
+7 ""
@End Analysis
@Analysis: 6 0
+1
+0 ""
@End Analysis
@Analysis: 7 0
+0 0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
@End Analysis
@Analysis: 8 0
+0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
@End Analysis
@Analysis: 9 0
+0 ""
@End Analysis
@Analysis: 10 0
+0 0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
+6 ""
+7 ""
@End Analysis
@Analysis: 11 1
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@End Analysis
@Analysis: 12 0
+2236960 0
@End Analysis
@Analysis: 13 1
+0 1 1 0
@End Analysis
@Analysis: 14 1
+1 1 1 "*"
@End Analysis
@Analysis: 15 0
@End Analysis