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Ignore whitespace Rev 351 → Rev 352

/schemata/mereni/VLF/SCH/APLIFIER.BOM
0,0 → 1,30
VLF receiver Revised: Thursday, August 23, 2007
Antenna preamp Revision: A
 
 
 
 
 
 
 
Bill Of Materials August 23,2007 18:09:26 Page1
 
Quantity Reference Part PCB Footprint
______________________________________________
 
1 C1 15nF CK050
3 C2,C5,C6 100nF CK050
1 C3 4,7nF CK050
1 C4 100pF CK050
1 C8 330uF CE035X8
2 D1,D2 1N4007 DO41
1 J2 output ARK210/2
1 J3 antenna loop ARK210/2
1 J4 Power ARK210/2
1 L1 3900uH LL150
1 Q1 BF245 TO92
1 R1 100 RL090
2 R2,R3 6k8 RL090
1 R4 10k RL090
1 R5 100k RL090
1 U1 NE5534 DIP8_300
/schemata/mereni/VLF/SCH/APLIFIER.DSN
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/schemata/mereni/VLF/SCH/APLIFIER.xls
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/schemata/mereni/VLF/SIM/RECEIVER.DSN
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/schemata/mereni/VLF/SIM/RECEIVER_0.DBK
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/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.1OP
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/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.cir
1,4 → 1,4
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-pspicefiles\schematic1\test.sim ]
 
** Creating circuit file "test.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.dat
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/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.mrk
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/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.out
1,7 → 1,7
**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
**** 08/23/07 17:58:38 ************** PSpice Lite (Jan 2005) *****************
 
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-pspicefiles\schematic1\test.sim ]
 
 
**** CIRCUIT DESCRIPTION
31,7 → 31,7
**** INCLUDING SCHEMATIC1.net ****
* source RECEIVER
C_C1 0 N03478 15nF
V_V2 N03432 0 DC 0Vdc AC 1Vac
V_V2 N03432 0 DC 0Vdc AC 0.001Vac
R_R1 0 N03490 100
E_U1 N03510 0 VALUE {LIMIT(V(N03718,N03634)*1E6,-15V,+15V)} _U1 N03718
+ N03634 1G
44,11 → 44,11
R_R7 0 N03774 100000k
V_V1 N03462 0 12Vdc
R_R2 N03634 N03510 100k
L_L1 N03462 N03478 3900uH
C_C3 N03634 N03510 270pF
L_L1 N03462 N03478 4900uH
C_C3 N03634 N03510 100pF
X_TX1 N03518 0 N03782 N03774 SCHEMATIC1_TX1
J_J1 N03478 N03432 N03490 JbreakN
C_C4 N03622 N03634 1nF
C_C4 N03622 N03634 4.7nF
R_R3 0 N03622 10k
 
.subckt SCHEMATIC1_TX1 1 2 3 4
60,9 → 60,9
**** RESUMING test.cir ****
.END
**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
**** 08/23/07 17:58:38 ************** PSpice Lite (Jan 2005) *****************
 
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-pspicefiles\schematic1\test.sim ]
 
 
**** Junction FET MODEL PARAMETERS
79,9 → 79,9
BETA 100.000000E-06
 
**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
**** 08/23/07 17:58:38 ************** PSpice Lite (Jan 2005) *****************
 
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-pspicefiles\schematic1\test.sim ]
 
 
**** Ferromagnetic Core MODEL PARAMETERS
102,9 → 102,9
K 25.74
 
**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
**** 08/23/07 17:58:38 ************** PSpice Lite (Jan 2005) *****************
 
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-pspicefiles\schematic1\test.sim ]
 
 
**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C
138,9 → 138,9
 
JOB CONCLUDED
**** 08/21/07 15:28:32 ************** PSpice Lite (Jan 2005) *****************
**** 08/23/07 17:58:38 ************** PSpice Lite (Jan 2005) *****************
 
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-PSpiceFiles\SCHEMATIC1\test.sim ]
** Profile: "SCHEMATIC1-test" [ D:\KAKLIK\projekty\schemata\mereni\VLF\SIM\receiver-pspicefiles\schematic1\test.sim ]
 
 
**** JOB STATISTICS SUMMARY
150,5 → 150,5
 
 
 
Total job time (using Solver 1) = .89
Total job time (using Solver 1) = .82
/schemata/mereni/VLF/SIM/receiver-PSpiceFiles/SCHEMATIC1/test/test.prb
38,10 → 38,10
MARKERID 3
TRACEADDEXT
END TRACE V(C5:1)
BEGIN TRACE V(R2:2)
BEGIN TRACE V(U1:OUT)
MARKERID 5
TRACEADDEXT
END TRACE V(R2:2)
END TRACE V(U1:OUT)
BEGIN TRACE V(TX1:3)
MARKERID 6
TRACEADDEXT