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/schemata/prenos/stenice/STENICE.DBK
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+application/octet-stream
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/schemata/prenos/stenice/STENICE.DSN
Cannot display: file marked as a binary type.
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+application/octet-stream
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/schemata/prenos/stenice/STENICE.ONL
0,0 → 1,216
(PCB STENICE
(description
(timeStamp "2003 04 02 16 51 19")
(program "CAPTURE.EXE" (Version "9.2.448 CIS - D"))
(source "Original data from OrCAD/CAPTURE schematic")
(title "")
(date "Wednesday, April 02, 2003")
(document "D:\\@KAKLIK\\SCHEMATA\\SEND\\STENICE\\STENICE.DSN")
(revision "")
(organization "")
(address1 "")
(address2 "")
(address3 "")
(address4 "")
(partvaluecombine "{Value}")
(pcbfootprintcombine "{Device}@{PCB Footprint}"))
(structure )
(placement
(component JUMP2
(place J1
(property
("PCB Footprint" JUMP2)
(Device JUMP2)
(timestamp 00000588)
("Source Package" JUMP2)
(Value JUMP2)))
(place J2
(property
("PCB Footprint" JUMP2)
(Device JUMP2)
(timestamp 00000902)
("Source Package" JUMP2)
(Value JUMP2))))
(component DIP8_300
(place U1
(property
("PCB Footprint" DIP8_300)
(Device DIP8)
(timestamp 00000065)
("Source Package" DIP8_300)
(Value LM386))))
(component MIKE
(place M1
(property
("PCB Footprint" JUMP2)
(Device JUMP2)
(timestamp 00000003)
("Source Package" MIKE)
(Value MIKE))))
(component "C-ELYT"
(place C1
(property
("PCB Footprint" ELYTB)
(Device ELYT)
(timestamp 000001DC)
("Source Package" "C-ELYT")
(Value 4,7u)))
(place C2
(property
("PCB Footprint" CE020X5/L)
(Device ELYT)
(timestamp 0000088F)
("Source Package" "C-ELYT")
(Value 100u))))
(component R
(place R1
(property
("PCB Footprint" R0603)
(Device R)
(timestamp 000001C4)
("Source Package" R)
(Value 220)))
(place R2
(property
("PCB Footprint" R0603)
(Device R)
(timestamp 000006BC)
("Source Package" R)
(Value 10k))))
(component C
(place C3
(property
("PCB Footprint" C0805)
(Device C)
(timestamp 000004FD)
("Source Package" C)
(Value 100n)))))
(library
(image DIP8_300
(property
(sourcelib C:\\LIBRARY\\ORCAD9X\\DECALES.OLB)
(Device DIP8))
(pin 999 1
(property
(pinname 1)
(pintype 4)))
(pin 999 2
(property
(pinname 2)
(pintype 4)))
(pin 999 3
(property
(pinname 3)
(pintype 4)))
(pin 999 4
(property
(pinname 4)
(pintype 4)))
(pin 999 5
(property
(pinname 5)
(pintype 4)))
(pin 999 6
(property
(pinname 6)
(pintype 4)))
(pin 999 7
(property
(pinname 7)
(pintype 4)))
(pin 999 8
(property
(pinname 8)
(pintype 4))))
(image R
(property
(sourcelib C:\\LIBRARY\\ORCAD9X\\GEN_RLC.OLB)
(Device R))
(pin 999 1
(property
(pinname 1)
(pintype 4)))
(pin 999 2
(property
(pinname 2)
(pintype 4))))
(image "C-ELYT"
(property
(sourcelib C:\\LIBRARY\\ORCAD9X\\GEN_RLC.OLB)
(Device C))
(pin 999 A
(property
(pinname A)
(pintype 4)))
(pin 999 C
(property
(pinname C)
(pintype 4))))
(image C
(property
(sourcelib C:\\LIBRARY\\ORCAD9X\\GEN_RLC.OLB)
(Device C))
(pin 999 1
(property
(pinname 1)
(pintype 4)))
(pin 999 2
(property
(pinname 2)
(pintype 4))))
(image MIKE
(property
(sourcelib "C:\\LIBRARY\\ORCAD91\\DEV-REST.OLB"))
(pin 999 1
(property
(pinname 1)
(pintype 4)))
(pin 999 2
(property
(pinname 2)
(pintype 4))))
(image JUMP2
(property
(sourcelib C:\\LIBRARY\\ORCAD9X\\JUMP.OLB)
(Device JUMP2))
(pin 999 1
(property
(pinname 1)
(pintype 4)))
(pin 999 2
(property
(pinname 2)
(pintype 4)))))
(network
(net N00823
(pins
C2-A U1-5))
(net N00528
(pins
U1-8 C1-C))
(net N00557
(pins
R1-1 U1-1))
(net N00904
(pins
C2-C J1-1))
(net VCC
(property
(nettype S))
(pins
J2-1 U1-6 R2-1))
(net N00250
(pins
U1-2 C3-2))
(net GND_POWER
(property
(nettype S))
(pins
M1-2 U1-3 J1-2 J2-2 U1-4))
(net N01652
(pins
C3-1 M1-1 R2-2))
(net N02015
(pins
R1-2 C1-A)))
)
/schemata/prenos/stenice/STENICE.asc
0,0 → 1,32
*PADS-PCB*
*PART*
C1 ELYT@ELYTB
C2 ELYT@CE020X5/L
C3 C@C0805
J1 JUMP2@JUMP2
J2 JUMP2@JUMP2
M1 JUMP2@JUMP2
R1 R@R0603
R2 R@R0603
U1 DIP8@DIP8_300
 
*NET*
*SIGNAL* N00823
C2.A U1.5
*SIGNAL* N00528
U1.8 C1.C
*SIGNAL* N00557
R1.1 U1.1
*SIGNAL* N00904
C2.C J1.1
*SIGNAL* VCC
J2.1 U1.6 R2.1
*SIGNAL* N00250
U1.2 C3.2
*SIGNAL* GND_POWER
M1.2 U1.3 J1.2 J2.2 U1.4
*SIGNAL* N01652
C3.1 M1.1 R2.2
*SIGNAL* N02015
R1.2 C1.A
*END*
/schemata/prenos/stenice/STENICE.eco
0,0 → 1,93
*PADS-ECO-V3.0-MILS*
 
*REMARK* -- STENICE.pcb -- Wed Apr 02 20:28:32 2003
 
*CREATE_GENERAL_RULES* CLEARANCE
HIERARCHY_OBJECT NET:VCC
HIERARCHY_OBJECT NET:GND_POWER
MIN_TRACK_WIDTH 0.5
REC_TRACK_WIDTH 0.5
MAX_TRACK_WIDTH 0.5
TRACK_TO_TRACK 0.5
VIA_TO_TRACK 0.5
VIA_TO_VIA 0.5
PAD_TO_TRACK 0.5
PAD_TO_VIA 0.5
PAD_TO_PAD 0.5
SMD_TO_TRACK 0.5
SMD_TO_VIA 0.5
SMD_TO_PAD 0.5
SMD_TO_SMD 0.5
COPPER_TO_TRACK 0.5
COPPER_TO_VIA 0.5
COPPER_TO_PAD 0.5
COPPER_TO_SMD 0.5
TEXT_TO_TRACK 0.5
TEXT_TO_VIA 0.5
TEXT_TO_PAD 0.5
TEXT_TO_SMD 0.5
OUTLINE_TO_TRACK 0.5
OUTLINE_TO_VIA 0.5
OUTLINE_TO_PAD 0.5
OUTLINE_TO_SMD 0.5
DRILL_TO_TRACK 0.5
DRILL_TO_VIA 0.5
DRILL_TO_PAD 0.5
DRILL_TO_SMD 0.5
DRILL_TO_COPPER 0.5
SAME_NET_SMD_TO_VIA 0.1524
SAME_NET_SMD_TO_CRN 0.1524
SAME_NET_VIA_TO_VIA 0.1524
SAME_NET_PAD_TO_CRN 0.1524
SAME_NET_TRACK_TO_CRN 0
 
*CREATE_GENERAL_RULES* CLEARANCE
HIERARCHY_OBJECT NET:N02015
HIERARCHY_OBJECT NET:N01652
HIERARCHY_OBJECT NET:N00904
HIERARCHY_OBJECT NET:N00823
HIERARCHY_OBJECT NET:N00557
HIERARCHY_OBJECT NET:N00528
HIERARCHY_OBJECT NET:N00250
MIN_TRACK_WIDTH 0.45
REC_TRACK_WIDTH 0.45
MAX_TRACK_WIDTH 0.45
TRACK_TO_TRACK 0.5
VIA_TO_TRACK 0.5
VIA_TO_VIA 0.5
PAD_TO_TRACK 0.5
PAD_TO_VIA 0.5
PAD_TO_PAD 0.5
SMD_TO_TRACK 0.5
SMD_TO_VIA 0.5
SMD_TO_PAD 0.5
SMD_TO_SMD 0.5
COPPER_TO_TRACK 0.5
COPPER_TO_VIA 0.5
COPPER_TO_PAD 0.5
COPPER_TO_SMD 0.5
TEXT_TO_TRACK 0.5
TEXT_TO_VIA 0.5
TEXT_TO_PAD 0.5
TEXT_TO_SMD 0.5
OUTLINE_TO_TRACK 0.5
OUTLINE_TO_VIA 0.5
OUTLINE_TO_PAD 0.5
OUTLINE_TO_SMD 0.5
DRILL_TO_TRACK 0.5
DRILL_TO_VIA 0.5
DRILL_TO_PAD 0.5
DRILL_TO_SMD 0.5
DRILL_TO_COPPER 0.5
SAME_NET_SMD_TO_VIA 0.1524
SAME_NET_SMD_TO_CRN 0.1524
SAME_NET_VIA_TO_VIA 0.1524
SAME_NET_PAD_TO_CRN 0.1524
SAME_NET_TRACK_TO_CRN 0
 
*END*
*PADS-ECO-V3.0-MILS*
 
*REMARK* -- STENICE.pcb -- Wed Apr 02 21:18:35 2003
 
*END*
/schemata/prenos/stenice/STENICE.pcb
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/schemata/prenos/stenice/layout.log
0,0 → 1,5
Wed Apr 02 18:39:23 Loaded file C:\PROGRAM FILES\ORCADLITE\LAYOUT_PLUS\LIBRARY\EMPTY.LLB
Wed Apr 02 18:39:23 Loaded file C:\PROGRAM FILES\ORCADLITE\LAYOUT_PLUS\LIBRARY\EX_GUI.LLB
Wed Apr 02 18:39:23 Loaded file C:\PROGRAM FILES\ORCADLITE\LAYOUT_PLUS\LIBRARY\METRIC.LLB
Wed Apr 02 18:39:23 Loaded file C:\PROGRAM FILES\ORCADLITE\LAYOUT_PLUS\LIBRARY\PADSTACK.LLB
Wed Apr 02 18:39:23 Loaded file C:\PROGRAM FILES\ORCADLITE\LAYOUT_PLUS\LIBRARY\rc.LLB
/schemata/prenos/stenice/stenice.opj
0,0 → 1,93
(ExpressProject "stenice"
(ProjectVersion "19981106")
(ProjectType "PCB")
(Folder "Design Resources"
(Folder "Library")
(NoModify)
(File ".\stenice.dsn"
(Type "Schematic Design"))
(BuildFileAddedOrDeleted "x")
(CompileFileAddedOrDeleted "x")
(Netlist_TAB "7")
(OTHER_Part_Value "{Value}")
(OTHER_Netlist_File "STENICE.asc")
(OTHER_Netlist_File2 "STENICE.CMP")
(OTHER_View_Output "TRUE")
(OTHER_View_Output2 "FALSE")
(OTHER_Formatter "padspcb.dll")
(OTHER_PCB_Footprint "{Device}@{PCB Footprint}")
(OTHER_Switch0 "FALSE")
(OTHER_Switch1 "FALSE")
(OTHER_Switch2 "FALSE")
(OTHER_Switch3 "FALSE")
(OTHER_Switch4 "FALSE")
(OTHER_Switch5 "FALSE")
(OTHER_Switch6 "FALSE"))
(Folder "Outputs"
(File ".\stenice.asc"
(Type "Report")))
(Folder "Referenced Projects")
(PartMRUSelector
(JUMP2
(FullPartName "JUMP2.Normal")
(LibraryName "C:\LIBRARY\ORCAD9X\JUMP.OLB")
(DeviceIndex "0"))
(C-ELYT
(FullPartName "C-ELYT.Normal")
(LibraryName "C:\LIBRARY\ORCAD9X\GEN_RLC.OLB")
(DeviceIndex "0"))
(R
(FullPartName "R.Normal")
(LibraryName "C:\LIBRARY\ORCAD9X\GEN_RLC.OLB")
(DeviceIndex "0"))
(VCC
(LibraryName "C:\PROGRAM FILES\ORCADLITE\CAPTURE\LIBRARY\CAPSYM.OLB")
(DeviceIndex "0"))
(GND_POWER
(LibraryName "C:\PROGRAM FILES\ORCADLITE\CAPTURE\LIBRARY\CAPSYM.OLB")
(DeviceIndex "0"))
(C
(FullPartName "C.Normal")
(LibraryName "C:\LIBRARY\ORCAD9X\GEN_RLC.OLB")
(DeviceIndex "0"))
(GROUND
(FullPartName "GROUND.Normal")
(LibraryName "C:\LIBRARY\ORCAD9X\GEN_REST.OLB")
(DeviceIndex "0"))
(DIP8_300
(FullPartName "DIP8_300.Normal")
(LibraryName "C:\LIBRARY\ORCAD9X\DECALES.OLB")
(DeviceIndex "0"))
(PHONEJACKSTEREO
(FullPartName "PHONEJACKSTEREO.Normal")
(LibraryName "C:\LIBRARY\ORCAD9X\_SENO_.OLB")
(DeviceIndex "0"))
(PADRC_4x6
(FullPartName "PADRC_4x6.Normal")
(LibraryName "C:\LIBRARY\ORCAD9X\COM_CON.OLB")
(DeviceIndex "0"))
(MIKE
(FullPartName "MIKE.Normal")
(LibraryName "C:\LIBRARY\ORCAD91\DEV-REST.OLB")
(DeviceIndex "0")))
(LastUsedLibraryBrowseDirectory "C:\library\ORCAD9x")
(GlobalState
(FileView
(Path "Design Resources")
(Path "Outputs"))
(HierarchyView)
(Doc
(Type "COrCapturePMDoc")
(Frame
(Placement "44 0 1 -1 -1 -4 -23 0 200 0 301"))
(Tab 0))
(Doc
(Type "COrSchematicDoc")
(Frame
(Placement "44 2 3 -1 -1 -4 -23 66 712 66 394")
(Scroll "0 0")
(Zoom "100")
(Occurrence "/"))
(Path "D:\@KAKLIK\SCHEMATA\SEND\STENICE\STENICE.DSN")
(Schematic "SCHEMATIC1")
(Page "PAGE1"))))
/schemata/prenos/stenice/vssver.scc
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