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\chap Trial design
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\chap Trial design
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The whole design of radioastronomy receiver digitalization unit is constructed to be used in a wide range of applications and tasks related to digitalization of signal from radioastronomy receivers. A good illustrating problem for its use is a signal digitalisation from multiple antenna arrays. This design will eventually become a part of MLAB Advanced Radio Astronomy System.
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The whole design of radioastronomy receiver digitalization unit is constructed to be used in a wide range of applications and tasks related to digitalization of signal from radioastronomy receivers. A good illustrating problem for its use is a signal digitalisation from multiple antenna arrays. This design will eventually become a part of MLAB Advanced Radio Astronomy System.
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\sec Required parameters
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\sec Required parameters
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Wide dynamical range and high IP3 are desired. The receiver must accept wide dynamic signals because a typical radioastronomical signal has a form of a weak signal covered by a strong man-made noise.
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Wide dynamical range and high IP3 are desired. The receiver must accept wide dynamic signals because a typical radioastronomical signal has a form of a weak signal covered by a strong man-made noise.
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Summary of main required parameters follows
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Summary of main required parameters follows
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\begitems
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\begitems
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* Dynamical range better than 80 dB
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* Dynamical range better than 80 dB
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* Phase stability between channels
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* Phase stability between channels
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* Noise (all types)
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* Noise (all types)
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* Sampling jitter better than 100 metres
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* Sampling jitter better than 100 metres
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* Support for any number of receivers in range 1 to 8
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* Support for any number of receivers in range 1 to 8
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\enditems
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\enditems
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\sec Sampling frequency
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\sec Sampling frequency
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Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market and interface bandwidth. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1 MSPS leads to need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5$\ $MSPS.
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Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market and interface bandwidth. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1$\ $MSPS leads to need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5$\ $MSPS.
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We calculate minimum data bandwidth data rate for eight receivers, 2 bytes per sample and 5MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/s. Such data rate is at the limit of real writing speed o classical HDD and it is almost double of real bandwidth of USB 2.0 interface.
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We calculate minimum data bandwidth data rate for eight receivers, 2 bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/s. Such data rate is at the limit of real writing speed o classical HDD and it is almost double of real bandwidth of USB 2.0 interface.
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\sec System scalability
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\sec System scalability
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For analogue channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each analogue channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow for conduction at relatively low digital data rates. As a result, the digital signal can be conducted even through long wires.
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For analogue channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each analogue channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow for conduction at relatively low digital data rates. As a result, the digital signal can be conducted even through long wires.
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Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.).
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Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.). If more robustness is required from designs DCO and FR signal may be collected from other modules and routed through an voting logic which will correct possible signal defects.
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This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power. There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.
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This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power. There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.
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\secc Differential signaling
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\secc Differential signaling
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The concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA or other flip-flops block and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such cases any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time a long distance brings problems with the digital signal transmission between ADC and computational unit. This obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used. This technology has two advantages over PCB signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path and second, the twisted pair may additionally be shielded by uninterrupted metal foil.
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The concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA or other flip-flops block and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such cases any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time a long distance brings problems with the digital signal transmission between ADC and computational unit. This obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used. This technology has two advantages over PCB signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path and second, the twisted pair may additionally be shielded by uninterrupted metal foil.
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\secc Phase matching
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\secc Phase matching
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For multiple antenna radioastronomy projects, system phase stability is a mandatory condition. It allows precise high resolution imaging of objects.
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For multiple antenna radioastronomy projects, system phase stability is a mandatory condition. It allows precise high resolution imaging of objects.
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High phase stability in our scalable design is achieved through centralized frequency generation and distribution with multi-output LVPECL hubs, that have equiphased outputs for multiple devices.
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High phase stability in our scalable design is achieved through centralized frequency generation and distribution with multi-output LVPECL hubs, that have equiphased outputs for multiple devices. LVPECL logic is used on every system critical clock signal distribution hub. LVPECL logic has advantage over LVDS in signal integrity robustness. LVPECL uses higher logical levels and higher signalling currents. Consumption currents of LVPECL logic are near constant over operating frequency range due to use of bipolar transistor this minimises voltage glitches which are typical for CMOS logic. One drawbacks of that parameters is high power consumption of LVPECL logic.
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This design ensures that all devices have access to the defined phase and known frequency.
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This design ensures that all devices have access to the defined phase and known frequency.
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\sec System description
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\sec System description
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In this section testing system will be described.
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In this section testing system will be described.
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\secc Frequency synthesis
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\secc Frequency synthesis
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We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO], while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis.}
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We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO], while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis.}
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We have used methods of frequency monitoring compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide scale for effective radioastronomy imaging.
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We have used methods of frequency monitoring compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide scale for effective radioastronomy imaging.
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GPSDO device consists the Si570 chip with LVPECL output. Phase jitter of GPSDO is determined mainly by Si570 phase noise. Parameters of used Si570 from source ... are summarized in table \ref[LO-noise].
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GPSDO device consists the Si570 chip with LVPECL output. Phase jitter of GPSDO is determined mainly by Si570 phase noise. Parameters of used Si570 from source \cite[si570-chip] are summarized in table \ref[LO-noise].
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\midinsert \clabel[LO-noise]{Available ADC types}
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\midinsert \clabel[LO-noise]{Available ADC types}
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\ctable{lcc}{
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\ctable{lcc}{
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& \multispan2 \hfil Phase Noise [dBc/Hz] \hfil \cr
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& \multispan2 \hfil Phase Noise [dBc/Hz] \hfil \cr
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Offset Frequency & $F_{out}$ 156.25 MHz & $F_{out}$ 622.08 MHz \cr
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Offset Frequency & $F_{out}$ 156.25 MHz & $F_{out}$ 622.08 MHz \cr
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100 [Hz] & –105 & –97 \cr
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100 [Hz] & –105 & –97 \cr
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1 [kHz] & –122 & –107 \cr
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1 [kHz] & –122 & –107 \cr
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10 [kHz] & –128 & –116 \cr
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10 [kHz] & –128 & –116 \cr
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100 [kHz] & –135 & –121 \cr
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100 [kHz] & –135 & –121 \cr
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1 [MHz] & –144 & –134 \cr
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1 [MHz] & –144 & –134 \cr
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10 [MHz] & –147 & –146 \cr
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10 [MHz] & –147 & –146 \cr
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100 [MHz] & n/a & –148 \cr
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100 [MHz] & n/a & –148 \cr
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}
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}
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\caption/t The summary of available ADC types and theirs characteristics.
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\caption/t The summary of available ADC types and theirs characteristics.
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\endinsert
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\endinsert
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from main local oscillator. This signal should use high quality differential signaling cable -- we should use SATA cable for this purpose. FPGA may slightly affect clock signal quality by additive noise, but has negligible effect in application where developed system will be used.
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from main local oscillator. This signal should use high quality differential signaling cable -- we should use SATA cable for this purpose. FPGA may slightly affect clock signal quality by additive noise, but has negligible effect in application where developed system will be used.
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GPSDO design included in data acquisition system has special feature -- generates time marks for precise time-stamping of received signal. Timestamps are created by disabling of local oscillator for 100 us as result rectangle click in input signal is created which appears as horizontal line in spectrogram.
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GPSDO design included in data acquisition system has special feature -- generates time marks for precise time-stamping of received signal. Timestamps are created by disabling of local oscillator for 100 us as result rectangle click in input signal is created which appears as horizontal line in spectrogram.
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Timestamps should be seen in image \ref[meteor-reflection] (above and below meteor reflection).
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Timestamps should be seen in image \ref[meteor-reflection] (above and below meteor reflection).
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Time-marking should be improved in future by digitalization of GPS signal received by antenna on observational station. GPS signal can be then directly sampled by dedicated receiver an separate ADC module. Datafile then consists samples from channels of radio-astronomy receivers along with GPS signal containing precise time information.
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Time-marking should be improved in future by digitalization of GPS signal received by antenna on observational station. GPS signal can be then directly sampled by dedicated receiver an separate ADC module. Datafile then consists samples from channels of radio-astronomy receivers along with GPS signal containing precise time information.
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\secc Signal cable connectors
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\secc Signal cable connectors
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Several widely used and commercially easily accessible differential connectors were considered to be use in our design.
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Several widely used and commercially easily accessible differential connectors were considered to be use in our design.
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\begitems
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\begitems
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* HDMI % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
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* HDMI % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
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* SATA %{http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]
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* SATA %{http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]
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* DisplayPort %[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>
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* DisplayPort %[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>
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* SAS/miniSAS
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* SAS/miniSAS
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\enditems
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\enditems
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At the end, MiniSAS connector was chosen as the best option to be used in connecting together multiple ADC modules. It is compatible with existing SATA cabling systems and aggregates multiple SATA cables to a single connector. It can be seen on the following picture \ref[img-miniSAS-cable]. A transition between SATA and miniSAS is achieved by SAS to SATA adapter cable which is commonly used in servers to connect SAS controller to multiple SATA hard disc in RAID systems and thus is commercially easily available.
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At the end, MiniSAS connector was chosen as the best option to be used in connecting together multiple ADC modules. It is compatible with existing SATA cabling systems and aggregates multiple SATA cables to a single connector. It can be seen on the following picture \ref[img-miniSAS-cable]. A transition between SATA and miniSAS is achieved by SAS to SATA adapter cable which is commonly used in servers to connect SAS controller to multiple SATA hard disc in RAID systems and thus is commercially easily available.
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The main drawback of miniSAS PCB connectors lies in the fact, that they are manufactured in SMT versions only. The outer metal housing of connector is designed to be mounted using a standard through-hole mounting scheme, a design that unfortunately decreases the durability of the connector.
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The main drawback of miniSAS PCB connectors lies in the fact, that they are manufactured in SMT versions only. The outer metal housing of connector is designed to be mounted using a standard through-hole mounting scheme, a design that unfortunately decreases the durability of the connector.
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\midinsert
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\midinsert
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\clabel[img-miniSAS-cable]{Used miniSAS cable}
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\clabel[img-miniSAS-cable]{Used miniSAS cable}
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\picw=10cm \cinspic ./img/miniSAS_SATA_cable.jpg
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\picw=10cm \cinspic ./img/miniSAS_SATA_cable.jpg
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\caption/f A type of miniSAS cable similar to used.
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\caption/f A type of miniSAS cable similar to used.
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\endinsert
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\endinsert
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\secc Signal integrity requirements
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\secc Signal integrity requirements
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\label[diff-signaling]
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\label[diff-signaling]
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We use ADC modules that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. This imply $ 1/4*10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate $t_s$ will be 4.95 m. Although we do not have any cables in system with comparable lengths, worst data bit skew described by data sheets of used components is $0.3 \cdot t_s$, which is 1.485 m. Therefore length matching is not critical in our design.
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We use ADC modules that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. This imply $ 1/4 \cdot 10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate $t_s$ will be 4.95 m. Although we do not have any cables in system with comparable lengths, worst data bit skew described by data sheets of used components is $0.3 \cdot t_s$, which is 1.485 m. Therefore length matching is not critical in our current design operated on lowest sampling speed. Length matching becomes critical in future version with higher sampling rates, then cable length must be matched. However SATA cabling technology is prepared for that case and matched SATA cables are standard merchandise.
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\secc ADC modules design
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\secc ADC modules design
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\secc ADC selection
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\secc ADC selection
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There exist several ADC signaling formats currently used in communication with FPGA.
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There exist several ADC signaling formats currently used in communication with FPGA.
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\begitems
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\begitems
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* DDR LVDS
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* DDR LVDS
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* JEDEC 204B
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* JEDEC 204B
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* JESD204A
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* JESD204A
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* Paralel LVDS
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* Paralel LVDS
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* Serdes
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* Serdes
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* serial LVDS
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* serial LVDS
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\enditems
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\enditems
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Because it uses the smallest number of differential pairs, the choice fell on the serial LVDS format. Small number of differential pairs is an important parameter determining the construction complexity and reliability\cite[serial-lvds].
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Because it uses the smallest number of differential pairs, the choice fell on the serial LVDS format. Small number of differential pairs is an important parameter determining the construction complexity and reliability\cite[serial-lvds].
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| 125 |
An ultrasound AFE chip seems to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though - it is incapable of handling differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC). Because this IO has many ADC channels the scaling is possible only by a factor of 4 receivers (making 8 analogue channels).
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An ultrasound AFE chip seems to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though - it is incapable of handling differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC). Because this IO has many ADC channels the scaling is possible only by a factor of 4 receivers (making 8 analogue channels).
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126 |
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| 127 |
If we require a separate output for every analogue channel and a 16bit depth we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these requirements. We have summarized the ADCs in the following table \ref[ADC-type]
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If we require a separate output for every analogue channel and a 16bit depth we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these requirements. We have summarized the ADCs in the following table \ref[ADC-type]
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\midinsert \clabel[ADC-types]{Available ADC types}
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\midinsert \clabel[ADC-types]{Available ADC types}
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\ctable{lrrrrrcc}{
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130 |
\ctable{lccccccc}{
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| 131 |
\hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr
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131 |
\hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr
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SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8 \cr
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132 |
SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8 \cr
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| 133 |
SFDR [dB] & 99 & 90 & 90 & 90 & 90 & 90 & 90 \cr
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133 |
SFDR [dB] & 99 & 90 & 90 & 90 & 90 & 90 & 90 \cr
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| 134 |
S/H Bandwidth [MHz] & 200 & \multispan6 550 \cr
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S/H Bandwidth [MHz] & 200 & \multispan6 550 \cr
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| 135 |
Sampling rate [MSPS] & 20 & 25 & 40 & 65 & 80 & 105 & 125 \cr
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135 |
Sampling rate [MSPS] & 20 & 25 & 40 & 65 & 80 & 105 & 125 \cr
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Configuration & \multispan7 SPI \cr
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Configuration & \multispan7 SPI \cr
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Package & \multispan7 52-Lead (7mm $×$ 8mm) QFN \cr
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Package & \multispan7 52-Lead (7mm $×$ 8mm) QFN \cr
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| 138 |
}
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138 |
}
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\caption/t The summary of available ADC types and theirs characteristics.
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\caption/t The summary of available ADC types and theirs characteristics.
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\endinsert
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140 |
\endinsert
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| 141 |
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141 |
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| 142 |
All parts in this category are compatible with one board layout. Main differences lay in the sampling frequency and signal to noise ratio, with the slowest having a maximum sampling frequency of 20 MHz. However all of them have a minimal sampling frequency of 5 MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..).
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All parts in this category are compatible with one board layout. Main differences lay in the sampling frequency and signal to noise ratio, with the slowest having a maximum sampling frequency of 20 MHz. However all of them have a minimal sampling frequency of 5 MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..).
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| 144 |
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The ADC modules have a standard MLAB construction scheme with four mounting holes in corners aligned in defined raster.
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The ADC modules have a standard MLAB construction scheme with four mounting holes in corners aligned in defined raster.
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| 147 |
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147 |
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| 148 |
Data serial data outputs of ADC modules should be connected directly to FPGAs for the basic primary signal processing. The ADC chip used in the modules has a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel. This creates a signal concept enabling a selection of a proper bus bit-width according to the sampling rate (higher bus bit-width downgrades signalling speed and vice versa.)
|
148 |
Data serial data outputs of ADC modules should be connected directly to FPGAs for the basic primary signal processing. The ADC chip used in the modules has a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel. This creates a signal concept enabling a selection of a proper bus bit-width according to the sampling rate (higher bus bit-width downgrades signalling speed and vice versa.)
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149 |
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| 150 |
In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable should be used.
|
150 |
In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable should be used.
|
| 151 |
|
151 |
|
| 152 |
A KiCAD design suite had been chosen for PCB layout. However, the version is, despite having integrated CERN Push \& Shove routing capability, slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad, the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software.
|
152 |
A KiCAD design suite had been chosen for PCB layout. However, the version is, despite having integrated CERN Push \& Shove routing capability, slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad, the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software.
|
| 153 |
|
153 |
|
| 154 |
As a part of work on the thesis, new PCB footprints for FMC, SATA a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub.
|
154 |
As a part of work on the thesis, new PCB footprints for FMC, SATA a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub.
|
| 155 |
|
155 |
|
| 156 |
|
156 |
|
| 157 |
ADCdual01A module has several digital data output formats. Distinction between these modes are in number of differential pairs use
|
157 |
ADCdual01A module has several digital data output formats. Distinction between these modes are in number of differential pairs use
|
| 158 |
|
158 |
|
| 159 |
\begitems
|
159 |
\begitems
|
| 160 |
* 1-lane mode
|
160 |
* 1-lane mode
|
| 161 |
* 2-lane mode
|
161 |
* 2-lane mode
|
| 162 |
* 4-lane mode
|
162 |
* 4-lane mode
|
| 163 |
\enditems
|
163 |
\enditems
|
| 164 |
|
164 |
|
| 165 |
All of these modes are supported by module design. For discussed data acquisition system the 1-lane mode was selected. 1-lane mode allows minimal number of differential pairs between ADCdual01A and FPGA. Digital signaling scheme used in 1-lane mode is shown in image \ref[1-line-out].
|
165 |
All of these modes are supported by module design. For discussed data acquisition system the 1-lane mode was selected. 1-lane mode allows minimal number of differential pairs between ADCdual01A and FPGA. Digital signaling scheme used in 1-lane mode is shown in image \ref[1-line-out].
|
| 166 |
|
166 |
|
| 167 |
\midinsert
|
167 |
\midinsert
|
| 168 |
\clabel[1-line-out]{Single line ADC output signals}
|
168 |
\clabel[1-line-out]{Single line ADC output signals}
|
| 169 |
\picw=15cm \cinspic ./img/ADC_single_line_output.png
|
169 |
\picw=15cm \cinspic ./img/ADC_single_line_output.png
|
| 170 |
\caption/f Digital signaling schema for 1-line ADC digital output mode.
|
170 |
\caption/f Digital signaling schema for 1-line ADC digital output mode.
|
| 171 |
\endinsert
|
171 |
\endinsert
|
| 172 |
|
172 |
|
| 173 |
ADCdual01A parameters can be set either by jumper setup (referred as parallel programming in device's data sheet) or by SPI interface. SPI interface has been selected for our system, because parallel programming lacks of options (test pattern output setup for example).
|
173 |
ADCdual01A parameters can be set either by jumper setup (referred as parallel programming in device's data sheet) or by SPI interface. SPI interface has been selected for our system, because parallel programming lacks of options (test pattern output setup for example).
|
| 174 |
|
174 |
|
| 175 |
Complete schematic diagram of ADCdual01A module board is included in the appendix.
|
175 |
Complete schematic diagram of ADCdual01A module board is included in the appendix.
|
| 176 |
|
176 |
|
| 177 |
|
177 |
|
| 178 |
\secc ADC modules interface
|
178 |
\secc ADC modules interface
|
| 179 |
|
179 |
|
| 180 |
Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter module expects the presence of FMC LPC connector and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions].
|
180 |
Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter module expects the presence of FMC LPC connector and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions].
|
| 181 |
This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the appendix.
|
181 |
This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the appendix.
|
| 182 |
|
182 |
|
| 183 |
The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques).
|
183 |
The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques).
|
| 184 |
Differential signaling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
|
184 |
Differential signaling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
|
| 185 |
|
185 |
|
| 186 |
\midinsert
|
186 |
\midinsert
|
| 187 |
\picw=10cm \cinspic ./img/ML605-board.jpg
|
187 |
\picw=10cm \cinspic ./img/ML605-board.jpg
|
| 188 |
\caption/f FPGA ML605 development board.
|
188 |
\caption/f FPGA ML605 development board.
|
| 189 |
\endinsert
|
189 |
\endinsert
|
| 190 |
|
190 |
|
| 191 |
\midinsert
|
191 |
\midinsert
|
| 192 |
\clabel[VITA57-regions]{VITA57 board geometry}
|
192 |
\clabel[VITA57-regions]{VITA57 board geometry}
|
| 193 |
\picw=10cm \cinspic ./img/VITA57_regions.png
|
193 |
\picw=10cm \cinspic ./img/VITA57_regions.png
|
| 194 |
\caption/f Definition of VITA57 regions.
|
194 |
\caption/f Definition of VITA57 regions.
|
| 195 |
\endinsert
|
195 |
\endinsert
|
| 196 |
|
196 |
|
| - |
|
197 |
|
| 197 |
Several SATA connectors and two miniSAS connectors are populated on this board. This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter.
|
198 |
Several SATA connectors and two miniSAS connectors are populated on this board. This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter.
|
| 198 |
|
199 |
|
| 199 |
Lengths of differential pairs routed on PCB of module are not matched between pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless signals within differential pairs itself are matched for length. Internal signal traces length mating of differential pairs is mandatory in order to avoid dynamic logic hazard conditions on digital signals. Thus clocks signals are routed most precisely on all designed boards.
|
200 |
Lengths of differential pairs routed on PCB of module are not matched between pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless signals within differential pairs itself are matched for length. Internal signal traces length mating of differential pairs is mandatory in order to avoid dynamic logic hazard conditions on digital signals. Thus clocks signals are routed most precisely on all designed boards.
|
| 200 |
|
201 |
|
| 201 |
|
202 |
|
| 202 |
Signal configuration used in our trial design is described in the following tables.
|
203 |
Signal configuration used in our trial design is described in the following tables.
|
| 203 |
|
204 |
|
| 204 |
\secc Output data format
|
205 |
%% zapojeni SPI, FPGA zpatky necte konfiguraci, ale je tam na slepo nahravana.
|
| 205 |
|
206 |
|
| - |
|
207 |
|
| - |
|
208 |
SPI interface is used by unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back are not possible, thus configuration written to registers in ADC module cannot be validated. We do not observe any problem with this system, but it may be possible source of failures.
|
| - |
|
209 |
|
| - |
|
210 |
\secc FPGA function
|
| - |
|
211 |
|
| - |
|
212 |
Several tasks are performed by FPGA. Firstly FPGA prepares sampling clock for ADCdual01A modules this task is separate block in FPGA and runs asynchronously to other logic. Second block is SPI configuration module, which sends configuration words to ADC modules after opening of Xillybus interface file. Third block is main module, which resolve ADC - PC communication itself. Last block is activated after ADC configuration.
|
| - |
|
213 |
|
| 206 |
\midinsert
|
214 |
Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which tranfers data from FPGA registers to host PC. Data appears in system device file "/dev/xillybus_data2_r" on host computer. Binary data which appears in this file after opening are described in table \ref[xillybus-interface].
|
| - |
|
215 |
|
| - |
|
216 |
\midinsert \clabel[xillybus-interface]{Grabber binary output format}
|
| 207 |
\ctable {clllllllll}{
|
217 |
\ctable {clllllllll}{
|
| 208 |
\hfil
|
218 |
\hfil
|
| 209 |
& \multispan9 \hfil 160bit packet \hfil \crl \tskip4pt
|
219 |
& \multispan9 \hfil 160bit packet \hfil \crl \tskip4pt
|
| 210 |
Data name & FRAME & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2 \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil \cr
|
220 |
Data name & FRAME & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2 \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil \cr
|
| 211 |
Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr
|
221 |
Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr
|
| 212 |
Content & saw signal & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ \cr
|
222 |
Content & saw signal & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ \cr
|
| 213 |
}
|
223 |
}
|
| 214 |
\caption/t System device "/dev/xillybus_data2_r" data format
|
224 |
\caption/t System device "/dev/xillybus_data2_r" data format
|
| 215 |
\endinsert
|
225 |
\endinsert
|
| 216 |
|
226 |
|
| 217 |
\sec Achieved parameters
|
227 |
Detailed description of FPGA function can be found in \cite[fpga-middleware]
|
| - |
|
228 |
|
| 218 |
|
229 |
|
| 219 |
\secc Data reading and recording
|
230 |
\secc Data reading and recording
|
| 220 |
|
231 |
|
| 221 |
We use Gnuradio software to read the data stream from the ADC drive. Gnuradio suite consist of gnuradio-companion which is a graphical tool for creating signal-flow graphs and generating flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view the data stream output from ADC modules.
|
232 |
We use Gnuradio software to read the data stream from the ADC drive. Gnuradio suite consist of gnuradio-companion which is a graphical tool for creating signal-flow graphs and generating flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view the data stream output from ADC modules.
|
| 222 |
|
233 |
|
| 223 |
\midinsert
|
234 |
\midinsert
|
| 224 |
\picw=15cm \cinspic ./img/screenshots/Grabber.grc.png
|
235 |
\picw=15cm \cinspic ./img/screenshots/Grabber.grc.png
|
| 225 |
\caption/f An ADC recorder flow graph created in gnuradio-companion.
|
236 |
\caption/f An ADC recorder flow graph created in gnuradio-companion.
|
| 226 |
\endinsert
|
237 |
\endinsert
|
| 227 |
|
238 |
|
| 228 |
\midinsert
|
239 |
\midinsert
|
| 229 |
\picw=15cm \cinspic ./img/screenshots/Grabber_running.png
|
240 |
\picw=15cm \cinspic ./img/screenshots/Grabber_running.png
|
| 230 |
\caption/f User interface window of a running ADC grabber.
|
241 |
\caption/f User interface window of a running ADC grabber.
|
| 231 |
\endinsert
|
242 |
\endinsert
|
| 232 |
|
243 |
|
| 233 |
Interactive grabber viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal.
|
244 |
Interactive grabber viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal.
|
| 234 |
|
245 |
|
| - |
|
246 |
|
| - |
|
247 |
\sec Achieved parameters
|
| - |
|
248 |
|
| 235 |
\secc ADC module parameters
|
249 |
\secc ADC module parameters
|
| 236 |
|
250 |
|
| 237 |
Two pieces of ADC modules were completed and tested. The first piece, labeled ADC1, has LTC2190
|
251 |
Two pieces of ADC modules were completed and tested. The first piece, labeled ADC1, has LTC2190
|
| 238 |
ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which gives it an ability of an internal attenuation of input signal. The value of this attenuation $A$ is described by the following formula \ref[ADC1-gain]
|
252 |
ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which gives it an ability of an internal attenuation of input signal. The value of this attenuation $A$ is described by the following formula \ref[ADC1-gain]
|
| 239 |
|
253 |
|
| - |
|
254 |
|
| 240 |
\label[ADC1-gain]
|
255 |
\label[ADC1-gain]
|
| 241 |
$$
|
256 |
$$
|
| 242 |
A = {806 \times R_1 \over R_1 + R_2}
|
257 |
A = {806 \cdot R_1 \over R_1 + R_2}
|
| 243 |
$$
|
258 |
$$
|
| 244 |
|
259 |
|
| 245 |
Where is
|
260 |
Where is
|
| 246 |
\begitems
|
261 |
\begitems
|
| 247 |
* $A$ - Gain of input amplifier.
|
262 |
* $A$ - Gain of input amplifier.
|
| 248 |
* $R_1$ - Output impedance of signal source (usually 50 Ohm).
|
263 |
* $R_1$ - Output impedance of signal source (usually 50 Ohm).
|
| 249 |
* $R_2$ - Value of serial resistors at operational amplifier inputs.
|
264 |
* $R_2$ - Value of serial resistors at operational amplifier inputs.
|
| 250 |
\enditems
|
265 |
\enditems
|
| 251 |
|
266 |
|
| 252 |
We have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply $A = 0.815$. That value of A is confirmed by measurement.
|
267 |
We have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply $A = 0.815$. That value of A is confirmed by measurement.
|
| 253 |
In our measurement setup we have H1012 Ethernet transformer connected at inputs of ADC. Transformer has 10\% tolerance in impedance and amplification. We measured ADC saturation voltage 705.7 mV (generator output) in this setup due to impedance mismatch and uncalibrated transformer gain.
|
268 |
In our measurement setup we have H1012 Ethernet transformer connected at inputs of ADC. Transformer has 10\% tolerance in impedance and amplification. We measured ADC saturation voltage 705.7 mV (generator output) in this setup due to impedance mismatch and uncalibrated transformer gain.
|
| 254 |
|
269 |
|
| 255 |
|
270 |
|
| 256 |
\midinsert
|
271 |
\midinsert
|
| 257 |
\clabel[ADC1-FFT]{ADC1 sine test FFT}
|
272 |
\clabel[ADC1-FFT]{ADC1 sine test FFT}
|
| 258 |
\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
|
273 |
\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
|
| 259 |
\caption/f Sine signal sampled by ADC1 module with LTC2190 and LT6600-5 devices.
|
274 |
\caption/f Sine signal sampled by ADC1 module with LTC2190 and LT6600-5 devices.
|
| 260 |
\endinsert
|
275 |
\endinsert
|
| 261 |
|
276 |
|
| 262 |
|
277 |
|
| 263 |
For ADC2 we must use formula with different constant \ref[ADC1-gain]. ADC2 module has LT6600-2.5 populated and gain is $A = 2.457$ with same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances of used setup.
|
278 |
For ADC2 we must use formula with different constant \ref[ADC1-gain]. ADC2 module has LT6600-2.5 populated and gain is $A = 2.457$ with same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances of used setup.
|
| 264 |
|
279 |
|
| 265 |
\label[ADC2-gain]
|
280 |
\label[ADC2-gain]
|
| 266 |
$$
|
281 |
$$
|
| 267 |
A = {1580 \times R_1 \over R_1 + R_2}
|
282 |
A = {1580 \cdot R_1 \over R_1 + R_2}
|
| 268 |
$$
|
283 |
$$
|
| 269 |
|
284 |
|
| 270 |
Where is
|
285 |
Where is
|
| 271 |
\begitems
|
286 |
\begitems
|
| 272 |
* $A$ - Gain of input amplifier.
|
287 |
* $A$ - Gain of input amplifier.
|
| 273 |
* $R_1$ - Output impedance of signal source (usually 50 Ohm).
|
288 |
* $R_1$ - Output impedance of signal source (usually 50 Ohm).
|
| 274 |
* $R_2$ - Value of serial resistors at operational amplifier inputs.
|
289 |
* $R_2$ - Value of serial resistors at operational amplifier inputs.
|
| 275 |
\enditems
|
290 |
\enditems
|
| 276 |
|
291 |
|
| 277 |
\midinsert
|
292 |
\midinsert
|
| 278 |
\clabel[ADC2-FFT]{ADC2 sine test FFT}
|
293 |
\clabel[ADC2-FFT]{ADC2 sine test FFT}
|
| 279 |
\picw=15cm \cinspic ./img/screenshots/ADC2_CH1_FFT.png
|
294 |
\picw=15cm \cinspic ./img/screenshots/ADC2_CH1_FFT.png
|
| 280 |
\caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices.
|
295 |
\caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices.
|
| 281 |
\endinsert
|
296 |
\endinsert
|
| 282 |
|
297 |
|
| 283 |
Computed FFT spectra for measured signal are shown in images \ref[ADC2-FFT] and \ref[ADC1-FFT]. Both images confirms that ADCdual01A modules have input dynamical range 80 dB at least.
|
298 |
Computed FFT spectra for measured signal are shown in images \ref[ADC2-FFT] and \ref[ADC1-FFT]. Both images confirms that ADCdual01A modules have input dynamical range 80 dB at least.
|
| 284 |
|
299 |
|
| 285 |
\chap Example of usage
|
300 |
\chap Example of usage
|
| 286 |
|
301 |
|
| 287 |
For additional validation of system design a receiver setup was constructed.
|
302 |
For additional validation of system design a receiver setup was constructed.
|
| 288 |
|
303 |
|
| 289 |
\sec Basic interferometer station
|
304 |
\sec Basic interferometer station
|
| 290 |
|
305 |
|
| 291 |
Interferometry station was selected as most basic setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematic of used setup is shown in image \ref[block-schematic]. Two ground-plane antennas were used and mounted outside of balcony at CTU building at location 50$^\circ$4'36.102"N, 14 $^\circ$ 25'4.170" E. Antennas were equipped by LNA01A amplifiers. Coaxial cable length are matched for 5 meters. And antennas were isolated by common mode ferrite bead mounted on cable for minimize signal coupling between antennas. Evaluation system consists SDGPSDO local oscillator subsystem used for tuning local oscillator frequency.
|
306 |
Interferometry station was selected as most basic setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematic of used setup is shown in image \ref[block-schematic]. Two ground-plane antennas were used and mounted outside of balcony at CTU building at location 50$^\circ$4'36.102"N, 14 $^\circ$ 25'4.170" E. Antennas were equipped by LNA01A amplifiers. Coaxial cable length are matched for 5 meters. And antennas were isolated by common mode ferrite bead mounted on cable for minimize signal coupling between antennas. Evaluation system consists SDGPSDO local oscillator subsystem used for tuning local oscillator frequency.
|
| 292 |
|
307 |
|
| 293 |
\midinsert
|
308 |
\midinsert
|
| 294 |
\clabel[block-schematic]{Receiver block schematic}
|
309 |
\clabel[block-schematic]{Receiver block schematic}
|
| 295 |
\picw=10cm \cinspic ./img/Coherent_UHF_SDR_receiver.png
|
310 |
\picw=10cm \cinspic ./img/Coherent_UHF_SDR_receiver.png
|
| 296 |
\caption/f Complete receiver block schematic of dual antenna interferometric station.
|
311 |
\caption/f Complete receiver block schematic of dual antenna interferometric station.
|
| 297 |
\endinsert
|
312 |
\endinsert
|
| 298 |
|
313 |
|
| - |
|
314 |
% doplnit schema skutecne pouziteho systemu
|
| - |
|
315 |
|
| - |
|
316 |
Despite of schematic diagram proposed on beginning of system description....
|
| - |
|
317 |
We used two separate oscillators -- one oscillator drives encode signal to ADCs still through FPGA based divider and other one drives SDRX01B mixer.
|
| - |
|
318 |
Reason for this modification is simplification of frequency tuning during experiment. It is because single oscillator may be used only with proper setting of FPGA divider, this divider may be modified only by recompilation of FPGA code and loading/flashing new FPGA schema. Due to fact that FPGA was connected to PCI express and kernel drivers and hardware must be reinitialized, reboot of PC is required. Instead of this procedure, we set the FPGA divider to constant division of factor 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver.
|
| 299 |
|
319 |
|
| 300 |
|
320 |
|
| 301 |
\midinsert
|
321 |
\midinsert
|
| 302 |
\clabel[meteor-reflection]{Meteor reflection}
|
322 |
\clabel[meteor-reflection]{Meteor reflection}
|
| 303 |
\picw=10cm \cinspic ./img/screenshots/observed_meteor.png
|
323 |
\picw=10cm \cinspic ./img/screenshots/observed_meteor.png
|
| 304 |
\caption/f Meteor reflection received by evaluation setup.
|
324 |
\caption/f Meteor reflection received by evaluation setup.
|
| 305 |
\endinsert
|
325 |
\endinsert
|
| 306 |
|
326 |
|
| 307 |
\midinsert
|
327 |
\midinsert
|
| 308 |
\clabel[phase-phase-difference]{Phase difference}
|
328 |
\clabel[phase-phase-difference]{Phase difference}
|
| 309 |
\picw=10cm \cinspic ./img/screenshots/phase_difference.png
|
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\picw=10cm \cinspic ./img/screenshots/phase_difference.png
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\caption/f Demonstration of phase difference between antennas.
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\caption/f Demonstration of phase difference between antennas.
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\endinsert
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\endinsert
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We use ACOUNT02A device for frequency checking on both local oscillators.
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%\sec Simple passive Doppler radar
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%\sec Simple passive Doppler radar
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%\sec Simple polarimeter station
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%\sec Simple polarimeter station
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\chap Proposed final system
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\chap Proposed final system
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Construction of a final system which is supposed to be employed for real radioastronomy observations will be described. This chapter is mainly a theoretical analysis of data handling systems. Realization of these ideas might be possible as a part of our future development after we fully evaluate and test the current trial design.
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Construction of a final system which is supposed to be employed for real radioastronomy observations will be described. This chapter is mainly a theoretical analysis of data handling systems. Realization of these ideas might be possible as a part of our future development after we fully evaluate and test the current trial design.
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The system requires proper handling of huge amounts of data and either huge and fast storage capacity is needed for store captured signal data, or enormous computational power is required for online data processing and filtering. Several hardware approach currently exist and are in use for data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially constructed ASICs are used for this task.
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The system requires proper handling of huge amounts of data and either huge and fast storage capacity is needed for store captured signal data, or enormous computational power is required for online data processing and filtering. Several hardware approach currently exist and are in use for data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially constructed ASICs are used for this task.
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\sec Custom design of FPGA board
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\sec Custom design of FPGA board
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In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than trial design. It should be compatible with MLAB which is further backward compatible with the existing or improved design of ADC modules. For a connection of this board to another adapter board with PCIe we expect a use of a host interface.
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In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than trial design. It should be compatible with MLAB which is further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface.
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Thunderbolt technology standard was expected to be used in this PC to PCIe -> FPGA module. Thunderbolt chips are currently available on the market for reasonable prices. However, a problem lies in the accessibility to their specifications, as they are only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution.
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Thunderbolt technology standard was expected to be used in this PC to PCIe module which further communicate with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as specification is only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need preserve standard PC as main computational platform.
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However, these systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing of thesis.
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However, these PCI express external systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing of thesis.
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Therefore, a better solution probably needs to be found.
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Therefore, a better solution probably needs to be found.
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An interfacing problem will by probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to increased demand of embedded technologies, which requires high computation capacity, low power consumption and small size -- especially smart phones. Many of those ARM based systems has interesting parameters for signal processing. This facts makes Intel's ix86 architecture unattractive for future project.
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\sec Parralella board computer
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\sec Parralella board computer
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%Parallella is gon
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Parallella is new product from Adapteva, Inc. \cite[parallella-board], this small supercomputer have been in development almost two years and only testing series of boards have been produced until now (first single-board computers with 16-core Epiphany chip were shipped December 2013) \cite[parallella-board]. This board have near ideal parameters for signal processing (provides around 50 GFLOPS of computational power). The board is equipped by Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and 866 MHz operating frequency, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. Completely this board provides In addition of that this board consume only 3 Watts of power if both Zynq and Epiphany cores are running.
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\midinsert
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\clabel[img-parallella-board]{Parallella board overview}
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\picw=15cm \cinspic ./img/ParallellaTopView31.png
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\caption/f Top view on Parallella-16 board \cite[parallella16-board].
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\endinsert
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If Parallella board will be used a new ADC interface board should be designed. Interfacing module will use four PEC connectors mounted on bottom of Parallella board. This doughter module should have MLAB compatible design preferably constructed as separable module for every Parallella's PEC connectors.
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Main imperfections of Parallella board is unknown lead time and absence of onboard data
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\sec GPU based computational system
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\sec GPU based computational system
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A new GPU development board NVIDIA K1, shown in the following picture \ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have ideal parameters for signal processing for a relatively low price of 192 USD. Unfortunately, they are currently only in pre-order release stage (in April 2014).
|
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A new GPU development board NVIDIA K1, shown in the following picture \ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have ideal parameters for signal processing for a relatively low price of 192 USD. Unfortunately, they are currently only in pre-order release stage (in April 2014).
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|
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|
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\midinsert
|
375 |
\midinsert
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\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}
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\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}
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| 343 |
\picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg
|
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\picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg
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\caption/f The NVIDIA Jetson TK1 Development Kit \url{https://developer.nvidia.com/jetson-tk1}.
|
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\caption/f The NVIDIA Jetson TK1 Development Kit \url{https://developer.nvidia.com/jetson-tk1}.
|
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\endinsert
|
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\endinsert
|
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