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#include "main.h" |
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#include "main.h" |
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#define VERSION 0.2 |
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#define VERSION 0.2 |
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|
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#define START PIN_D4 |
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#define START PIN_D4 |
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#define STOP1 PIN_D5 |
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#define STOP1 PIN_D5 |
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#define STOP2 PIN_D6 |
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#define STOP2 PIN_D6 |
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|
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#include "GP2.h" |
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#include "GP2.h" |
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|
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#define ONE_WIRE_PIN PIN_E2 |
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#define ONE_WIRE_PIN PIN_E2 |
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#include "ds1820.c" |
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#include "ds1820.c" |
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|
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|
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void main() |
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void main() |
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{ |
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{ |
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setup_adc_ports(NO_ANALOGS|VSS_VDD); |
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setup_adc_ports(NO_ANALOGS|VSS_VDD); |
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setup_adc(ADC_CLOCK_DIV_2); |
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setup_adc(ADC_CLOCK_DIV_2); |
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setup_psp(PSP_DISABLED); |
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setup_psp(PSP_DISABLED); |
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setup_spi(SPI_SS_DISABLED); |
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setup_spi(SPI_SS_DISABLED); |
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setup_wdt(WDT_OFF); |
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setup_wdt(WDT_OFF); |
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setup_timer_0(RTCC_INTERNAL); |
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setup_timer_0(RTCC_INTERNAL); |
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setup_timer_1(T1_DISABLED); |
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setup_timer_1(T1_DISABLED); |
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setup_timer_2(T2_DISABLED,0,1); |
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setup_timer_2(T2_DISABLED,0,1); |
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setup_ccp1(CCP_OFF); |
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setup_ccp1(CCP_OFF); |
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setup_comparator(NC_NC_NC_NC); |
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setup_comparator(NC_NC_NC_NC); |
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setup_vref(FALSE); |
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setup_vref(FALSE); |
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|
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|
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TDC_reset(); |
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TDC_reset(); |
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|
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|
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output_low(START); |
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output_low(START); |
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output_low(STOP1); |
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output_low(STOP1); |
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output_low(STOP2); |
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output_low(STOP2); |
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|
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|
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delay_ms(50); |
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delay_ms(50); |
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|
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|
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/* |
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/* |
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1 0 0 0 0 ADR2 ADR1 ADR0 Write into address ADR |
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1 0 0 0 0 ADR2 ADR1 ADR0 Write into address ADR |
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1 0 1 1 0 ADR2 ADR1 ADR0 Read from address ADR |
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1 0 1 1 0 ADR2 ADR1 ADR0 Read from address ADR |
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0 1 1 1 0 0 0 0 Init |
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0 1 1 1 0 0 0 0 Init |
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0 1 0 1 0 0 0 0 Power On Reset |
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0 1 0 1 0 0 0 0 Power On Reset |
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0 0 0 0 0 0 0 1 Start_Cycle |
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0 0 0 0 0 0 0 1 Start_Cycle |
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0 0 0 0 0 0 1 0 Start_Temp |
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0 0 0 0 0 0 1 0 Start_Temp |
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0 0 0 0 0 0 1 1 Start_Cal_Resonator |
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0 0 0 0 0 0 1 1 Start_Cal_Resonator |
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0 0 0 0 0 1 0 0 Start_Cal_TDC |
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0 0 0 0 0 1 0 0 Start_Cal_TDC |
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*/ |
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*/ |
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|
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|
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int32 ble; |
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int32 ble; |
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int16 ret16; |
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int16 ret16; |
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int8 ret8; |
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int8 ret8; |
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|
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|
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|
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|
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while(TRUE) |
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while(TRUE) |
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{ |
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{ |
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delay_ms(100); |
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delay_ms(100); |
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|
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|
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|
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|
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TDC_reset(); |
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TDC_reset(); |
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delay_ms(100); |
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delay_ms(100); |
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|
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|
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//----------------------------------------------- Nastaveni registru |
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//----------------------------------------------- Nastaveni registru |
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output_low(TDC_ENABLE); |
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/* output_low(TDC_ENABLE); |
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ble=0; |
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ble=0; |
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ble=(8<<28)|(0<<24); // write addres |
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ble=(8<<28)|(0<<24); // write addres |
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ble|=(0<<20)|(0<<16)|(0<<14)|(3<<12)|(1<<10)|(0<<9)|(0<<8)|(0<<7)|(1<<6)|(1<<5)|(0<<4)|(1<<3)|(0<<2)|(0<<1)|0; |
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ble|=(0<<20)|(0<<16)|(0<<14)|(3<<12)|(1<<10)|(0<<9)|(0<<8)|(0<<7)|(1<<6)|(1<<5)|(0<<4)|(1<<3)|(0<<2)|(0<<1)|0; |
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spi_xfer(TDC_stream,ble,32); |
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spi_xfer(TDC_stream,ble,32); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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|
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|
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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ble=0; |
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ble=0; |
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ble=(8<<28)|(1<<24); |
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ble=(8<<28)|(1<<24); |
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ble|=(2<<20)|(1<<16)|(0<<15)|(1<<14)|(0<<11)|(4<<8)|0; |
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ble|=(2<<20)|(1<<16)|(0<<15)|(1<<14)|(0<<11)|(4<<8)|0; |
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spi_xfer(TDC_stream,ble,32); |
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spi_xfer(TDC_stream,ble,32); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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|
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|
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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ble=0; |
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ble=0; |
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ble=(8<<28)|(2<<24); |
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ble=(8<<28)|(2<<24); |
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ble|=(1<<21)|(1<<20)|(1<<19)|0; |
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ble|=(1<<21)|(1<<20)|(1<<19)|0; |
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spi_xfer(TDC_stream,ble,32); |
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spi_xfer(TDC_stream,ble,32); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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|
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|
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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ble=0; |
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ble=0; |
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ble=(8<<28)|(3<<24); |
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ble=(8<<28)|(3<<24); |
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ble|=(0<<22)|(1<<21)|(1<<20)|(1<<19)|0; |
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ble|=(0<<22)|(1<<21)|(1<<20)|(1<<19)|0; |
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spi_xfer(TDC_stream,ble,32); |
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spi_xfer(TDC_stream,ble,32); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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|
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|
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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ble=0; |
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ble=0; |
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ble=(8<<28)|(4<<24); |
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ble=(8<<28)|(4<<24); |
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ble|=(4<<19)|0; |
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ble|=(4<<19)|0; |
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spi_xfer(TDC_stream,ble,32); |
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spi_xfer(TDC_stream,ble,32); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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|
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|
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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ble=0; |
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ble=0; |
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ble=(8<<28)|(5<<24); |
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ble=(8<<28)|(5<<24); |
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ble|=(0<<21)|(0<<20)|(0<<19)|(0<<16)|0; |
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ble|=(0<<21)|(0<<20)|(0<<19)|(0<<16)|0; |
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spi_xfer(TDC_stream,ble,32); |
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spi_xfer(TDC_stream,ble,32); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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|
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*/ |
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|
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|
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|
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hit1=TDC_MRANGE2_HIT1_START; |
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|
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// hit2=TDC_MRANGE2_HIT2_2CH1; |
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|
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hitin1=TDC_HITIN1_4; |
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|
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hitin2=TDC_HITIN2_0; |
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|
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en_int= TDC_INT_ALU | TDC_INT_ENDHIT | TDC_INT_TIMEOUT; |
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|
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en_err_val=TDC_ERRVAL_EN; |
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|
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delval1=0x0; |
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|
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delval2=0x0; |
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|
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delval3=0x0; |
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|
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|
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|
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TDC_update_registers(); |
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|
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|
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//----------------------------------------------- Vypis registru |
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//----------------------------------------------- Vypis registru |
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|
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|
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printf("- %LX %LX %LX %LX ", TDC_get_measurement(1), TDC_get_measurement(2), TDC_get_measurement(3), TDC_get_measurement(4)); |
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printf("- %LX %LX %LX %LX ", TDC_get_measurement(1), TDC_get_measurement(2), TDC_get_measurement(3), TDC_get_measurement(4)); |
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|
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|
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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ret8=0; |
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ret8=0; |
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ret8=(0b1011<<4)|4; |
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ret8=(0b1011<<4)|4; |
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spi_xfer(TDC_stream,ret8,8); |
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spi_xfer(TDC_stream,ret8,8); |
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ret16=spi_xfer(TDC_stream,0,16); |
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ret16=spi_xfer(TDC_stream,0,16); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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printf("[%Lu %Lu %Lu %Lu %Lu %Lu %Lu] ", (1&(ret16)>>12), (1&(ret16)>>11), (1&(ret16)>>10), 1&(ret16)>>9, 7&(ret16)>>6, 7&(ret16)>>3, 7&ret16); |
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printf("[%Lu %Lu %Lu %Lu %Lu %Lu %Lu] ", (1&(ret16)>>12), (1&(ret16)>>11), (1&(ret16)>>10), 1&(ret16)>>9, 7&(ret16)>>6, 7&(ret16)>>3, 7&ret16); |
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|
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|
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printf("%X\r\n",TDC_get_reg1()); |
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printf("%X\r\n",TDC_get_reg1()); |
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|
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|
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//----------------------------------------------- Mereni |
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//----------------------------------------------- Mereni |
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|
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|
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TDC_init(); |
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TDC_init(); |
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|
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|
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delay_ms(50); |
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delay_ms(50); |
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|
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|
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TDC_start_cycle(); |
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TDC_start_cycle(); |
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|
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|
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delay_ms(200); |
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delay_ms(200); |
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|
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|
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output_high(STOP2); // Merime jenom jednim kanalem (druhy zrejme musi byt v H) |
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output_high(STOP2); // Merime jenom jednim kanalem (druhy zrejme musi byt v H) |
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|
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|
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output_high(START); |
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output_high(START); |
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output_low(START); |
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output_low(START); |
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delay_us(1); |
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delay_us(1); |
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|
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|
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output_high(STOP1); |
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output_high(STOP1); |
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output_low(STOP1); |
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output_low(STOP1); |
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delay_us(1); |
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delay_us(1); |
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|
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|
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|
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|
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output_high(STOP1); |
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output_high(STOP1); |
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output_low(STOP1); |
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output_low(STOP1); |
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delay_us(1); |
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delay_us(1); |
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|
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|
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output_high(STOP1); |
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output_high(STOP1); |
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output_low(STOP1); |
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output_low(STOP1); |
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delay_us(1); |
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delay_us(1); |
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|
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|
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|
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|
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|
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|
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//----------------------------------------------- Pocitani |
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//----------------------------------------------- Pocitani |
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int32 nn; |
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int32 nn; |
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for(nn=3;nn<=5;nn++) |
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for(nn=1;nn<=3;nn++) |
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{ |
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{ |
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delay_ms(500); |
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delay_ms(500); |
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|
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|
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printf("* %LX %LX %LX %LX ", TDC_get_measurement(1), TDC_get_measurement(2), TDC_get_measurement(3), TDC_get_measurement(4)); |
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printf("* %LX %LX %LX %LX ", TDC_get_measurement(1), TDC_get_measurement(2), TDC_get_measurement(3), TDC_get_measurement(4)); |
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|
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|
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output_low(TDC_ENABLE); //status register |
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output_low(TDC_ENABLE); //status register |
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ret8=0; |
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ret8=0; |
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ret8=(0b1011<<4)|4; |
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ret8=(0b1011<<4)|4; |
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spi_xfer(TDC_stream,ret8,8); |
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spi_xfer(TDC_stream,ret8,8); |
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ret16=spi_xfer(TDC_stream,0,16); |
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ret16=spi_xfer(TDC_stream,0,16); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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printf("[%Lu %Lu %Lu %Lu %Lu %Lu %Lu] ", (1&(ret16)>>12), (1&(ret16)>>11), (1&(ret16)>>10), 1&(ret16)>>9, 7&(ret16)>>6, 7&(ret16)>>3, 7&ret16); |
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printf("[%Lu %Lu %Lu %Lu %Lu %Lu %Lu] ", (1&(ret16)>>12), (1&(ret16)>>11), (1&(ret16)>>10), 1&(ret16)>>9, 7&(ret16)>>6, 7&(ret16)>>3, 7&ret16); |
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|
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|
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printf("%X\r\n",TDC_get_reg1()); |
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printf("%X\r\n",TDC_get_reg1()); |
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|
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|
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// Next calculation |
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switch (nn) |
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output_low(TDC_ENABLE); |
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{ |
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ble=0; |
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case 1: |
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ble=(8<<28)|(1<<24); // write to reg1 |
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hit2=TDC_MRANGE2_HIT2_1CH1; |
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ble|=(nn<<20)|(1<<16)|(0<<15)|(1<<14)|(0<<11)|(4<<8)|0x00; |
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break; |
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|
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|
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spi_xfer(TDC_stream,ble,32); |
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case 2: |
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output_high(TDC_ENABLE); |
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hit2=TDC_MRANGE2_HIT2_2CH1; |
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|
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break; |
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} |
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|
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|
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|
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} |
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|
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|
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|
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|
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case 3: |
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|
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hit2=TDC_MRANGE2_HIT2_3CH1; |
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|
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break; |
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|
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} |
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|
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TDC_update_reg1(); |
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|
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} |
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|
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} |
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} |
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} |