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\chap Testing construction
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\chap Testing construction
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\sec Required parameters
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\sec Required parameters
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Wide dynamical range and high 3 intercept point are desired. The receiver must accept wide dynamic signals because classic radioastronomy signal in typically weak signal covered by strong man made noise signal.
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Wide dynamical range and high 3 intercept point are desired. The receiver must accept wide dynamic signals because classic radioastronomy signal in typically weak signal covered by strong man made noise signal.
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\sec Sampling frequency
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\sec Sampling frequency
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Sampling frequency is limited by technical constrains in testing construction design. This parameter is especially limited by sampling frequencies of analog to digital conversion chips accessible on market. Combination of required parameters -- dynamic range which needs 16bit at least and minimum sampling frequency of 1 MSPS, leads to high end ADC chips. Which does not support such low sampling frequencies at all. Its minimum sampling frequency is 5 MSPS.
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Sampling frequency is limited by technical constrains in testing construction design. This parameter is especially limited by sampling frequencies of analog to digital conversion chips accessible on market. Combination of required parameters -- dynamic range which needs 16bit at least and minimum sampling frequency of 1 MSPS, leads to high end ADC chips. Which does not support such low sampling frequencies at all. Its minimum sampling frequency is 5 MSPS.
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\sec System scalability
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\sec System scalability
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For analog channels scalability special parameters of ADC modules were needed. ADC module ideally needs separate output for each I/Q channel. ADC module must have separate inputs for sampling and for data output clocks. This parameters allows conduction of relatively low digital data rates. And digital signal can be conducted on long wires.
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For analog channels scalability special parameters of ADC modules were needed. ADC module ideally needs separate output for each I/Q channel. ADC module must have separate inputs for sampling and for data output clocks. This parameters allows conduction of relatively low digital data rates. And digital signal can be conducted on long wires.
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Clock signal will be handled specially in this scalable design. Selected ADC chip guaranteed defined clock skew between sampling and data output clock. This allows taking data and frame clocks from first ADC module only. Other data and frame clocks from other ADC modules can be measured for diagnostic purposes. (Failure detection, jitter measurement etc.)
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Clock signal will be handled specially in this scalable design. Selected ADC chip guaranteed defined clock skew between sampling and data output clock. This allows taking data and frame clocks from first ADC module only. Other data and frame clocks from other ADC modules can be measured for diagnostic purposes. (Failure detection, jitter measurement etc.)
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This system concept allows scalability technically limited by number of differential signals on host side, and its computational power. There is another advantage of scalable data acquisition system -- economic reasons. Observatories or end user can pick choice how much money they are able to spent in radioastronomy receiver system. This option is especially useful for science sites without previous experience with radioastronomy observations.
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This system concept allows scalability technically limited by number of differential signals on host side, and its computational power. There is another advantage of scalable data acquisition system -- economic reasons. Observatories or end user can pick choice how much money they are able to spent in radioastronomy receiver system. This option is especially useful for science sites without previous experience with radioastronomy observations.
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\secc Differential signalling
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\secc Differential signalling
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This concept of scalable design requires relatively long traces between ADC and digital unit which captures the data and performs computations. Distance of digital processing unit and analog to digital conversion unit has advantage in noise retention typically produced by digital circuits. Those digital circuits such as FPGA or other flip-flops block and traces usually works on high frequencies and emits wideband noise with relatively low power. In such case any distance increase between noise source and analog signal source increase S/N significantly. But this distance also brings problems with digital signal transmission between ADC and computational unit. But this obstruction should be resolved easier in free space than on board routing. The high quality differential signalling shielded cables should be used. This technology have two advantages on PCB signal routing. It can use two wire twisting for leak inductance suppression of signal path. And this twisted pair may be additionally shielded by uninterrupted metal foil.
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This concept of scalable design requires relatively long traces between ADC and digital unit which captures the data and performs computations. Distance of digital processing unit and analog to digital conversion unit has advantage in noise retention typically produced by digital circuits. Those digital circuits such as FPGA or other flip-flops block and traces usually works on high frequencies and emits wideband noise with relatively low power. In such case any distance increase between noise source and analog signal source increase S/N significantly. But this distance also brings problems with digital signal transmission between ADC and computational unit. But this obstruction should be resolved easier in free space than on board routing. The high quality differential signalling shielded cables should be used. This technology have two advantages on PCB signal routing. It can use two wire twisting for leak inductance suppression of signal path. And this twisted pair may be additionally shielded by uninterrupted metal foil.
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\secc Phase matching
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For multiple antenna radioastronomy project, system phase stability is mandatory. It allows precise high resolution imaging of object.
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High phase stability in this scalable design is achieved by centralised frequency generation and distribution with multi-output LVPECL hubs. These hubs have equiphased outputs for multiple devices.
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This design ensures that all devices have access to defined phase and known frequency.
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\sec System description
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\sec System description
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In this section testing system will be described.
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In this section testing system will be described.
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\secc Frequency synthesis
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\secc Frequency synthesis
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Centralised topology was used for frequency synthesis. One precise high frequency and low jitter digital oscillator was used and other working frequencies are delivered by division from it. This central oscillator has software defined GPS disciplined control loop for frequency stabilisation. This method was used in order to meet modern requirements on radioastronomy equipment, which needs precise frequency and phase stability on wide area for effective radioastronomy imaging.
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Centralised topology was used for frequency synthesis. One precise high frequency and low jitter digital oscillator was used and other working frequencies are delivered by division from it. This central oscillator has software defined GPS disciplined control loop for frequency stabilisation.\ref{gpsdo} This method was used in order to meet modern requirements on radioastronomy equipment, which needs precise frequency and phase stability on wide area for effective radioastronomy imaging.
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\fnote{This design was developed in parallel to this diploma thesis construction as related project, but it is not explicitly required by specification.}
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\secc Signal connectors
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\secc Signal connectors
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Several widely used and commercially easily accessible differential connectors was considered.
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Several widely used and commercially easily accessible differential connectors was considered.
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\begitems
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\begitems
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* <del>[[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
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* <del>[[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
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* [[http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]
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* [[http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]
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* <del>[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>
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* <del>[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>
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\enditems
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\enditems
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MiniSAS connector was chosen as the best for use in connection multiple ADC modules. This miniSAS connector is compatible with existing SATA cabling system. Translation between SATA and miniSAS is achieved by SAS to SATA adapter cable. This cable is used in servers to connecting SAS controller to multiple SATA hard disc in RAID systems.
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MiniSAS connector was chosen as the best for use in connection multiple ADC modules. This miniSAS connector is compatible with existing SATA cabling system. Translation between SATA and miniSAS is achieved by SAS to SATA adapter cable. This cable is used in servers to connecting SAS controller to multiple SATA hard disc in RAID systems.
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\secc Design of ADC modules
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\secc Design of ADC modules
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For PCB layout KiCAD design suite was used. Used version has the CERN Push \& Shove routing capability integrated but was slightly unstable and sometimes falls on exception during routing. Design must be often saved due to this stability issues. But Open-source KiCAD works well compared to commercial solutions as MentorGraphics PADS or Cadence Orcad. And much better than widely used Eagle software.
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For PCB layout KiCAD design suite was used. Used version has the CERN Push \& Shove routing capability integrated but was slightly unstable and sometimes falls on exception during routing. Design must be often saved due to this stability issues. But Open-source KiCAD works well compared to commercial solutions as MentorGraphics PADS or Cadence Orcad. And much better than widely used Eagle software.
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New PCB footprints must be designed for FMC, SATA a and miniSAS connectors. These new footprints were committed to KiCAD github library repository. They are now publicly accessible from official KiCAD repository at GitHub.
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New PCB footprints must be designed for FMC, SATA a and miniSAS connectors. These new footprints were committed to KiCAD github library repository. They are now publicly accessible from official KiCAD repository at GitHub.
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\secc ADC modules interface
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\secc ADC modules interface
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All two ADCdual01A modules was connected to FPGA ML605 board trough
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All two ADCdual01A modules was connected to FPGA ML605 board trough FMC2DIFF01A adapter board. Construction of this adapter module suppose FMC LPC connector. And this board is not MLAB compatible design. But this board is designed to meet VITA 57 standard specification for boards which uses zone 1 and zone 3.
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This specification guarantee compatibility with others FPGA board which has FMC LPC connector for mezzane cards. Schematic diagram of this adapter board is included in appendix.
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\midinsert
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\midinsert
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\picw=10cm \cinspic ./img/ML605-board.jpg
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\picw=10cm \cinspic ./img/ML605-board.jpg
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\caption/f Used FPGA ML605 development board.
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\caption/f Used FPGA ML605 development board.
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\endinsert
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\endinsert
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Several SATA connectors and two miniSAS connectors are populated on this board. This set of connectors allows connection of any number of ADC modules in range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors. Other supporting signal should be routed directly to SATA connectors on adapter.
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Signal configuration used in testing construction is described in tables.
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\secc Output data format
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\secc Output data format
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\midinsert
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\midinsert
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\ctable {cccccccccc}{
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\ctable {cccccccccc}{
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\hfil
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\hfil
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& \multispan9 \hfil 160bit packet \hfil \crl \tskip4pt
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& \multispan9 \hfil 160bit packet \hfil \crl \tskip4pt
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Data name & FRAME & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2 \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil \cr
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Data name & FRAME & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2 \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil \cr
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Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr
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Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr
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Content & saw signal & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ \cr
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Content & saw signal & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ \cr
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}
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}
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\caption/t System device "/dev/xillybus_data2_r" data format
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\caption/t System device "/dev/xillybus_data2_r" data format
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\endinsert
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\endinsert
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\sec Achieved parameters
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\sec Achieved parameters
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\secc Data reading and recording
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\secc Data reading and recording
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For reading data stream from ADC driver Gnuradio software was used. Gnuradio suite consist gnuradio-companion which is a graphical tool for creating signal flow graphs and generating flow-graph source code. This tool was used to create basic RAW data grabber to record and interactive wiev data stream output from ADC modules.
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For reading data stream from ADC driver Gnuradio software was used. Gnuradio suite consist gnuradio-companion which is a graphical tool for creating signal flow graphs and generating flow-graph source code. This tool was used to create basic RAW data grabber to record and interactive wiev data stream output from ADC modules.
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\midinsert
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\midinsert
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\picw=15cm \cinspic ./img/screenshots/Grabber.grc.png
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\picw=15cm \cinspic ./img/screenshots/Grabber.grc.png
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\caption/f ADC recorder flow graph created in gnuradio-companion.
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\caption/f ADC recorder flow graph created in gnuradio-companion.
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\endinsert
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\endinsert
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\midinsert
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\midinsert
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\picw=15cm \cinspic ./img/screenshots/Grabber_running.png
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\picw=15cm \cinspic ./img/screenshots/Grabber_running.png
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\caption/f User interface window of running ADC grabber.
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\caption/f User interface window of running ADC grabber.
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\endinsert
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\endinsert
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Interactive graber wiewer user interface shows live osciloscope-like time-value display for all data channels and live time-frequency scrolling display (waterfall wiev) for displaying frequency components of grabbed signal.
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Interactive graber wiewer user interface shows live osciloscope-like time-value display for all data channels and live time-frequency scrolling display (waterfall wiev) for displaying frequency components of grabbed signal.
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\sec Future improvements
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\sec Future improvements
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Several ADC module imperfections such as useless separation of FRAME and DCO signal to two connectors should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest.
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Several ADC module imperfections such as useless separation of FRAME and DCO signal to two connectors should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest.
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%\chap Example of usage
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%\chap Example of usage
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%\sec Simple polarimeter station
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%\sec Simple polarimeter station
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%\sec Basic interferometer station
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%\sec Basic interferometer station
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%\sec Simple passive Doppler radar
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%\sec Simple passive Doppler radar
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\chap Proposed final system
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\chap Proposed final system
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Construction of final system which should be used for real radioastronomy observations will be described. This chapter is mainly theoretical analysis of systems which should be used for data handling.
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Construction of final system which should be used for real radioastronomy observations will be described. This chapter is mainly theoretical analysis of systems which should be used for data handling.
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\sec Custom design of FPGA board
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\sec Custom design of FPGA board
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\sec Parralella board computer
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\sec Parralella board computer
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Parallella is gon
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Parallella is gon
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\sec GPU based computational system
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\sec GPU based computational system
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\chap Conclusion
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\chap Conclusion
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Special design of scalable data-aquisition system was proposed. This system has parameters
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Special design of scalable data-aquisition system was proposed. This system has parameters
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