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\chap Trial version of the receiver, design and implementation
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\chap Trial version of the receiver, design and implementation
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The whole design of radioastronomy receiver digitalization unit is constructed to be used in a wide range of applications and tasks related to digitalization of signal from radioastronomy receivers. A good illustrating problem for its use is a signal digitalisation from multiple antenna arrays.
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The whole design of radioastronomy receiver digitalization unit is constructed to be used in a wide range of applications and tasks related to digitalization of signal from radioastronomy receivers. A good illustrating problem for its use is a signal digitalisation from multiple antenna arrays.
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\midinsert
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\midinsert
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\clabel[expected-block-schematic]{Expected system block schematic}
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\clabel[expected-block-schematic]{Expected system block schematic}
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\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png }
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\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png }
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\par\nobreak \vskip\wd0 \vskip-\ht0
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\par\nobreak \vskip\wd0 \vskip-\ht0
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\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}
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\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}
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\caption/f Expected realisation of signal digitalisation unit.
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\caption/f Expected realisation of signal digitalisation unit.
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\endinsert
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\endinsert
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\sec Required parameters
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\sec Required parameters
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We require following technical parameter, to supersede existing digitalization units solutions.
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We require the following technical parameters, to supersede existing digitalization units solutions.
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Primarily, we need wide dynamical range and high IP3. The receiver must accept wide dynamic signals because a typical radioastronomical signal has a form of a weak signal covered by a strong man-made noise or other undesired noises as lighting, Sun emissions etc.
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Primarily, we need wide a dynamical range and high IP3. The receiver must accept wide dynamic signals because a typical radioastronomical signal has a form of a weak signal covered by a strong man-made noise or other undesired noises as lighting, Sun emissions etc.
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Summary of other additional required parameters follows
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Summary of other additional required parameters follows
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\begitems
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\begitems
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  * Dynamical range better than 80 dB see section \ref[dynamic-range-theory] for explanation
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  * Dynamical range better than 80 dB, see section \ref[dynamic-range-theory] for explanation
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  * Phase stability between channels
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  * Phase stability between channels
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  * Low noise (all types)
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  * Low noise (all types)
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  * Sampling jitter better than 100 metres
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  * Sampling jitter better than 100 metres
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  * Support for any number of receivers in range 1 to 8
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  * Support for any number of receivers in the range of 1 to 8
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\enditems
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\enditems
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Now we analyze several of the parameters in detail.
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Now we analyze several of the parameters in detail.
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\sec Sampling frequency
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\sec Sampling frequency
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Sampling frequency is not limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market and interface bandwidth. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1$\ $MSPS leads to need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5$\ $MSPS.
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Sampling frequency is not limited by the technical constrains in the trial version. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market and interface bandwidth. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1$\ $MSPS leads to the need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5$\ $MSPS.
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We calculate minimum data bandwidth data rate for eight receivers, 2 bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/s. Such data rate is at the limit of real writing speed o classical HDD and it is almost double of real bandwidth of USB 2.0 interface. As result of this facts we must use faster interface. Faster interface is especially needed in case where we need faster sampling rates than ADC minimal 5$\ $MSPS sample rate.
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We calculated a minimum data bandwidth data rate for eight receivers, 2 bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/s. Such data rate is at the limit of the actual writing speed of classical HDD and it is almost double the real bandwidth of USB 2.0 interface. As a result of these facts we must use faster interface. Faster interface is especially needed in cases where we require faster sampling rates than ADC's minimal 5$\ $MSPS sample rate.
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Most perspective interfaces for use in our type of application is USB 3.0 or PCI Express interface. Although USB 3.0 is new technology without availability of good development tools. We used PCI Express interface as simplest and most reliable solution.
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The most perspective interface for use in our type of application is USB 3.0 or PCI Express interface. However, USB 3.0 is a relatively new technology without good development tools currently available. We have used PCI Express interface as the simplest and the most reliable solution.
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\sec System scalability
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\sec System scalability
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For analogue channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each analogue channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow for conduction at relatively low digital data rates. As a result, the digital signal can be conducted even through long wires. Modular concept allows separation from central logic which support optimization of number analogue channels.
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For analogue channels' scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each analogue channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow for conduction at relatively low digital data rates. As a result, the digital signal can be conducted even through long wires. Modular concept allows a separation from central logical unit which supports optimization of number analogue channels.
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Clock and data signals will be then handled distinctively in our modular scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.) but these redundant signals are not used for data sampling. If more robustness is required in final application, DCO and FR signal may be collected from other modules and routed through an voting logic which will correct possible signal defects.
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Clock and data signals will be then handled distinctively in our modular scalable design. Selected ADC chips are guaranteed to have defined clock skew between the sampling and data output clocks. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.), but these redundant signals are not used for data sampling. If more robustness is required in the final application, DCO and FR signals may be collected from other modules and routed through an voting logic which will correct possible signal defects.
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This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power.  There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.
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This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power.  There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.
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\secc Differential signaling
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\secc Differential signalling
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The above mentioned concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA, Ethernet or other flip-flops blocks and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such cases any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time a long distance brings problems with the digital signal transmission between ADC and computational unit. But this obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used such as massively produced and cheap SATA cables. This technology has two advantages over PCB signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path and second, the twisted pair may additionally be shielded by uninterrupted metal foil.
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The above mentioned concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA, Ethernet or other flip-flops blocks and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such cases any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time, a long distance brings problems with the digital signal transmission between ADC and computational unit. But this obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used, such as massively produced and cheap SATA cables. This technology has two advantages over PCB signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path and second, the twisted pair may additionally be shielded by uninterrupted metal foil.
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\secc Phase matching
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\secc Phase matching
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For multiple antenna radioastronomy projects, system phase stability is a mandatory condition. It allows precise high resolution imaging of objects, increases signal to noise ratios in several observation methods and allows use of advanced algorithms for signal processing.
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For multiple antenna radioastronomy projects, system phase stability is a mandatory condition. It allows a precise, high resolution imaging of objects, increases signal to noise ratios in several observation methods and allows the use of advanced algorithms for signal processing.
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High phase stability in our scalable design is achieved through centralized frequency generation  and distribution with multi-output LVPECL hubs (CLKHUB02A), that have equiphased outputs for multiple devices. LVPECL logic is used on every system critical clock signal distribution hub. LVPECL logic has advantage over LVDS in signal integrity robustness. LVPECL uses higher logical levels and higher signalling currents. Power consumption of LVPECL logic are near constant over operating frequency range due to use of bipolar transistors this minimizes voltage glitches which are typical for CMOS logic. One drawbacks of that parameters is high power consumption of LVPECL logic which easily reach tens of milliamperes per device.
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High phase stability in our scalable design is achieved through centralized frequency generation  and distribution with multi-output LVPECL hubs (CLKHUB02A), that have equiphased outputs for multiple devices. LVPECL logic is used on every system critical clock signal distribution hub. LVPECL logic has an advantage over LVDS in signal integrity robustness. LVPECL uses higher logical levels and higher signalling currents. Power consumption of LVPECL logic is nearly constant over the operating frequency range due to the use of bipolar transistors. This minimizes voltage glitches which are typical for CMOS logic. One drawback of its parameters is a high power consumption of LVPECL logic which easily reaches tens of milliamperes per device.
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This design ensures that all system devices have access to the defined phase and known frequency.
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This design ensures that all system devices have access to the defined phase and known frequency.
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\sec System description
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\sec System description
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In this section testing system based on Xilinx ML605 development board \ref[ML605-development-board] will be described. This board was used in previous finished project and was unused until now, but FPGA parrameters are more than enough we need in fast data aquisition system.
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This section deals with the description of the trial version based on Xilinx ML605 development board \ref[ML605-development-board]. The board had been used in a previous project and has not been used since then, but the FPGA parameters are more than sufficient of what we need for fast data acquisition system.
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\secc Frequency synthesis
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\secc Frequency synthesis
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We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO], while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis. Thus is described in separate document}
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We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO], while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the thesis itself and thus it is described in a separate document}
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We have used new methods of software frequency monitoring and compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide baseline scales for effective radioastronomy imaging.
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We have used new methods of software frequency monitoring and compensation in order to meet modern requirements on radioastronomy equipment which need precise frequency and phase stability over a wide baseline scales for effective radioastronomy imaging.
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GPSDO device consists the Si570 chip with LVPECL output. Phase jitter of GPSDO is determined mainly by Si570 phase noise. Parameters of used Si570 from source \cite[si570-chip] are summarized in table \ref[LO-noise].
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The GPSDO device consists of Si570 chip with LVPECL output. Phase jitter of GPSDO is determined mainly by Si570 phase noise. Parameters of the Si570 are summarized in the following table \ref[LO-noise] (source \cite[si570-chip] ).
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GPSDO design included in data acquisition system has special feature -- generates time marks for precise time-stamping of received signal. Timestamps are created by disabling of local oscillator outputs connected to SDRX01B receivers for 100 us.  As result rectangle click in ADC input signal is created which appears as horizontal line in spectrogram.
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The GPSDO design, that is included in data acquisition system, has special feature -- it generates time marks for a precise time-stamping of the received signal. Timestamps are created by disabling the local oscillator's outputs, connected to SDRX01B receivers, for 100 us.  As result, a rectangular click in the ADC input signal is created which appears as a horizontal line in spectrogram.
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Timestamps should be seen in image \ref[meteor-reflection] (above and below meteor reflection).
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Timestamps should be seen in image \ref[meteor-reflection] (above and below the meteor reflection).
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Time-marking should be improved in future by digitalization of GPS signal received by antenna on observational station. GPS signal can be then directly sampled by dedicated receiver and one separate ADC module. Datafile then consists samples from channels of radio-astronomy receivers along with GPS signal containing precise time information.
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Time-marking should be improved in future by digitalization of GPS signal received by antenna on observational station. Following that, the GPS signal can be directly sampled by a dedicated receiver and one separate ADC module. Datafile then consists of samples from channels of radio-astronomy receivers along with the GPS signal containing precise time information.
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\midinsert \clabel[LO-noise]{Phase noise of used local oscillator}
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\midinsert \clabel[LO-noise]{Phase noise of the local oscillator}
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\ctable{lcc}{
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\ctable{lcc}{
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	&	 \multispan2 \hfil Phase Noise [dBc/Hz] \hfil 		\cr
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	&	 \multispan2 \hfil Phase Noise [dBc/Hz] \hfil 		\cr
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Offset Frequency	&	$F_{out}$ 156.25 MHz	& $F_{out}$ 622.08 MHz \cr
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Offset Frequency	&	$F_{out}$ 156.25 MHz	& $F_{out}$ 622.08 MHz \cr
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100 [Hz]	&	–105	&	–97 \cr
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100 [Hz]	&	–105	&	–97 \cr
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1 [kHz]	&	–122	&	–107 \cr
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1 [kHz]	&	–122	&	–107 \cr
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10 [kHz]	&	–128	&	–116 \cr
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10 [kHz]	&	–128	&	–116 \cr
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100 [kHz]	&	–135	&	–121 \cr
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100 [kHz]	&	–135	&	–121 \cr
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1 [MHz]	&	–144	&	–134 \cr
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1 [MHz]	&	–144	&	–134 \cr
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10 [MHz]	&	–147	&	–146 \cr
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10 [MHz]	&	–147	&	–146 \cr
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100 [MHz]	&	n/a	&	–148 \cr
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100 [MHz]	&	n/a	&	–148 \cr
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}
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}
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\caption/t Phase noise of used Silicon Laboratories Si570 chip. Offset frequency is measured from carrier frequency. Values are tabled for two district carrier frequencies.
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\caption/t Phase noise of the used Silicon Laboratories Si570 chip. Offset frequency is measured from carrier frequency. Values shown in the table are given for two different carrier frequencies.
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\endinsert
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\endinsert
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from main local oscillator.  This signal should use high quality differential signaling cable -- we should use SATA cable for this purpose. FPGA may slightly affect clock signal quality by additive noise, but has negligible effect in application where developed system will be used.
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from the main local oscillator.  This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose. FPGA may slightly affect the clock signal quality by adding a noise, but it has a negligible effect on the application where developed system will be used.
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\secc Signal cable connectors
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\secc Signal cable connectors
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\label[signal-cables]
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\label[signal-cables]
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Several widely used and commercially easily accessible differential connectors were considered to be use in our design.
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Several widely used and commercially easily accessible differential connectors were considered to be use in our design.
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\begitems
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\begitems
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* HDMI % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
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* HDMI % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
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* SATA  		%{http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]
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* SATA  		%{http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]
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* DisplayPort 		%[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>
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* DisplayPort 		%[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>
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* SAS/miniSAS
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* SAS/miniSAS
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\enditems
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\enditems
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At the end, MiniSAS connector was chosen as the best option to be used in connecting together multiple ADC modules. A transition between SATA and miniSAS is achieved by SAS to SATA adapter cable which is commonly used in servers to connect SAS controller to multiple SATA hard disc in RAID systems and thus is commercially easily available. It is compatible with existing SATA cabling systems and aggregates multiple SATA cables to a single connector, it has SPI configuration lines which can be seen on the following picture \ref[img-miniSAS-cable] as standard pinheader connector.
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At the end, MiniSAS connector was chosen as the best option to be used in connecting together multiple ADC modules. A transition between SATA and miniSAS is achieved by SAS to SATA adapter cable which is commonly used in servers to connect SAS controller to multiple SATA hard disc in RAID systems and thus is commercially easily available. It is compatible with existing SATA cabling systems and aggregates multiple SATA cables to a single connector. It also has SPI configuration lines which can be seen in the following picture \ref[img-miniSAS-cable] as standard pinheader connector.
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The main drawback of miniSAS PCB connectors lies in the fact, that they are manufactured in SMT versions only, SMT design may eventually decrease the durability of the connector even if outer metal housing of connector is designed to be mounted using a standard through-hole mounting method.
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The main drawback of miniSAS PCB connectors lies in the fact, that they are manufactured in SMT versions only. SMT design may eventually decrease the durability of the connector even if outer metal housing of connector is designed to be mounted using a standard through-hole mounting method.
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\midinsert
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\midinsert
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\clabel[img-miniSAS-cable]{Used miniSAS cable}
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\clabel[img-miniSAS-cable]{Used miniSAS cable}
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\picw=5cm \cinspic ./img/miniSAS_SATA_cable.jpg
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\picw=5cm \cinspic ./img/miniSAS_SATA_cable.jpg
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\caption/f An example of miniSAS cable similar to used.
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\caption/f An example of miniSAS cable similar to used.
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\endinsert
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\endinsert
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\secc Signal integrity requirements
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\secc Signal integrity requirements
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\label[diff-signaling]
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\label[diff-signaling]
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We use ADC devices that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. This imply $ 1/4 \cdot 10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate $t_s$ will be 4.95 m. Although we do not have any cables in system with comparable lengths, worst data bit skew described by data sheets of used components is $0.3 \cdot t_s$, which is 1.485 m. Therefore length matching is not critical in our current design operated on lowest sampling speed. Length matching becomes critical in future version with higher sampling rates, then cable length must be matched. However SATA cabling technology is prepared for that case and matched SATA cables are standard merchandise.
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We use ADC devices that have DATA clock frequency eight times higher than sampling frequency in a single line output mode, implying a 40 MHz output bit rate. This implies a $ 1/4 \cdot 10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate $t_s$ will be 4.95 m. Although we do not have any cables in the system with comparable lengths, the worst data bit skew described by data sheets of the used components is $0.3 \cdot t_s$, which is 1.485 m. Therefore the length matching is not critical in our current design operating on lowest sampling speed. Length matching may become critical in future versions with higher sampling rates, where the cable length must be matched. However SATA cabling technology is already prepared for that case and matched SATA cables are a standard merchandise.
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\secc ADC modules design
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\secc ADC modules design
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\midinsert
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\midinsert
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\clabel[adcdual-preview]{Preview of designed ADCdual PCB}
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\clabel[adcdual-preview]{Preview of designed ADCdual PCB}
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\picw=10cm \cinspic ./img/ADCdual01A_Top_Big.JPG
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\picw=10cm \cinspic ./img/ADCdual01A_Top_Big.JPG
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\picw=10cm \cinspic ./img/ADCdual01A_Bottom_Big.JPG
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\picw=10cm \cinspic ./img/ADCdual01A_Bottom_Big.JPG
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\caption/f Realised PCB of ADCdual01A modules. Differential pairs routing are clearly visible.
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\caption/f Realised PCB of ADCdual01A modules. Differential pairs routings are clearly visible.
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\endinsert
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\endinsert
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\secc ADC selection
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\secc ADC selection
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There exist several standard ADC signaling formats currently used in communication with FPGA.
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There exist several standard ADC signalling formats currently used in communication with FPGA.
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\begitems
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\begitems
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  * DDR LVDS
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  * DDR LVDS
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  * JEDEC 204B
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  * JEDEC 204B
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  * JESD204A
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  * JESD204A
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  * Paralel LVDS
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  * Paralel LVDS
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  * Serdes
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  * Serdes
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  * serial LVDS
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  * serial LVDS
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\enditems
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\enditems
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Because we need to use the smallest number of cables, the choice fell on the serial LVDS format. Small number of differential pairs is an important parameter determining the construction complexity and reliability\cite[serial-lvds]. No much many currently existing ADC devices have this kind of digital interface. An ultrasound AFE device chips seems to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though - it is incapable of handling differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC) and has many single ended ADC channels. Consequently scaling is possible only by a factor of 4 receivers (making 8 analogue single ended channels).
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As a result of our need to use the smallest number of cables possible, the choice fell on the serial LVDS format. Small number of differential pairs is an important parameter determining the construction complexity and reliability\cite[serial-lvds]. No many currently existing ADC devices have this kind of digital interface. An ultrasound AFE device chips seem to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though - it is incapable of handling differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC) and has many single ended ADC channels. Consequently, the scaling is possible only by a factor of 4 receivers (making 8 analogue single ended channels).
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If we add a requirement of  separate output for every analogue channel and a 16bit depth we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these requirements.  We have summarized those ADCs in the following table \ref[ADC-types]
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If we add a requirement of separate output for every analogue channel and a 16bit depth we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these criteria. We have summarized those ADCs in the following table \ref[ADC-types]
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\midinsert
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\midinsert
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\typosize[9/11] \def\tabiteml{ }\let\tabitemr=\tabiteml
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\typosize[9/11] \def\tabiteml{ }\let\tabitemr=\tabiteml
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\clabel[ADC-types]{Available ADC types}
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\clabel[ADC-types]{Available ADC types}
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\ctable{lccccccc}{
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\ctable{lccccccc}{
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\hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr
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\hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr
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SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8  \cr
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SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8  \cr
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SFDR [dB] & 99 & 90 & 90 & 90 & 90 & 90 & 90  \cr
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SFDR [dB] & 99 & 90 & 90 & 90 & 90 & 90 & 90  \cr
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S/H Bandwidth [MHz] & 200 & \multispan6 550 \strut \cr
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S/H Bandwidth [MHz] & 200 & \multispan6 550 \strut \cr
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Sampling rate [MSPS] & 20 & 25 & 40 & 65 & 80 &  105 & 125  \cr
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Sampling rate [MSPS] & 20 & 25 & 40 & 65 & 80 &  105 & 125  \cr
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Configuration & \multispan7 SPI \strut \cr
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Configuration & \multispan7 SPI \strut \cr
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Package & \multispan7 \hfil 52-Lead (7mm $\times$ 8mm) QFN \hfil \strut \cr
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Package & \multispan7 \hfil 52-Lead (7mm $\times$ 8mm) QFN \hfil \strut \cr
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}
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}
159 
\caption/t The summary of available ADC types and theirs characteristics.
 159 
\caption/t The summary of the currently available ADC types and theirs characteristics.
160 
\endinsert
 160 
\endinsert
161 
 
 161 
 
162 
All parts in this category are compatible with one board layout. Main differences lay in the sampling frequency and signal to noise ratio, with the slowest having a maximum sampling frequency of 20 MHz. However all of them have a minimal sampling frequency of 5 MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..).  We selected two slowest types for our evaluation design. Then PCB for this part have been designed.
 162 
All parts in this category are compatible with one board layout. The main differences lay in the sampling frequency and signal to noise ratio, with the slowest having a maximum sampling frequency of 20 MHz. However, all of them have a minimal sampling frequency of 5 MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..).  We have selected two slowest types for our evaluation design. Following that, a PCB for this part have been designed.
163 
We decided that ADCdual01A modules have a standard MLAB construction layout with four mounting holes in corners aligned in defined raster of 400 mils.
 163 
We have decided that ADCdual01A modules will have a standard MLAB construction layout with four mounting holes in corners aligned in defined raster of 400 mils.
164 
 
 164 
 
165 
Data serial data outputs of ADC modules should be connected directly by LVDS signalling levels conducted by SATA cables to FPGAs for the basic primary signal processing. The ADC chips used in the modules has a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel.  This creates a signal concept enabling a selection of a proper bus bit-width according to the sampling rate (higher bus bit-width downgrades signalling speed and vice versa.)
 165 
Data serial data outputs of ADC modules should be connected directly by LVDS signalling levels conducted by SATA cables to FPGAs for the basic primary signal processing. The ADC chips used in the modules have a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel.  This creates a signal concept enabling a selection of proper bus bit-width according to the sampling rate (higher bus bit-width downgrades signalling speed and vice versa.)
166 
 
 166 
 
167 
In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable should be used as described in section \ref[signal-cables].
 167 
In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable should be used as described in section \ref[signal-cables].
168 
 
 168 
 
169 
A KiCAD design suite had been chosen for PCB layout. However, the version is, despite having integrated CERN Push \& Shove routing capability, slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad,  the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software.
 169 
A KiCAD design suite had been chosen for PCB layout. However, the version, despite having integrated CERN Push \& Shove routing capability, is slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad,  the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software.
170 
 
 170 
 
171 
As a part of work on the thesis, new PCB footprints for FMC, SATA, ADCs a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub.
 171 
As a part of work on the thesis, new PCB footprints for FMC, SATA, ADCs a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub.
172 
 
 172 
 
173 
ADCdual01A module has several digital data output formats. Difference between these modes lays in the number of differential pairs used.
 173 
ADCdual01A module has several digital data output formats. Difference between these modes lays in the number of differential pairs used.
174 
 
 174 
 
175 
\begitems
 175 
\begitems
176 
    * 1-lane mode
 176 
    * 1-lane mode
177 
    * 2-lane mode
 177 
    * 2-lane mode
178 
    * 4-lane mode
 178 
    * 4-lane mode
179 
\enditems
 179 
\enditems
180 
 
 180 
 
181 
All of the above-mentioned modes are supported by the module design. For the discussed data acquisition system, the 1-lane mode was selected. 1-lane mode allows a minimal number of differential pairs between ADCdual01A and FPGA. Digital signalling scheme used in 1-lane mode is shown in the following image \ref[1-line-out].
 181 
All of the above-mentioned modes are supported by the module design. For the discussed data acquisition system, the 1-lane mode was selected. 1-lane mode allows a minimal number of differential pairs between ADCdual01A and FPGA. Digital signalling scheme used in 1-lane mode is shown in the following image \ref[1-line-out].
182 
 
 182 
 
183 
\midinsert
 183 
\midinsert
184 
\clabel[1-line-out]{Single line ADC output signals}
 184 
\clabel[1-line-out]{Single line ADC output signals}
185 
\picw=15cm \cinspic ./img/ADC_single_line_output.png
 185 
\picw=15cm \cinspic ./img/ADC_single_line_output.png
186 
\caption/f Digital signalling schema for 1-line ADC digital output mode.
 186 
\caption/f Digital signalling schema for 1-line ADC digital output mode.
187 
\endinsert
 187 
\endinsert
188 
 
 188 
 
189 
ADCdual01A parameters can be set either by jumper setup (referred to as a parallel programming  in the device's data sheet) or by SPI interface. SPI interface has been selected for our system, because of the parallel programming lack of options (test pattern output setup for example).
 189 
ADCdual01A parameters can be set either by jumper setup (referred to as a parallel programming  in the device's data sheet) or by SPI interface. SPI interface has been chosen for our system, because of the parallel programming's lack of options (test pattern output setup for example).
190 
 
 190 
 
191 
Complete schematic diagram of ADCdual01A module board is included in the appendix.
 191 
Complete schematic diagram of ADCdual01A module board is included in the appendix.
192 
 
 192 
 
193 
 
 193 
 
194 
\secc ADC modules interface
 194 
\secc ADC modules interface
195 
 
 195 
 
196 
\midinsert
 196 
\midinsert
197 
\picw=10cm \cinspic ./img/FMC2DIFF_Top_Big.JPG
 197 
\picw=10cm \cinspic ./img/FMC2DIFF_Top_Big.JPG
198 
\picw=10cm \cinspic ./img/FMC2DIFF_Bottom_Big.JPG
 198 
\picw=10cm \cinspic ./img/FMC2DIFF_Bottom_Big.JPG
199 
\caption/f Realised PCB of FMC2DIFF01A module.
 199 
\caption/f Realised PCB of FMC2DIFF01A module.
200 
\endinsert
 200 
\endinsert
201 
 
 201 
 
202 
Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter expects the presence of FMC LPC connector on host side and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions].
 202 
Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter expects the presence of FMC LPC connector on host side and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions].
203 
This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the appendix.
 203 
This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the appendix.
204 
 
 204 
 
205 
The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case with ML605 development board. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques).
 205 
The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case with ML605 development board. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques).
206 
Differential signaling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
 206 
Differential signalling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
207 
 
 207 
 
208 
LVPECL level signal connectors on FMC2DIFF01A board are dedicated for clock signals. We selected  the SY55855V and SY55857L dual translators. Dual configuration in useful due to fact that SATA cable contains two differential pairs.
 208 
LVPECL level signal connectors on FMC2DIFF01A board are dedicated to transmit the clock signals. We have selected  the SY55855V and SY55857L dual translators. Dual configuration in useful due to fact, that SATA cable contains two differential pairs.
209 
 
 209 
 
210 
The SY55855V is a fully differential, CML/PECL/LVPECL-to-LVDS translator. It achieves LVDS signaling up to 1.5Gbps, depending on the distance and the characteristics of the media and noise coupling sources.
 210 
The SY55855V is a fully differential, CML/PECL/LVPECL-to-LVDS translator. It achieves LVDS signalling up to 1.5Gbps, depending on the distance and the characteristics of the media and noise coupling sources.
211 
LVDS is intended to drive 50 $\Omega$ impedance transmission
 - 
 
212 
line media such as PCB traces, backplanes, or cables. SY55855V inputs can be terminated with a single resistor between the true and the complement pins of a given input \cite[SY55855V-chip].
 211 
LVDS is intended to drive 50 $\Omega$ impedance transmission line media such as PCB traces, backplanes, or cables. SY55855V inputs can be terminated with a single resistor between the true and the complement pins of a given input \cite[SY55855V-chip].
213 
 
 212 
 
214 
The SY55857L is a fully differential, high-speed dual translator optimized to accept any logic standard from single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is guaranteed for speeds up to 2.5Gbps (2.5GHz toggle frequency). The SY55857L does not internally terminate its inputs, as different interfacing standards have different termination requirements\cite[SY55857L-chip].
 213 
The SY55857L is a fully differential, high-speed dual translator optimized to accept any logic standard from single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is guaranteed for speeds up to 2.5Gbps (2.5GHz toggle frequency). The SY55857L does not internally terminate its inputs, as different interfacing standards have different termination requirements\cite[SY55857L-chip].
215 
 
 214 
 
216 
Inputs of both used chips are terminated accordingly to used logic. The LVDS input is terminated differentially by 100 $\Omega$ resistor between positive and negative inputs. PECL input is terminated by Thevenin resistor network. Thevenin termination method was selected as optimal due to absence of proper power voltage (1,3 V) for direct termination by 50 $\Omega$ resistors. Termination on FPGA side is realized directly by settings proper digital logic type on input pins.
 215 
Inputs of both used chips are terminated accordingly to used logic. The LVDS input is terminated differentially by 100 $\Omega$ resistor between positive and negative inputs. PECL input is terminated by Thevenin resistor network. Thevenin termination method was selected as optimal one, due to the absence of a proper power voltage (1,3 V) for direct termination by 50 $\Omega$ resistors. Termination on FPGA side is realized directly by settings the proper digital logic type on input pins.
217 
 
 216 
 
218 
\midinsert
 217 
\midinsert
219 
\clabel[ML605-development-board]{ML605 development board}
 218 
\clabel[ML605-development-board]{ML605 development board}
220 
\picw=10cm \cinspic ./img/ML605-board.jpg
 219 
\picw=10cm \cinspic ./img/ML605-board.jpg
221 
\caption/f FPGA ML605 development board.
 220 
\caption/f FPGA ML605 development board.
222 
\endinsert
 221 
\endinsert
223 
 
 222 
 
224 
\midinsert
 223 
\midinsert
225 
\clabel[VITA57-regions]{VITA57 board geometry}
 224 
\clabel[VITA57-regions]{VITA57 board geometry}
226 
\picw=10cm \cinspic ./img/VITA57_regions.png
 225 
\picw=10cm \cinspic ./img/VITA57_regions.png
227 
\caption/f Definition of VITA57 regions.
 226 
\caption/f Definition of VITA57 regions.
228 
\endinsert
 227 
\endinsert
229 
 
 228 
 
230 
% doplnit presny pocet konektoru
 229 
% doplnit presny pocet konektoru
231 
 
 230 
 
232 
Several SATA connectors and two miniSAS connectors are populated on this board.  This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter.
 231 
Several SATA connectors and two miniSAS connectors are populated on this board.  This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter.
233 
 
 232 
 
234 
Lengths of differential pairs routed on PCB of the module are not matched between the pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless, signals within differential pairs themselves are matched for length. Internal signal trace length matching of differential pairs is mandatory in order to minimize jitter and avoid a dynamic logic hazard conditions on digital signals in worst case. Thus clocks signals are routed in the most precise way on all designed boards.
 233 
Lengths of differential pairs routed on PCB of the module are not matched between the pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless, signals within differential pairs themselves are matched for length. Internal signal trace length matching of differential pairs is mandatory in order to minimize jitter and avoid a dynamic logic hazard conditions on digital signals in worst case. Thus clocks signals are routed in the most precise way on all designed boards.
235 
 
 234 
 
236 
Signal configuration used in our trial design is described in the following tables \ref[minisas-interface], \ref[SPI-system] and \ref[clock-interconnections].
 235 
Signal configuration used in our trial design is described in the following tables \ref[minisas-interface], \ref[SPI-system] and \ref[clock-interconnections].
237 
 
 236 
 
238 
 
 237 
 
239 
\midinsert \clabel[minisas-interface]{miniSAS differential pairs connections}
 238 
\midinsert \clabel[minisas-interface]{miniSAS differential pairs connections}
240 
\ctable {cccc}
 239 
\ctable {cccc}
241 
{
 240 
{
242 
miniSAS	&	SATA pair	&	FMC signal	&	Used as	\cr
 241 
miniSAS	&	SATA pair	&	FMC signal	&	Used as	\cr
243 
P0	&	1	&	LA03	&	 not used 	\cr
 242 
P0	&	1	&	LA03	&	 not used 	\cr
244 
P0	&	2	&	LA04	&	 not used 	\cr
 243 
P0	&	2	&	LA04	&	 not used 	\cr
245 
P1	&	1	&	LA08	&	 not used 	\cr
 244 
P1	&	1	&	LA08	&	 not used 	\cr
246 
P1	&	2	&	LA07	&	 not used 	\cr
 245 
P1	&	2	&	LA07	&	 not used 	\cr
247 
P2	&	1	&	LA16	&	ADC1  CH1 (LTC2190)	\cr
 246 
P2	&	1	&	LA16	&	ADC1  CH1 (LTC2190)	\cr
248 
P2	&	2	&	LA11	&	ADC1  CH2 (LTC2190) 	\cr
 247 
P2	&	2	&	LA11	&	ADC1  CH2 (LTC2190) 	\cr
249 
P3	&	1	&	LA17	&	ADC2 CH1 (LTC2271)	\cr
 248 
P3	&	1	&	LA17	&	ADC2 CH1 (LTC2271)	\cr
250 
P3	&	2	&	LA15	&	ADC2 CH2 (LTC2271)	\cr
 249 
P3	&	2	&	LA15	&	ADC2 CH2 (LTC2271)	\cr
251 
}
 250 
}
252 
\caption/t miniSAS (FMC2DIFF01A J7) signal connections between modules.
 251 
\caption/t miniSAS (FMC2DIFF01A J7) signal connections between modules.
253 
\endinsert
 252 
\endinsert
254 
 
 253 
 
255 
 
 254 
 
256 
\midinsert \clabel[SPI-system]{SPI configuration interface connections}
 255 
\midinsert \clabel[SPI-system]{SPI configuration interface connections}
257 
\ctable {ccc}
 256 
\ctable {ccc}
258 
{
 257 
{
259 
SPI connection J7	&	FMC signal	&	Connected to	\cr
 258 
SPI connection J7	&	FMC signal	&	Connected to	\cr
260 
SAS-AUX1	 &	LA14\_N	&	SPI DOUT	\cr
 259 
SAS-AUX1	 &	LA14\_N	&	SPI DOUT	\cr
261 
SAS-AUX2	 &	LA14\_P	&	SPI CLK	\cr
 260 
SAS-AUX2	 &	LA14\_P	&	SPI CLK	\cr
262 
SAS-AUX3	 &	LA12\_N	&	CE ADC1	\cr
 261 
SAS-AUX3	 &	LA12\_N	&	CE ADC1	\cr
263 
SAS-AUX4	 &	LA12\_P	&	CE ADC2	\cr
 262 
SAS-AUX4	 &	LA12\_P	&	CE ADC2	\cr
264 
SAS-AUX5	 &	LA13\_N	&	soldered to GND	\cr
 263 
SAS-AUX5	 &	LA13\_N	&	soldered to GND	\cr
265 
SAS-AUX6	 &	LA13\_P	&	not used	\cr
 264 
SAS-AUX6	 &	LA13\_P	&	not used	\cr
266 
SAS-AUX7	 &	LA09\_N	&	not used	\cr
 265 
SAS-AUX7	 &	LA09\_N	&	not used	\cr
267 
SAS-AUX8	 &	LA09\_P	&	soldered to GND	\cr
 266 
SAS-AUX8	 &	LA09\_P	&	soldered to GND	\cr
268 
}
 267 
}
269 
\caption/t SPI system interconnections
 268 
\caption/t SPI system interconnections
270 
\endinsert
 269 
\endinsert
271 
 
 270 
 
272 
SPI interface is used in an unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back is not possible, thus the configuration written to registers in ADC module cannot be validated. We have not observed any problems with this system, but it may be a possible source of failures.
 271 
SPI interface is used in an unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back is not possible, thus the configuration written to registers in ADC module cannot be validated. We have not observed any problems with this system, but it may be a possible source of failures.
273 
 
 272 
 
274 
 
 273 
 
275 
\midinsert \clabel[clock-interconnections]{System clock interconnections}
 274 
\midinsert \clabel[clock-interconnections]{System clock interconnections}
276 
\ctable {lccc}
 275 
\ctable {lccc}
277 
{
 276 
{
278 
Signal	&	FMC signal	&	FMC2DIFF01A	&	ADCdual01A	\cr
 277 
Signal	&	FMC signal	&	FMC2DIFF01A	&	ADCdual01A	\cr
279 
DCO	&	CLK1\_M2C	&	J5-1	&	J13-1	\cr
 278 
DCO	&	CLK1\_M2C	&	J5-1	&	J13-1	\cr
280 
FR	&	LA18\_CC	&	J10-1	&	J12-1	\cr
 279 
FR	&	LA18\_CC	&	J10-1	&	J12-1	\cr
281 
ENC	&	LA01\_CC	&	J2-1(PECL OUT)	&	J3-1	\cr
 280 
ENC	&	LA01\_CC	&	J2-1(PECL OUT)	&	J3-1	\cr
282 
SDGPSDO01A LO	&	CLK0\_M2C	&	J3-1 (PECL IN)	&	N/A	\cr
 281 
SDGPSDO01A LO	&	CLK0\_M2C	&	J3-1 (PECL IN)	&	N/A	\cr
283 
}
 282 
}
284 
\caption/t Clock system interconnections
 283 
\caption/t Clock system interconnections
285 
\endinsert
 284 
\endinsert
286 
 
 285 
 
287 
\secc FPGA function
 286 
\secc FPGA function
288 
 
 287 
 
289 
Several tasks in separate FPGA blocks are performed by FPGA. In first block FPGA prepares sampling clock for ADCdual01A modules by division of main local oscillator. This task is separate block in FPGA and runs asynchronously to other logical circuits. Second block is SPI configuration module, which sends configuration words to ADC modules it is activated by opening of Xillybus interface file. Third block represents the main module, which resolves ADC - PC communication itself it communicates via PCIe, collect data from ADC hardware and creates data packet \ref[xillybus-interface]. Last block is activated after ADC configuration via SPI.
 288 
Several tasks in separate FPGA blocks are performed by FPGA. In first block FPGA prepares sampling clock for ADCdual01A modules by division of main local oscillator. This task is separate block in FPGA and runs asynchronously to other logical circuits. Second block is SPI configuration module, which sends configuration words to ADC modules it is activated by opening of Xillybus interface file. Third block represents the main module, which resolves ADC - PC communication itself it communicates via PCIe, collect data from ADC hardware and creates data packet \ref[xillybus-interface]. Last block is activated after ADC configuration via SPI.
290 
 
 289 
 
291 
Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in system device file named  "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are described in the table below \ref[xillybus-interface].
 290 
Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in system device file named  "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are described in the table below \ref[xillybus-interface].
292 
 
 291 
 
293 
\midinsert
 292 
\midinsert
294 
\def\tabiteml{ }\let\tabitemr=\tabiteml
 293 
\def\tabiteml{ }\let\tabitemr=\tabiteml
295 
\clabel[xillybus-interface]{Grabber binary output format}
 294 
\clabel[xillybus-interface]{Grabber binary output format}
296 
\ctable {lccccccccc}{
 295 
\ctable {lccccccccc}{
297 
\hfil & \multispan9 \hfil 160bit packet \hfil \strut \crl \tskip4pt
 296 
\hfil & \multispan9 \hfil 160bit packet \hfil \strut \crl \tskip4pt
298 
Data name &  FRAME  & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2  \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil \strut  \cr
 297 
Data name &  FRAME  & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2  \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil \strut  \cr
299 
Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr
 298 
Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr
300 
Content & saw signal & $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ \cr
 299 
Content & saw signal & $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ \cr
301 
}
 300 
}
302 
\caption/t System device "/dev/xillybus_data2_r" data format
 301 
\caption/t System device "/dev/xillybus_data2_r" data format
303 
\endinsert
 302 
\endinsert
304 
 
 303 
 
305 
Data packet block which is carried on PCI Express is described by table \ref[xillybus-interface]. The data packet consist several 32bit words. First word contain FRAME number and it is filled by saw signal for now, with increment step of every data packet transmission. Following data words contains samples from ADCs for first and second channel. Samples from every channel is transmitted in pairs of two samples. Number of ADC channels is expandable according to number of physically connected channels. An CRC word may be added in future at end of transmission packet for data integrity validation.
 304 
Data packet block which is carried on PCI Express is described by table \ref[xillybus-interface]. The data packet consist several 32bit words. First word contain FRAME number and it is filled by saw signal for now, with increment step of every data packet transmission. Following data words contains samples from ADCs for first and second channel. Samples from every channel is transmitted in pairs of two samples. Number of ADC channels is expandable according to number of physically connected channels. An CRC word may be added in future at end of transmission packet for data integrity validation.
306 
 
 305 
 
307 
FRAME word at beginning of data packet now filled with incrementing and overflowing saw signal is used for ensure that no data samples ale lost during data transfers from FPGA. FRAME signal may be used in future for pairing the ADC samples data packet with another data packet in future. This new additional data packet should carry meta-data information about sample time jitter, current accuracy of local oscillator frequency etc.
 306 
FRAME word at beginning of data packet now filled with incrementing and overflowing saw signal is used for ensure that no data samples ale lost during data transfers from FPGA. FRAME signal may be used in future for pairing the ADC samples data packet with another data packet in future. This new additional data packet should carry meta-data information about sample time jitter, current accuracy of local oscillator frequency etc.
308 
 
 307 
 
309 
Detailed description of currently implemented FPGA functions can be found in separate paper \cite[fpga-middleware]. HDL source codes for FPGA at state which was used are included on enclosed CD. Future development versions are publicly available from MLAB sources repository.
 308 
Detailed description of currently implemented FPGA functions can be found in separate paper \cite[fpga-middleware]. HDL source codes for FPGA at state which was used are included on enclosed CD. Future development versions are publicly available from MLAB sources repository.
310 
 
 309 
 
311 
% doplnit odkaz na mlab repozitar
 310 
% doplnit odkaz na mlab repozitar
312 
 
 311 
 
313 
\secc Data reading and recording
 312 
\secc Data reading and recording
314 
 
 313 
 
315 
In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view waterfall plots the data streams output from ADC modules.
 314 
In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view waterfall plots the data streams output from ADC modules.
316 
 
 315 
 
317 
\midinsert
 316 
\midinsert
318 
\clabel[grabber-flow-graph]{Gnuradio flow graph for signal grabbing}
 317 
\clabel[grabber-flow-graph]{Gnuradio flow graph for signal grabbing}
319 
\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/screenshots/Grabber.grc.png }
 318 
\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/screenshots/Grabber.grc.png }
320 
\par\nobreak \vskip\wd0 \vskip-\ht0
 319 
\par\nobreak \vskip\wd0 \vskip-\ht0
321 
\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}
 320 
\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}
322 
\caption/f The ADC recorder flow graph created in gnuradio-companion.
 321 
\caption/f The ADC recorder flow graph created in gnuradio-companion.
323 
\endinsert
 322 
\endinsert
324 
 
 323 
 
325 
\midinsert
 324 
\midinsert
326 
\picw=15cm \cinspic ./img/screenshots/Grabber_running.png
 325 
\picw=15cm \cinspic ./img/screenshots/Grabber_running.png
327 
\caption/f User interface window of a running ADC grabber.
 326 
\caption/f User interface window of a running ADC grabber.
328 
\endinsert
 327 
\endinsert
329 
 
 328 
 
330 
The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. Signal is grabbed to file with exactly the same format, as it is described in table \ref[xillybus-interface].
 329 
The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. Signal is grabbed to file with exactly the same format, as it is described in table \ref[xillybus-interface].
331 
 
 330 
 
332 
 
 331 
 
333 
\chap Achieved parameters
 332 
\chap Achieved parameters
334 
 
 333 
 
335 
Trial design construction was tested for proper handling of sampling rates in range of 5 MSPS to 15 MSPS it should work above this limit. System works on i7 8 cores computer with Ubuntu 12.04 LTS operating system.  Data recording of input signal is impossible above sampling rates around 7 MSPS due to bottleneck at HDD speed limits, it should be resolved by use of SSD disk drive. But it is not tested in our setup.
 334 
Trial design construction was tested for proper handling of sampling rates in range of 5 MSPS to 15 MSPS it should work above this limit. System works on i7 8 cores computer with Ubuntu 12.04 LTS operating system.  Data recording of input signal is impossible above sampling rates around 7 MSPS due to bottleneck at HDD speed limits, it should be resolved by use of SSD disk drive. But it is not tested in our setup.
336 
 
 335 
 
337 
\sec Measured parameters
 336 
\sec Measured parameters
338 
 
 337 
 
339 
Two prototypes of ADC modules were assembled and tested. The first prototype, labeled ADC1, has LTC2190 ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which give it an ability of an internal attenuation of the input signal. The value of this attenuation $A$ is described by the following formula \ref[ADC1-gain]
 338 
Two prototypes of ADC modules were assembled and tested. The first prototype, labeled ADC1, has LTC2190 ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which give it an ability of an internal attenuation of the input signal. The value of this attenuation $A$ is described by the following formula \ref[ADC1-gain]
340 
 
 339 
 
341 
\label[ADC1-gain]
 340 
\label[ADC1-gain]
342 
$$
 341 
$$
343 
A = {806 \cdot R_1 \over R_1 + R_2} \eqmark
 342 
A = {806 \cdot R_1 \over R_1 + R_2} \eqmark
344 
$$
 343 
$$
345 
 
 344 
 
346 
Where the letters stand for:
 345 
Where the letters stand for:
347 
\begitems
 346 
\begitems
348 
  * $A$ -  Gain of an input amplifier.
 347 
  * $A$ -  Gain of an input amplifier.
349 
  * $R_1$ - Output impedance of signal source (usually 50 Ohm).
 348 
  * $R_1$ - Output impedance of signal source (usually 50 Ohm).
350 
  * $R_2$ - Value of serial resistors at operational amplifier inputs.
 349 
  * $R_2$ - Value of serial resistors at operational amplifier inputs.
351 
\enditems
 350 
\enditems
352 
 
 351 
 
353 
We have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply that $A = 0.815$. That value of A is further confirmed by the measurement.
 352 
We have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply that $A = 0.815$. That value of A is further confirmed by the measurement.
354 
In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator. Circuit diagram of used transformer circuit is shown in picture \ref[balun-circuit]  and circuit realization in photograph \ref[SMA2SATA-nest].
 353 
In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator. Circuit diagram of used transformer circuit is shown in picture \ref[balun-circuit]  and circuit realization in photograph \ref[SMA2SATA-nest].
355 
 
 354 
 
356 
\midinsert
 355 
\midinsert
357 
\clabel[balun-circuit]{Balun transformer circuit}
 356 
\clabel[balun-circuit]{Balun transformer circuit}
358 
\picw=10cm \cinspic ./img/SMA2SATA.pdf
 357 
\picw=10cm \cinspic ./img/SMA2SATA.pdf
359 
\caption/f Simplified balun transformer circuit diagram.
 358 
\caption/f Simplified balun transformer circuit diagram.
360 
\endinsert
 359 
\endinsert
361 
 
 360 
 
362 
The signal generator Agilent 33220A which we used does not have optimal parameters for this type of dynamic range measurement. Signal distortion and spurious levels are only -70 dBc according to Agilent datasheet \cite[33220A-generator]. We have managed to measure an ADC saturation voltage of 705.7 mV (generator output) with this setup, mostly due to an impedance mismatch and uncalibrated measurement setup, with 1V ADC range selected by sense pin. This is a relatively large error, but the main result of our measurement, seen as a FFT plot shown in image \ref[ADC1-FFT], confirms $>$80 dB dynamic range at ADC module input.
 361 
The signal generator Agilent 33220A which we used does not have optimal parameters for this type of dynamic range measurement. Signal distortion and spurious levels are only -70 dBc according to Agilent datasheet \cite[33220A-generator]. We have managed to measure an ADC saturation voltage of 705.7 mV (generator output) with this setup, mostly due to an impedance mismatch and uncalibrated measurement setup, with 1V ADC range selected by sense pin. This is a relatively large error, but the main result of our measurement, seen as a FFT plot shown in image \ref[ADC1-FFT], confirms $>$80 dB dynamic range at ADC module input.
363 
 
 362 
 
364 
\midinsert
 363 
\midinsert
365 
\clabel[ADC1-FFT]{ADC1 sine test FFT}
 364 
\clabel[ADC1-FFT]{ADC1 sine test FFT}
366 
\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
 365 
\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
367 
\caption/f Sine signal sampled by ADC1 module with LTC2190 and LT6600-5 devices.
 366 
\caption/f Sine signal sampled by ADC1 module with LTC2190 and LT6600-5 devices.
368 
\endinsert
 367 
\endinsert
369 
 
 368 
 
370 
 
 369 
 
371 
Similar test was performed at ADC2 module. For ADC2 we have to use formula with a different constant \ref[ADC1-gain]. The ADC2 module has LT6600-2.5 amplifiers populated on it with gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances  of used setup.
 370 
Similar test was performed at ADC2 module. For ADC2 we have to use formula with a different constant \ref[ADC1-gain]. The ADC2 module has LT6600-2.5 amplifiers populated on it with gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances  of used setup.
372 
 
 371 
 
373 
\label[ADC2-gain]
 372 
\label[ADC2-gain]
374 
$$
 373 
$$
375 
A = {1580 \cdot R_1 \over R_1 + R_2} \eqmark
 374 
A = {1580 \cdot R_1 \over R_1 + R_2} \eqmark
376 
$$
 375 
$$
377 
 
 376 
 
378 
Where the letters stand for:
 377 
Where the letters stand for:
379 
\begitems
 378 
\begitems
380 
  * $A$ -  Gain of an input amplifier.
 379 
  * $A$ -  Gain of an input amplifier.
381 
  * $R_1$ - Output impedance of signal source (usually 50 Ohm).
 380 
  * $R_1$ - Output impedance of signal source (usually 50 Ohm).
382 
  * $R_2$ - Value of serial resistors at operational amplifier inputs.
 381 
  * $R_2$ - Value of serial resistors at operational amplifier inputs.
383 
\enditems
 382 
\enditems
384 
 
 383 
 
385 
\midinsert
 384 
\midinsert
386 
\clabel[ADC2-FFT]{ADC2 sine test FFT}
 385 
\clabel[ADC2-FFT]{ADC2 sine test FFT}
387 
\picw=15cm \cinspic ./img/screenshots/ADC2_CH1_FFT.png
 386 
\picw=15cm \cinspic ./img/screenshots/ADC2_CH1_FFT.png
388 
\caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices.
 387 
\caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices.
389 
\endinsert
 388 
\endinsert
390 
 
 389 
 
391 
Computed FFT spectra for measured signal are shown in the images \ref[ADC2-FFT] and \ref[ADC1-FFT].  Both images confirm that ADCdual01A modules have input dynamical range of 80 dB at least.
 390 
Computed FFT spectra for measured signal are shown in the images \ref[ADC2-FFT] and \ref[ADC1-FFT].  Both images confirm that ADCdual01A modules have input dynamical range of 80 dB at least.
392 
 
 391 
 
393 
\midinsert
 392 
\midinsert
394 
\clabel[SMA2SATA-nest]{Used balun transformer}
 393 
\clabel[SMA2SATA-nest]{Used balun transformer}
395 
\picw=15cm \cinspic ./img/SMA2SATA_nest1.JPG
 394 
\picw=15cm \cinspic ./img/SMA2SATA_nest1.JPG
396 
\caption/f Balun transformer circuit used for ADC parameters measurement. It is constructed from H1012 transformer salvaged from an old Ethernet card.
 395 
\caption/f Balun transformer circuit used for ADC parameters measurement. It is constructed from H1012 transformer salvaged from an old Ethernet card.
397 
\endinsert
 396 
\endinsert
398 
 
 397 
 
399 
 
 398 
 
400 
 
 399 
 
401 
\sec Example of usage
 400 
\sec Example of usage
402 
 
 401 
 
403 
For additional validation of system characteristics a receiver setup has been constructed.
 402 
For additional validation of system characteristics a receiver setup has been constructed.
404 
 
 403 
 
405 
\secc Basic interferometric station
 404 
\secc Basic interferometric station
406 
 
 405 
 
407 
Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N,  14$^\circ$ 25' 4.170'' E.
 406 
Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N,  14$^\circ$ 25' 4.170'' E.
408 
Antennae were equipped  by LNA01A amplifiers. All coaxial cables have the same length of 5 meters. Antennae were isolated by common mode ferrite bead mounted on cable to minimise the signal coupling between antennas. Evaluation system consists of SDGPSDO local oscillator subsystem used to tune the local oscillator frequency.
 407 
Antennae were equipped  by LNA01A amplifiers. All coaxial cables have the same length of 5 meters. Antennae were isolated by common mode ferrite bead mounted on cable to minimise the signal coupling between antennas. Evaluation system consists of SDGPSDO local oscillator subsystem used to tune the local oscillator frequency.
409 
 
 408 
 
410 
\midinsert
 409 
\midinsert
411 
\clabel[block-schematic]{Receiver block schematic}
 410 
\clabel[block-schematic]{Receiver block schematic}
412 
\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Basic_interferometer.png }
 411 
\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Basic_interferometer.png }
413 
\par\nobreak \vskip\wd0 \vskip-\ht0
 412 
\par\nobreak \vskip\wd0 \vskip-\ht0
414 
\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}
 413 
\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}
415 
\caption/f Complete receiver block schematic of dual antenna interferometric station.
 414 
\caption/f Complete receiver block schematic of dual antenna interferometric station.
416 
\endinsert
 415 
\endinsert
417 
 
 416 
 
418 
% doplnit schema skutecne pouziteho systemu
 417 
% doplnit schema skutecne pouziteho systemu
419 
 
 418 
 
420 
Despite of the schematic diagram proposed at beginning of system description....
 419 
Despite of the schematic diagram proposed at beginning of system description....
421 
We used two separate oscillators -- one oscillator drives encode signal to ADCs still through FPGA based divider and other one drives SDRX01B mixer.
 420 
We used two separate oscillators -- one oscillator drives encode signal to ADCs still through FPGA based divider and other one drives SDRX01B mixer.
422 
The reason for this modification is a simplification of frequency tuning during the experiment. It is because a single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA schema. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA scheme is changed.  Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver.
 421 
The reason for this modification is a simplification of frequency tuning during the experiment. It is because a single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA schema. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA scheme is changed.  Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver.
423 
We use ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators.
 422 
We use ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators.
424 
 
 423 
 
425 
\midinsert
 424 
\midinsert
426 
\clabel[meteor-reflection]{Meteor reflection}
 425 
\clabel[meteor-reflection]{Meteor reflection}
427 
\picw=10cm \cinspic ./img/screenshots/observed_meteor.png
 426 
\picw=10cm \cinspic ./img/screenshots/observed_meteor.png
428 
\caption/f Meteor reflection received by evaluation setup.
 427 
\caption/f Meteor reflection received by evaluation setup.
429 
\endinsert
 428 
\endinsert
430 
 
 429 
 
431 
\midinsert
 430 
\midinsert
432 
\clabel[phase-difference]{Phase difference}
 431 
\clabel[phase-difference]{Phase difference}
433 
\picw=10cm \cinspic ./img/screenshots/phase_difference.png
 432 
\picw=10cm \cinspic ./img/screenshots/phase_difference.png
434 
\caption/f Demonstration of phase difference between antennae.
 433 
\caption/f Demonstration of phase difference between antennae.
435 
\endinsert
 434 
\endinsert
436 
 
 435 
 
437 
For the simplest demonstration of phase difference between antennae, we have analysed part of the signal by complex conjugate multiplication between channels. Results of this analysis can be seen in the following picture \ref[phase-difference]. Points of the selected part of signal create a clear vector, which illustrates the presence of the phase difference.
 436 
For the simplest demonstration of phase difference between antennae, we have analysed part of the signal by complex conjugate multiplication between channels. Results of this analysis can be seen in the following picture \ref[phase-difference]. Points of the selected part of signal create a clear vector, which illustrates the presence of the phase difference.
438 
 
 437 
 
439 
 
 438 
 
440 
\secc Simple passive Doppler radar
 439 
\secc Simple passive Doppler radar
441 
 
 440 
 
442 
% doplnit popis
 441 
% doplnit popis
443 
 
 442 
 
444 
 
 443 
 
445 
\secc Simple polarimeter station
 444 
\secc Simple polarimeter station
446 
 
 445 
 
447 
% doplnit popis
 446 
% doplnit popis
448 
 
 447 
 
449 
\chap Proposition of the final system
 448 
\chap Proposition of the final system
450 
 
 449 
 
451 
The construction of a final system, that is supposed to be employed for real radioastronomy observations will be described in this chapter. It is mainly a theoretical analysis of the data handling systems. Realization of the described ideas might be possible as a part of our future development after we fully evaluate and test the current trial design.
 450 
The construction of a final system, that is supposed to be employed for real radioastronomy observations will be described in this chapter. It is mainly a theoretical analysis of the data handling systems. Realization of the described ideas might be possible as a part of our future development after we fully evaluate and test the current trial design.
452 
 
 451 
 
453 
The system requires proper handling of huge amounts of data and either huge and fast storage capacity is needed for store captured signal data, or enormous computational power is required for online data processing and filtering. Several hardware approach currently exist and are in use for data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially  constructed ASICs are used for this task.
 452 
The system requires proper handling of huge amounts of data and either huge and fast storage capacity is needed for store captured signal data, or enormous computational power is required for online data processing and filtering. Several hardware approach currently exist and are in use for data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially  constructed ASICs are used for this task.
454 
 
 453 
 
455 
\sec Custom design of FPGA board
 454 
\sec Custom design of FPGA board
456 
 
 455 
 
457 
In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than the trial design. It should be compatible with MLAB internal standards  which is further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface.
 456 
In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than the trial design. It should be compatible with MLAB internal standards  which is further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface.
458 
Thunderbolt technology standard was expected to be used in this PC to PCIe module which further communicate with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as specification is only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need preserve standard PC as main computational platform.
 457 
Thunderbolt technology standard was expected to be used in this PC to PCIe module which further communicate with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as specification is only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need preserve standard PC as main computational platform.
459 
 
 458 
 
460 
However, these PCI express external systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing of thesis.
 459 
However, these PCI express external systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing of thesis.
461 
Therefore, a better solution probably needs to be found.
 460 
Therefore, a better solution probably needs to be found.
462 
 
 461 
 
463 
An interface problem will by probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to an increased demand of embedded technologies, which require high computation capacity, low power consumption and small size -- especially smartphones. Many of those ARM based systems have interesting parameters of signal processing. These facts make Intel's ix86 architecture unattractive for future projects.
 462 
An interface problem will by probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to an increased demand of embedded technologies, which require high computation capacity, low power consumption and small size -- especially smartphones. Many of those ARM based systems have interesting parameters of signal processing. These facts make Intel's ix86 architecture unattractive for future projects.
464 
 
 463 
 
465 
\sec Parralella board computer
 464 
\sec Parralella board computer
466 
 
 465 
 
467 
Parallella is a new product created by Adapteva, Inc. \cite[parallella-board]. It represents a small supercomputer, that has been in development for almost two years with only testing series of boards produced until now (first single-board computers with 16-core Epiphany chip were shipped in December 2013) \cite[parallella-board]. The board has nearly ideal parameters for signal processing (as it provides around 50 GFLOPS of computational power). It is is equipped with Epiphany coprocessor which has 16 High Performance RISC CPU Cores,  Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and operating frequency of 866 MHz, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition to this, the board consumes only 3 Watts of power if both Zynq and Epiphany cores are running simultaniously.
 466 
Parallella is a new product created by Adapteva, Inc. \cite[parallella-board]. It represents a small supercomputer, that has been in development for almost two years with only testing series of boards produced until now (first single-board computers with 16-core Epiphany chip were shipped in December 2013) \cite[parallella-board]. The board has nearly ideal parameters for signal processing (as it provides around 50 GFLOPS of computational power). It is is equipped with Epiphany coprocessor which has 16 High Performance RISC CPU Cores,  Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and operating frequency of 866 MHz, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition to this, the board consumes only 3 Watts of power if both Zynq and Epiphany cores are running simultaniously.
468 
 
 467 
 
469 
The main disadvantage of Parralella board is its unknown lead time and an absence of SATA interface or other interface suitable for data storage connection. Fast data storage interface would be useful and would allow bulk processing of captured data. Following that, the results of data processing may be sent over the Ethernet interface to data storage server.
 468 
The main disadvantage of Parralella board is its unknown lead time and an absence of SATA interface or other interface suitable for data storage connection. Fast data storage interface would be useful and would allow bulk processing of captured data. Following that, the results of data processing may be sent over the Ethernet interface to data storage server.
470 
 
 469 
 
471 
\midinsert
 470 
\midinsert
472 
\clabel[img-parallella-board]{Parallella board overview}
 471 
\clabel[img-parallella-board]{Parallella board overview}
473 
\picw=15cm \cinspic ./img/ParallellaTopView31.png
 472 
\picw=15cm \cinspic ./img/ParallellaTopView31.png
474 
\caption/f Top view on Parallella-16 board \cite[parallella16-board].
 473 
\caption/f Top view on Parallella-16 board \cite[parallella16-board].
475 
\endinsert
 474 
\endinsert
476 
 
 475 
 
477 
If Parallella board will be used as a radioastronomy data interface, there would be a demand for new ADC interface module. The interface module will use four PEC connectors mounted on the bottom of the Parallella board. This daughter module should have MLAB compatible design and should preferably be constructed as separable modules for every Parallella's PEC connectors.
 476 
If Parallella board will be used as a radioastronomy data interface, there would be a demand for new ADC interface module. The interface module will use four PEC connectors mounted on the bottom of the Parallella board. This daughter module should have MLAB compatible design and should preferably be constructed as separable modules for every Parallella's PEC connectors.
478 
 
 477 
 
479 
\sec GPU based computational system
 478 
\sec GPU based computational system
480 
 
 479 
 
481 
A new GPU development board NVIDIA K1, shown in the following picture \ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have good parameters for signal processing for a relatively low price of 192 USD.  Unfortunately, they are currently only in pre-order release stage (in April 2014).
 480 
A new GPU development board NVIDIA K1, shown in the following picture \ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have good parameters for signal processing for a relatively low price of 192 USD.  Unfortunately, they are currently only in pre-order release stage (in April 2014).
482 
 
 481 
 
483 
\midinsert
 482 
\midinsert
484 
\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}
 483 
\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}
485 
\picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg
 484 
\picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg
486 
\caption/f The NVIDIA Jetson TK1 Development Kit \cite[nvidia-k1].
 485 
\caption/f The NVIDIA Jetson TK1 Development Kit \cite[nvidia-k1].
487 
\endinsert
 486 
\endinsert
488 
 
 487 
 
489 
NVIDIA board differs from other boards in its category by a presence of PCI Experess connector. If we decide to use this development board in our radio astronomy digitalisation system, the PCI express  should be used for FPGA connection. A new FPGA board with PCI Express  direct PCB connector
 488 
NVIDIA board differs from other boards in its category by a presence of PCI Experess connector. If we decide to use this development board in our radio astronomy digitalisation system, the PCI express  should be used for FPGA connection. A new FPGA board with PCI Express  direct PCB connector
490 
 
 489 
 
491 
% doplnit popis pripojeni FPGA desky s HDMI Kabelem.
 490 
% doplnit popis pripojeni FPGA desky s HDMI Kabelem.
492 
 
 491 
 
493 
\sec Other ARM based computation systems
 492 
\sec Other ARM based computation systems
494 
 
 493 
 
495 
Other embedded ARM based computers, for example ODROID-XU, lack a suitable high speed interface. Their highest speed interface is USB 3.0 which has currently unsettled development support and needs commercial software tools for evaluation and testing.
 494 
Other embedded ARM based computers, for example ODROID-XU, lack a suitable high speed interface. Their highest speed interface is USB 3.0 which has currently unsettled development support and needs commercial software tools for evaluation and testing.
496 
 
 495 
 
497 
 
 496 
 
498 
From the summary analysis mentioned above, the Parrallella board should be a best candidate for computational board in radioastronomy data acquisition system, as it is optimised for high data flow processing. On one hand, Parrallella does not have much memory to cache the processing data but on the other hand it has wide bandwidth data channels instead. Other boards might provide much more computational power -- 300 GFLOPS in case of NVIDIA K1, but they are optimised for heavy computational tasks on limited amount of data which represents a typical problem in computer graphics. However, in our application we do not need such extreme computation power at data acquisition system level.
 497 
From the summary analysis mentioned above, the Parrallella board should be a best candidate for computational board in radioastronomy data acquisition system, as it is optimised for high data flow processing. On one hand, Parrallella does not have much memory to cache the processing data but on the other hand it has wide bandwidth data channels instead. Other boards might provide much more computational power -- 300 GFLOPS in case of NVIDIA K1, but they are optimised for heavy computational tasks on limited amount of data which represents a typical problem in computer graphics. However, in our application we do not need such extreme computation power at data acquisition system level.
499 
As a result we should presumably wait until Parallella becomes widely available. Following that, a new ADCdual interface board should be designed and prepared to be used in new scalable radio astronomy data acquisition system. In the meantime, before suitable computing hardware become accessible, the required applications and algorithms should be optimised using the proposed trial design.  with FPGA development board on standard PC host computer with PCI Express interface to development board.
 498 
As a result we should presumably wait until Parallella becomes widely available. Following that, a new ADCdual interface board should be designed and prepared to be used in new scalable radio astronomy data acquisition system. In the meantime, before suitable computing hardware become accessible, the required applications and algorithms should be optimised using the proposed trial design.  with FPGA development board on standard PC host computer with PCI Express interface to development board.
500 
 
 499