Subversion Repositories svnkaklik

Rev

Rev 1166 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log

Rev 1166 Rev 1167
Line 49... Line 49...
49
 
49
 
50
This design ensures that all system devices have access to the defined phase and the known frequency.
50
This design ensures that all system devices have access to the defined phase and the known frequency.
51
 
51
 
52
\sec System description
52
\sec System description
53
 
53
 
54
This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board], available at the workplace. This FPGA parameters are more than sufficient of what we need for the fast data acquisition system being developed. Expected system configuration is shown in Figure~\ref[expected-block-schematic]. The system consist antennas equipped by
54
This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board], available at the workplace. This FPGA parameters are more than sufficient of what we need for the fast data acquisition system being developed.
55
 
55
 
-
 
56
\secc Receiver overview 
-
 
57
 
56
%% dopsat celkovy popis systemu.
58
Expected system configuration is shown in Figure~\ref[expected-block-schematic]. The system consists of  antennas equipped by preamplifier (LNA) and optionally by band pass filter (BPF). The signal is conducted to down-converting mixers after amplification. Mixers are connected to precise local oscillator (GPSDO01A) controlled from PC by I$^2$C bus. Down-converted signal is digitized by ADCdual01A modules. The ADC modules are connected using FMC2DIFF01A adapter board to data concentrator realized by FPGA board. 
-
 
59
 
-
 
60
In this thesis, the ADC module, adapter board, FPGA specification is proposed. The other modules of the receiver system are currently existing.
57
 
61
 
58
\midinsert
62
\midinsert
59
\clabel[expected-block-schematic]{Expected system block schematic}
63
\clabel[expected-block-schematic]{Expected system block schematic}
60
\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png }
64
\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png }
61
\par\nobreak \vskip\wd0 \vskip-\ht0
65
\par\nobreak \vskip\wd0 \vskip-\ht0