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Signal configuration used in our trial design is described in the following tables.
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Signal configuration used in our trial design is described in the following tables.
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%% zapojeni SPI, FPGA zpatky necte konfiguraci, ale je tam na slepo nahravana.
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%% zapojeni SPI, FPGA zpatky necte konfiguraci, ale je tam na slepo nahravana.
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\midinsert \clabel[minisas-interface]{Grabber binary output format}
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\ctable {cccc}
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{
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miniSAS	&	SATA pair	&	FMC signal	&	Used as	\cr
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P0	&	1	&	LA03	&	 not used 	\cr
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P0	&	2	&	LA04	&	 not used 	\cr
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P1	&	1	&	LA08	&	 not used 	\cr
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P1	&	2	&	LA07	&	 not used 	\cr
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P2	&	1	&	LA16	&	ADC1  CH1 (LTC2190)	\cr
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P2	&	2	&	LA11	&	ADC1  CH2 (LTC2190) 	\cr
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P3	&	1	&	LA17	&	ADC2 CH1 (LTC2271)	\cr
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P3	&	2	&	LA15	&	ADC2 CH2 (LTC2271)	\cr
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}
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\caption/t miniSAS (FMC2DIFF01A J7) signal connections between modules.
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\endinsert
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SPI interface is used by unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back are not possible, thus configuration written to registers in ADC module cannot be validated. We do not observe any problem with this system, but it may be possible source of failures.
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SPI interface is used by unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back are not possible, thus configuration written to registers in ADC module cannot be validated. We do not observe any problem with this system, but it may be possible source of failures.
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\midinsert \clabel[SPI-system]{Grabber binary output format}
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\ctable {ccc}
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{
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SPI connection J7	&	FMC signal	&	Connected to	\cr
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SAS-AUX1	 &	LA14\_N	&	SPI DOUT	\cr
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SAS-AUX2	 &	LA14\_P	&	SPI CLK	\cr
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SAS-AUX3	 &	LA12\_N	&	CE ADC1	\cr
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SAS-AUX4	 &	LA12\_P	&	CE ADC2	\cr
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SAS-AUX5	 &	LA13\_N	&	soldered to GND	\cr
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SAS-AUX6	 &	LA13\_P	&	not used	\cr
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SAS-AUX7	 &	LA09\_N	&	not used	\cr
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SAS-AUX8	 &	LA09\_P	&	soldered to GND	\cr
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}
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\caption/t SPI system interconnections
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\endinsert
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\midinsert \clabel[clock-interconnections]{Grabber binary output format}
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\ctable {lccc}
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{
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Signal	&	FMC signal	&	FMC2DIFF01A	&	ADCdual01A	\cr
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DCO	&	CLK1\_M2C	&	J5-1	&	J13-1	\cr
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FR	&	LA18\_CC	&	J10-1	&	J12-1	\cr
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ENC	&	LA01\_CC	&	J2-1(PECL OUT)	&	J3-1	\cr
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SDGPSDO01A LO	&	CLK0\_M2C	&	J3-1 (PECL IN)	&	N/A	\cr
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}
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\caption/t Clock system interconnections
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\endinsert
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\secc FPGA function
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\secc FPGA function
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Several tasks are performed by FPGA. Firstly FPGA prepares sampling clock for ADCdual01A modules this task is separate block in FPGA and runs asynchronously to other logic. Second block is SPI configuration module, which sends configuration words to ADC modules after opening of Xillybus interface file. Third block is main module, which resolve ADC - PC communication itself. Last block is activated after ADC configuration.
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Several tasks are performed by FPGA. Firstly FPGA prepares sampling clock for ADCdual01A modules this task is separate block in FPGA and runs asynchronously to other logic. Second block is SPI configuration module, which sends configuration words to ADC modules after opening of Xillybus interface file. Third block is main module, which resolve ADC - PC communication itself. Last block is activated after ADC configuration.
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Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which tranfers data from FPGA registers to host PC. Data appears in system device file  "/dev/xillybus_data2_r" on host computer. Binary data which appears in this file after opening are described in table \ref[xillybus-interface].
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Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which tranfers data from FPGA registers to host PC. Data appears in system device file  "/dev/xillybus_data2_r" on host computer. Binary data which appears in this file after opening are described in table \ref[xillybus-interface].